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RedBear-OS/local
vasilito 9e4bf89d24 intel: reimplement CDCLK from Linux 7.1 — full per-gen support
Replaces 155-line Gen9/Xe2-only CDCLK with 300-line comprehensive
implementation covering all supported generations:

SKL/KBL/CFL (Gen9):
  CDCLK programming via CDCLK_CTL register with freq_select + decimal
  4 frequency options: 308.57/337.5/450/432/540/675/617.14 MHz
  VCO decode: 3.2GHz to 6.75GHz per frequency/decimal combination
  Squash vs crawl waveform detection for seamless transitions

TGL/ADL/DG2 (Gen12):
  CDCLK programming via CDCLK_FREQ register
  7 frequency options with 38.4 MHz refclk
  VCO computation: 14.7GHz to 17.3GHz

MTL (Gen12.7):
  4 frequency options: 172.8/307.2/556.8/652.8 MHz

Xe2 (ARL/LNL/BMG):
  DE_CAP register primary, CDCLK_FREQ fallback
  4 frequency options: 307.2/384/556.8/652.8 MHz

CdclkState struct now carries: frequency_khz, vco_khz, refclk_khz,
  voltage_level, waveform
set_frequency() with wait_cdclk_change() polling
required_cdclk() for mode-based frequency selection
2026-06-02 06:32:47 +03:00
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