vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
49 lines
1.4 KiB
TableGen
49 lines
1.4 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
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// Make sure that ReadAdvance entries with multiple writes are correctly
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// handled.
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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let OutOperandList = (outs), InOperandList = (ins) in {
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def Inst_A : Instruction;
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def Inst_B : Instruction;
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def Inst_C : Instruction;
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}
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let CompleteModel = 0 in {
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def SchedModel_A: SchedMachineModel;
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}
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def Read_D : SchedRead;
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def Read_E : SchedRead;
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// CHECK: extern const llvm::MCReadAdvanceEntry MyTargetReadAdvanceTable[] = {
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// CHECK-NEXT: {0, 0, 0}, // Invalid
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// CHECK-NEXT: {0, 1, 1}, // #1
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// CHECK-NEXT: {0, 2, 3}, // #2
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// CHECK-NEXT: {0, 3, 2} // #3
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// CHECK-NEXT: }; // MyTargetReadAdvanceTable
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let SchedModel = SchedModel_A in {
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def Write_A : SchedWriteRes<[]>;
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def Write_B : SchedWriteRes<[]>;
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def Write_C : SchedWriteRes<[]>;
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def : InstRW<[Write_A], (instrs Inst_A)>;
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def : InstRW<[Write_B], (instrs Inst_B)>;
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def : InstRW<[Write_C, Read_D], (instrs Inst_C)>;
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def : ReadAdvance<Read_D, 2, [Write_A, Write_B, Write_C], [-1, 1]>;
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#ifdef ERROR1
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// ERROR1: error: assertion failed: cannot have more `tunables' than `writes'
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def : ReadAdvance<Read_E, 2, [Write_A, Write_B, Write_C], [1, 2, 3, 4]>;
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#endif
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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