vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
200 lines
6.2 KiB
Plaintext
200 lines
6.2 KiB
Plaintext
//===---------------------------------------------------------------------===//
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Common register allocation / spilling problem:
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mul lr, r4, lr
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str lr, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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ldr r4, [sp, #+52]
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mla r4, r3, lr, r4
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can be:
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mul lr, r4, lr
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mov r4, lr
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str lr, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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mla r4, r3, lr, r4
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and then "merge" mul and mov:
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mul r4, r4, lr
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str r4, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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mla r4, r3, lr, r4
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It also increase the likelihood the store may become dead.
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//===---------------------------------------------------------------------===//
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bb27 ...
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...
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%reg1037 = ADDri %reg1039, 1
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%reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
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Successors according to CFG: 0x8b03bf0 (#5)
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bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
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Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
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%reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
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Note ADDri is not a two-address instruction. However, its result %reg1037 is an
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operand of the PHI node in bb76 and its operand %reg1039 is the result of the
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PHI node. We should treat it as a two-address code and make sure the ADDri is
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scheduled after any node that reads %reg1039.
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//===---------------------------------------------------------------------===//
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Use local info (i.e. register scavenger) to assign it a free register to allow
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reuse:
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ldr r3, [sp, #+4]
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add r3, r3, #3
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ldr r2, [sp, #+8]
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add r2, r2, #2
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ldr r1, [sp, #+4] <==
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add r1, r1, #1
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ldr r0, [sp, #+4]
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add r0, r0, #2
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//===---------------------------------------------------------------------===//
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LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
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effects:
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R1 = X + 4
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R2 = X + 7
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R3 = X + 15
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loop:
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load [i + R1]
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...
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load [i + R2]
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...
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load [i + R3]
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Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
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to implement proper re-materialization to handle this:
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R1 = X + 4
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R2 = X + 7
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R3 = X + 15
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loop:
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R1 = X + 4 @ re-materialized
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load [i + R1]
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...
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R2 = X + 7 @ re-materialized
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load [i + R2]
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...
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R3 = X + 15 @ re-materialized
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load [i + R3]
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Furthermore, with re-association, we can enable sharing:
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R1 = X + 4
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R2 = X + 7
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R3 = X + 15
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loop:
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T = i + X
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load [T + 4]
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...
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load [T + 7]
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...
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load [T + 15]
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//===---------------------------------------------------------------------===//
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It's not always a good idea to choose rematerialization over spilling. If all
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the load / store instructions would be folded then spilling is cheaper because
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it won't require new live intervals / registers. See 2003-05-31-LongShifts for
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an example.
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//===---------------------------------------------------------------------===//
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With a copying garbage collector, derived pointers must not be retained across
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collector safe points; the collector could move the objects and invalidate the
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derived pointer. This is bad enough in the first place, but safe points can
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crop up unpredictably. Consider:
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%array = load { i32, [0 x %obj] }** %array_addr
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%nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
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%old = load %obj** %nth_el
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%z = div i64 %x, %y
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store %obj* %new, %obj** %nth_el
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If the i64 division is lowered to a libcall, then a safe point will (must)
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appear for the call site. If a collection occurs, %array and %nth_el no longer
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point into the correct object.
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The fix for this is to copy address calculations so that dependent pointers
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are never live across safe point boundaries. But the loads cannot be copied
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like this if there was an intervening store, so may be hard to get right.
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Only a concurrent mutator can trigger a collection at the libcall safe point.
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So single-threaded programs do not have this requirement, even with a copying
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collector. Still, LLVM optimizations would probably undo a front-end's careful
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work.
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//===---------------------------------------------------------------------===//
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The ocaml frametable structure supports liveness information. It would be good
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to support it.
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//===---------------------------------------------------------------------===//
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The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
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revisited. The check is there to work around a misuse of directives in inline
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assembly.
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//===---------------------------------------------------------------------===//
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It would be good to detect collector/target compatibility instead of silently
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doing the wrong thing.
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//===---------------------------------------------------------------------===//
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It would be really nice to be able to write patterns in .td files for copies,
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which would eliminate a bunch of explicit predicates on them (e.g. no side
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effects). Once this is in place, it would be even better to have tblgen
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synthesize the various copy insertion/inspection methods in TargetInstrInfo.
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//===---------------------------------------------------------------------===//
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Stack coloring improvements:
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1. Do proper LiveStacks analysis on all stack objects including those which are
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not spill slots.
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2. Reorder objects to fill in gaps between objects.
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e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4
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//===---------------------------------------------------------------------===//
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The scheduler should be able to sort nearby instructions by their address. For
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example, in an expanded memset sequence it's not uncommon to see code like this:
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movl $0, 4(%rdi)
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movl $0, 8(%rdi)
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movl $0, 12(%rdi)
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movl $0, 0(%rdi)
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Each of the stores is independent, and the scheduler is currently making an
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arbitrary decision about the order.
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//===---------------------------------------------------------------------===//
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Another opportunitiy in this code is that the $0 could be moved to a register:
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movl $0, 4(%rdi)
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movl $0, 8(%rdi)
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movl $0, 12(%rdi)
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movl $0, 0(%rdi)
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This would save substantial code size, especially for longer sequences like
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this. It would be easy to have a rule telling isel to avoid matching MOV32mi
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if the immediate has more than some fixed number of uses. It's more involved
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to teach the register allocator how to do late folding to recover from
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excessive register pressure.
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