vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
362 lines
16 KiB
Common Lisp
362 lines
16 KiB
Common Lisp
// RUN: %clang_cc1 %s -cl-std=CL2.0 -emit-llvm -O0 -o - -triple=amdgcn-amd-amdhsa \
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// RUN: | FileCheck %s
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// Also test serialization of atomic operations here, to avoid duplicating the test.
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// RUN: %clang_cc1 %s -cl-std=CL2.0 -emit-pch -O0 -o %t -triple=amdgcn-amd-amdhsa
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// RUN: %clang_cc1 %s -cl-std=CL2.0 -include-pch %t -O0 -triple=amdgcn-amd-amdhsa \
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// RUN: -emit-llvm -o - | FileCheck %s
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#ifndef ALREADY_INCLUDED
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#define ALREADY_INCLUDED
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#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable
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#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable
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typedef __INTPTR_TYPE__ intptr_t;
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typedef int int8 __attribute__((ext_vector_type(8)));
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typedef enum memory_order {
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memory_order_relaxed = __ATOMIC_RELAXED,
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memory_order_acquire = __ATOMIC_ACQUIRE,
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memory_order_release = __ATOMIC_RELEASE,
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memory_order_acq_rel = __ATOMIC_ACQ_REL,
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memory_order_seq_cst = __ATOMIC_SEQ_CST
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} memory_order;
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typedef enum memory_scope {
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memory_scope_work_item = __OPENCL_MEMORY_SCOPE_WORK_ITEM,
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memory_scope_work_group = __OPENCL_MEMORY_SCOPE_WORK_GROUP,
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memory_scope_device = __OPENCL_MEMORY_SCOPE_DEVICE,
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memory_scope_all_svm_devices = __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES,
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#if defined(cl_intel_subgroups) || defined(cl_khr_subgroups)
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memory_scope_sub_group = __OPENCL_MEMORY_SCOPE_SUB_GROUP
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#endif
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} memory_scope;
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atomic_int j;
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void fi1(atomic_int *i) {
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// CHECK-LABEL: @fi1
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// CHECK: load atomic i32, ptr %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4{{$}}
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int x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: load atomic i32, ptr %{{[.0-9A-Z_a-z]+}} syncscope("agent") seq_cst, align 4{{$}}
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x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_device);
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// CHECK: load atomic i32, ptr %{{[.0-9A-Z_a-z]+}} seq_cst, align 4{{$}}
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x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_all_svm_devices);
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// CHECK: load atomic i32, ptr %{{[.0-9A-Z_a-z]+}} syncscope("wavefront") seq_cst, align 4{{$}}
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x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_sub_group);
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}
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void fi2(atomic_int *i) {
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// CHECK-LABEL: @fi2
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// CHECK: store atomic i32 %{{[.0-9A-Z_a-z]+}}, ptr %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4{{$}}
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__opencl_atomic_store(i, 1, memory_order_seq_cst, memory_scope_work_group);
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}
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void test_addr(global atomic_int *ig, private atomic_int *ip, local atomic_int *il) {
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// CHECK-LABEL: @test_addr
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// CHECK: store atomic i32 %{{[.0-9A-Z_a-z]+}}, ptr addrspace(1) %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4{{$}}
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__opencl_atomic_store(ig, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: store atomic i32 %{{[.0-9A-Z_a-z]+}}, ptr addrspace(5) %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4{{$}}
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__opencl_atomic_store(ip, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: store atomic i32 %{{[.0-9A-Z_a-z]+}}, ptr addrspace(3) %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4{{$}}
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__opencl_atomic_store(il, 1, memory_order_seq_cst, memory_scope_work_group);
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}
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void fi3(atomic_int *i, atomic_uint *ui) {
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// CHECK-LABEL: @fi3
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// CHECK: atomicrmw and ptr %{{[.0-9A-Z_a-z]+}}, i32 %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE:![0-9]+]], [[$DEFMD:!amdgpu.no.fine.grained.memory ![0-9]+, !amdgpu.no.remote.memory ![0-9]+$]]
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int x = __opencl_atomic_fetch_and(i, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: atomicrmw min ptr %{{[.0-9A-Z_a-z]+}}, i32 %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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x = __opencl_atomic_fetch_min(i, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: atomicrmw max ptr %{{[.0-9A-Z_a-z]+}}, i32 %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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x = __opencl_atomic_fetch_max(i, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: atomicrmw umin ptr %{{[.0-9A-Z_a-z]+}}, i32 %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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x = __opencl_atomic_fetch_min(ui, 1, memory_order_seq_cst, memory_scope_work_group);
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// CHECK: atomicrmw umax ptr %{{[.0-9A-Z_a-z]+}}, i32 %{{[.0-9A-Z_a-z]+}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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x = __opencl_atomic_fetch_max(ui, 1, memory_order_seq_cst, memory_scope_work_group);
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}
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bool fi4(atomic_int *i) {
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// CHECK-LABEL: @fi4(
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// CHECK: [[PAIR:%[.0-9A-Z_a-z]+]] = cmpxchg ptr [[PTR:%[.0-9A-Z_a-z]+]], i32 [[EXPECTED:%[.0-9A-Z_a-z]+]], i32 [[DESIRED:%[.0-9A-Z_a-z]+]] syncscope("workgroup-one-as") acquire acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: [[OLD:%[.0-9A-Z_a-z]+]] = extractvalue { i32, i1 } [[PAIR]], 0
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// CHECK: [[CMP:%[.0-9A-Z_a-z]+]] = extractvalue { i32, i1 } [[PAIR]], 1
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// CHECK: br i1 [[CMP]], label %[[STORE_EXPECTED:[.0-9A-Z_a-z]+]], label %[[CONTINUE:[.0-9A-Z_a-z]+]]
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// CHECK: store i32 [[OLD]]
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int cmp = 0;
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return __opencl_atomic_compare_exchange_strong(i, &cmp, 1, memory_order_acquire, memory_order_acquire, memory_scope_work_group);
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}
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void fi5(atomic_int *i, int scope) {
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// CHECK-LABEL: @fi5
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// CHECK: switch i32 %{{.*}}, label %[[opencl_allsvmdevices:.*]] [
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// CHECK-NEXT: i32 1, label %[[opencl_workgroup:.*]]
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// CHECK-NEXT: i32 2, label %[[opencl_device:.*]]
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// CHECK-NEXT: i32 4, label %[[opencl_subgroup:.*]]
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// CHECK-NEXT: ]
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// CHECK: [[opencl_workgroup]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("workgroup") seq_cst, align 4{{$}}
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// CHECK: br label %[[continue:.*]]
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// CHECK: [[opencl_device]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("agent") seq_cst, align 4{{$}}
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// CHECK: br label %[[continue]]
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// CHECK: [[opencl_allsvmdevices]]:
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// CHECK: load atomic i32, ptr %{{.*}} seq_cst, align 4
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// CHECK: br label %[[continue]]
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// CHECK: [[opencl_subgroup]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("wavefront") seq_cst, align 4{{$}}
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// CHECK: br label %[[continue]]
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// CHECK: [[continue]]:
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int x = __opencl_atomic_load(i, memory_order_seq_cst, scope);
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}
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void fi6(atomic_int *i, int order, int scope) {
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// CHECK-LABEL: @fi6
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// CHECK: switch i32 %{{.*}}, label %[[monotonic:.*]] [
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// CHECK-NEXT: i32 1, label %[[acquire:.*]]
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// CHECK-NEXT: i32 2, label %[[acquire:.*]]
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// CHECK-NEXT: i32 5, label %[[seqcst:.*]]
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// CHECK-NEXT: ]
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// CHECK: [[monotonic]]:
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// CHECK: switch i32 %{{.*}}, label %[[MON_ALL:.*]] [
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// CHECK-NEXT: i32 1, label %[[MON_WG:.*]]
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// CHECK-NEXT: i32 2, label %[[MON_DEV:.*]]
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// CHECK-NEXT: i32 4, label %[[MON_SUB:.*]]
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// CHECK-NEXT: ]
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// CHECK: [[acquire]]:
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// CHECK: switch i32 %{{.*}}, label %[[ACQ_ALL:.*]] [
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// CHECK-NEXT: i32 1, label %[[ACQ_WG:.*]]
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// CHECK-NEXT: i32 2, label %[[ACQ_DEV:.*]]
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// CHECK-NEXT: i32 4, label %[[ACQ_SUB:.*]]
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// CHECK-NEXT: ]
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// CHECK: [[seqcst]]:
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// CHECK: switch i32 %{{.*}}, label %[[SEQ_ALL:.*]] [
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// CHECK-NEXT: i32 1, label %[[SEQ_WG:.*]]
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// CHECK-NEXT: i32 2, label %[[SEQ_DEV:.*]]
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// CHECK-NEXT: i32 4, label %[[SEQ_SUB:.*]]
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// CHECK-NEXT: ]
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// CHECK: [[MON_WG]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("workgroup-one-as") monotonic, align 4{{$}}
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// CHECK: [[MON_DEV]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("agent-one-as") monotonic, align 4{{$}}
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// CHECK: [[MON_ALL]]:
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// CHECK: load atomic i32, ptr %{{.*}} monotonic, align 4{{$}}
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// CHECK: [[MON_SUB]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("wavefront-one-as") monotonic, align 4{{$}}
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// CHECK: [[ACQ_WG]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("workgroup-one-as") acquire, align 4{{$}}
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// CHECK: [[ACQ_DEV]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("agent-one-as") acquire, align 4{{$}}
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// CHECK: [[ACQ_ALL]]:
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// CHECK: load atomic i32, ptr %{{.*}} acquire, align 4{{$}}
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// CHECK: [[ACQ_SUB]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("wavefront-one-as") acquire, align 4{{$}}
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// CHECK: [[SEQ_WG]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("workgroup") seq_cst, align 4{{$}}
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// CHECK: [[SEQ_DEV]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("agent") seq_cst, align 4{{$}}
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// CHECK: [[SEQ_ALL]]:
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// CHECK: load atomic i32, ptr %{{.*}} seq_cst, align 4{{$}}
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// CHECK: [[SEQ_SUB]]:
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// CHECK: load atomic i32, ptr %{{.*}} syncscope("wavefront") seq_cst, align 4{{$}}
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int x = __opencl_atomic_load(i, order, scope);
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}
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float ff1(global atomic_float *d) {
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// CHECK-LABEL: @ff1
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// CHECK: load atomic i32, ptr addrspace(1) {{.*}} syncscope("workgroup-one-as") monotonic, align 4{{$}}
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return __opencl_atomic_load(d, memory_order_relaxed, memory_scope_work_group);
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}
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void ff2(atomic_float *d) {
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// CHECK-LABEL: @ff2
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// CHECK: store atomic i32 {{.*}} syncscope("workgroup-one-as") release, align 4
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__opencl_atomic_store(d, 1, memory_order_release, memory_scope_work_group);
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}
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float ff3(atomic_float *d) {
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// CHECK-LABEL: @ff3
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// CHECK: atomicrmw xchg ptr {{.*}} syncscope("workgroup") seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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return __opencl_atomic_exchange(d, 2, memory_order_seq_cst, memory_scope_work_group);
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}
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float ff4(global atomic_float *d, float a) {
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// CHECK-LABEL: @ff4
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// CHECK: atomicrmw fadd ptr addrspace(1) {{.*}} syncscope("workgroup-one-as") monotonic, align 4, [[$DEFMD]]
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return __opencl_atomic_fetch_add(d, a, memory_order_relaxed, memory_scope_work_group);
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}
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float ff5(global atomic_double *d, double a) {
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// CHECK-LABEL: @ff5
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// CHECK: atomicrmw fadd ptr addrspace(1) {{.*}} syncscope("workgroup-one-as") monotonic, align 8, [[$DEFMD]]
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return __opencl_atomic_fetch_add(d, a, memory_order_relaxed, memory_scope_work_group);
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}
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float ff4_generic(atomic_float *d, float a) {
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// CHECK-LABEL: @ff4_generic
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// CHECK: atomicrmw fadd ptr {{.*}} syncscope("workgroup-one-as") monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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return __opencl_atomic_fetch_add(d, a, memory_order_relaxed, memory_scope_work_group);
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}
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float ff5_generic(atomic_double *d, double a) {
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// CHECK-LABEL: @ff5_generic
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// CHECK: atomicrmw fadd ptr {{.*}} syncscope("workgroup-one-as") monotonic, align 8, !noalias.addrspace [[$NOPRIVATE]], [[$DEFMD]]
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return __opencl_atomic_fetch_add(d, a, memory_order_relaxed, memory_scope_work_group);
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}
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// CHECK-LABEL: @atomic_init_foo
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void atomic_init_foo()
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{
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// CHECK-NOT: atomic
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// CHECK: store
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__opencl_atomic_init(&j, 42);
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// CHECK-NOT: atomic
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// CHECK: }
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}
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// CHECK-LABEL: @failureOrder
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void failureOrder(atomic_int *ptr, int *ptr2) {
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// CHECK: cmpxchg ptr {{%[0-9A-Za-z._]+}}, i32 {{%[0-9A-Za-z._]+}}, i32 {{%[0-9A-Za-z_.]+}} syncscope("workgroup-one-as") acquire monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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__opencl_atomic_compare_exchange_strong(ptr, ptr2, 43, memory_order_acquire, memory_order_relaxed, memory_scope_work_group);
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// CHECK: cmpxchg weak ptr {{%[0-9A-Za-z._]+}}, i32 {{%[0-9A-Za-z._]+}}, i32 {{%[0-9A-Za-z_.]+}} syncscope("workgroup") seq_cst acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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__opencl_atomic_compare_exchange_weak(ptr, ptr2, 43, memory_order_seq_cst, memory_order_acquire, memory_scope_work_group);
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}
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// CHECK-LABEL: @generalFailureOrder
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void generalFailureOrder(atomic_int *ptr, int *ptr2, int success, int fail) {
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__opencl_atomic_compare_exchange_strong(ptr, ptr2, 42, success, fail, memory_scope_work_group);
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// CHECK: switch i32 {{.*}}, label %[[MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[ACQUIRE]]
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// CHECK-NEXT: i32 3, label %[[RELEASE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 4, label %[[ACQREL:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 5, label %[[SEQCST:[0-9a-zA-Z._]+]]
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// CHECK: [[MONOTONIC]]
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// CHECK: switch {{.*}}, label %[[MONOTONIC_MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[MONOTONIC_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[MONOTONIC_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 5, label %[[MONOTONIC_SEQCST:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: ]
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// CHECK: [[ACQUIRE]]
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// CHECK: switch {{.*}}, label %[[ACQUIRE_MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[ACQUIRE_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[ACQUIRE_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 5, label %[[ACQUIRE_SEQCST:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: ]
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// CHECK: [[RELEASE]]
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// CHECK: switch {{.*}}, label %[[RELEASE_MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[RELEASE_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[RELEASE_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 5, label %[[RELEASE_SEQCST:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: ]
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// CHECK: [[ACQREL]]
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// CHECK: switch {{.*}}, label %[[ACQREL_MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[ACQREL_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[ACQREL_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 5, label %[[ACQREL_SEQCST:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: ]
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// CHECK: [[SEQCST]]
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// CHECK: switch {{.*}}, label %[[SEQCST_MONOTONIC:[0-9a-zA-Z._]+]] [
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// CHECK-NEXT: i32 1, label %[[SEQCST_ACQUIRE:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: i32 2, label %[[SEQCST_ACQUIRE]]
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// CHECK-NEXT: i32 5, label %[[SEQCST_SEQCST:[0-9a-zA-Z._]+]]
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// CHECK-NEXT: ]
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// CHECK: [[MONOTONIC_MONOTONIC]]
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// CHECK: cmpxchg {{.*}} monotonic monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[MONOTONIC_ACQUIRE]]
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// CHECK: cmpxchg {{.*}} monotonic acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[MONOTONIC_SEQCST]]
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// CHECK: cmpxchg {{.*}} monotonic seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQUIRE_MONOTONIC]]
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// CHECK: cmpxchg {{.*}} acquire monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQUIRE_ACQUIRE]]
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// CHECK: cmpxchg {{.*}} acquire acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQUIRE_SEQCST]]
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// CHECK: cmpxchg {{.*}} acquire seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[RELEASE_MONOTONIC]]
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// CHECK: cmpxchg {{.*}} release monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[RELEASE_ACQUIRE]]
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// CHECK: cmpxchg {{.*}} release acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[RELEASE_SEQCST]]
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// CHECK: cmpxchg {{.*}} release seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQREL_MONOTONIC]]
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// CHECK: cmpxchg {{.*}} acq_rel monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQREL_ACQUIRE]]
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// CHECK: cmpxchg {{.*}} acq_rel acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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// CHECK: [[ACQREL_SEQCST]]
|
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// CHECK: cmpxchg {{.*}} acq_rel seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
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// CHECK: br
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|
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// CHECK: [[SEQCST_MONOTONIC]]
|
|
// CHECK: cmpxchg {{.*}} seq_cst monotonic, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
|
|
// CHECK: br
|
|
|
|
// CHECK: [[SEQCST_ACQUIRE]]
|
|
// CHECK: cmpxchg {{.*}} seq_cst acquire, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
|
|
// CHECK: br
|
|
|
|
// CHECK: [[SEQCST_SEQCST]]
|
|
// CHECK: cmpxchg {{.*}} seq_cst seq_cst, align 4, !noalias.addrspace [[$NOPRIVATE]]{{$}}
|
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// CHECK: br
|
|
}
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|
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|
int test_volatile(volatile atomic_int *i) {
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|
// CHECK-LABEL: @test_volatile
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// CHECK: %[[i_addr:.*]] = alloca ptr
|
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// CHECK-NEXT: %[[atomicdst:.*]] = alloca i32
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// CHECK-NEXT: %[[retval_ascast:.*]] = addrspacecast ptr addrspace(5) {{.*}} to ptr
|
|
// CHECK-NEXT: %[[i_addr_ascast:.*]] = addrspacecast ptr addrspace(5) %[[i_addr]] to ptr
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// CHECK-NEXT: %[[atomicdst_ascast:.*]] = addrspacecast ptr addrspace(5) %[[atomicdst]] to ptr
|
|
// CHECK-NEXT: store ptr %i, ptr %[[i_addr_ascast]]
|
|
// CHECK-NEXT: %[[addr:.*]] = load ptr, ptr %[[i_addr_ascast]]
|
|
// CHECK-NEXT: %[[res:.*]] = load atomic volatile i32, ptr %[[addr]] syncscope("workgroup") seq_cst, align 4{{$}}
|
|
// CHECK-NEXT: store i32 %[[res]], ptr %[[atomicdst_ascast]]
|
|
// CHECK-NEXT: %[[retval:.*]] = load i32, ptr %[[atomicdst_ascast]]
|
|
// CHECK-NEXT: ret i32 %[[retval]]
|
|
return __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group);
|
|
}
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|
|
|
#endif
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// CHECK: [[$NOPRIVATE]] = !{i32 5, i32 6}
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