vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
80 lines
4.4 KiB
Common Lisp
80 lines
4.4 KiB
Common Lisp
// RUN: %clang_cc1 < %s -cl-std=CL2.0 -triple spir64 -emit-llvm | FileCheck -check-prefix=SPIR %s
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// RUN: %clang_cc1 < %s -cl-std=CL2.0 -triple armv5e-none-linux-gnueabi -emit-llvm | FileCheck -check-prefix=ARM %s
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typedef enum memory_order {
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memory_order_relaxed = __ATOMIC_RELAXED,
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memory_order_acquire = __ATOMIC_ACQUIRE,
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memory_order_release = __ATOMIC_RELEASE,
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memory_order_acq_rel = __ATOMIC_ACQ_REL,
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memory_order_seq_cst = __ATOMIC_SEQ_CST
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} memory_order;
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typedef enum memory_scope {
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memory_scope_work_item = __OPENCL_MEMORY_SCOPE_WORK_ITEM,
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memory_scope_work_group = __OPENCL_MEMORY_SCOPE_WORK_GROUP,
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memory_scope_device = __OPENCL_MEMORY_SCOPE_DEVICE,
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memory_scope_all_svm_devices = __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES,
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#if defined(cl_intel_subgroups) || defined(cl_khr_subgroups)
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memory_scope_sub_group = __OPENCL_MEMORY_SCOPE_SUB_GROUP
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#endif
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} memory_scope;
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void f(atomic_int *i, global atomic_int *gi, local atomic_int *li, private atomic_int *pi, atomic_uint *ui, int cmp, int order, int scope) {
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int x;
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// SPIR: load atomic i32, ptr addrspace(4) {{.*}} seq_cst, align 4
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// ARM: load atomic i32, ptr {{.*}} seq_cst, align 4
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x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: store atomic i32 {{.*}}, ptr addrspace(4) {{.*}} seq_cst, align 4
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// ARM: store atomic i32 {{.*}}, ptr {{.*}} seq_cst, align 4
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__opencl_atomic_store(i, 1, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: store atomic i32 {{.*}}, ptr addrspace(1) {{.*}} seq_cst, align 4
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// ARM: store atomic i32 {{.*}}, ptr {{.*}} seq_cst, align 4
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__opencl_atomic_store(gi, 1, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: store atomic i32 {{.*}}, ptr addrspace(3) {{.*}} seq_cst, align 4
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// ARM: store atomic i32 {{.*}}, ptr {{.*}} seq_cst, align 4
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__opencl_atomic_store(li, 1, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: store atomic i32 {{.*}}, ptr {{.*}} seq_cst, align 4
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// ARM: store atomic i32 {{.*}}, ptr {{.*}} seq_cst, align 4
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__opencl_atomic_store(pi, 1, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: atomicrmw add ptr addrspace(4) {{.*}}, i32 {{.*}} seq_cst, align 4
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// ARM: atomicrmw add ptr {{.*}}, i32 {{.*}} seq_cst, align 4
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x = __opencl_atomic_fetch_add(i, 3, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: atomicrmw min ptr addrspace(4) {{.*}}, i32 {{.*}} seq_cst, align 4
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// ARM: atomicrmw min ptr {{.*}}, i32 {{.*}} seq_cst, align 4
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x = __opencl_atomic_fetch_min(i, 3, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: atomicrmw umin ptr addrspace(4) {{.*}}, i32 {{.*}} seq_cst, align 4
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// ARM: atomicrmw umin ptr {{.*}}, i32 {{.*}} seq_cst, align 4
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x = __opencl_atomic_fetch_min(ui, 3, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: cmpxchg ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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// ARM: cmpxchg ptr {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_strong(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: cmpxchg weak ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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// ARM: cmpxchg weak ptr {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group);
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// SPIR: cmpxchg weak ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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// ARM: cmpxchg weak ptr {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_device);
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// SPIR: cmpxchg weak ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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// ARM: cmpxchg weak ptr {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_all_svm_devices);
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#ifdef cl_khr_subgroups
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// SPIR: cmpxchg weak ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_sub_group);
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#endif
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// SPIR: cmpxchg weak ptr addrspace(4) {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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// ARM: cmpxchg weak ptr {{.*}}, i32 {{.*}}, i32 {{.*}} seq_cst seq_cst, align 4
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x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, order, order, scope);
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}
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