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RedBear-OS/local/recipes/dev/libclc/source/clang/test/CodeGen/attr-target-version-riscv.c
T
vasilito cb424d7448 build: static patch-sanity linter (shift-left the malformed-patch class) 
verify-patch-sanity.py validates every active recipe .patch has internally-
consistent hunk line counts — catching the 'malformed patch at line N' failure
at commit/CI/preflight time instead of hours into a cook. This cycle hit that
class three times (qtwaylandscanner, sddm, xwayland), each only discovered when
cookbook tried to apply the patch.

Running it across the repo found 29 latent malformed patches (validated against
GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22').
They were harmless only because they sit in vendored recipes (baked, not re-
applied) — but would fail on any version-bump re-derivation. --fix recounts the
hunk headers (body untouched) and repaired all 29.

Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test
(test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats
(empty placeholders, bare-@@ git hunks).
2026-08-01 05:13:02 +03:00

385 lines
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s
__attribute__((target_version("arch=+v"))) int foo1(void) { return 1; }
__attribute__((target_version("default"))) int foo1(void) { return 1; }
__attribute__((target_version("arch=+zbb"))) int foo2(void) { return 1; }
__attribute__((target_version("arch=+m"))) int foo2(void) { return 1; }
__attribute__((target_version("default"))) int foo2(void) { return 1; }
__attribute__((target_version("arch=+zbb,+c"))) int foo3(void) { return 1; }
__attribute__((target_version("arch=+m"))) int foo3(void) { return 1; }
__attribute__((target_version("default"))) int foo3(void) { return 1; }
__attribute__((target_version("arch=+zba"))) int foo4(void) { return 1; }
__attribute__((target_version("arch=+zbb"))) int foo4(void) { return 1; }
__attribute__((target_version("arch=+zbb,+zba"))) int foo4(void) { return 1; }
__attribute__((target_version("default"))) int foo4(void) { return 1; }
__attribute__((target_version("arch=+zba"))) int foo5(void) { return 1; }
__attribute__((target_version("arch=+zbb,+zba"))) int foo5(void) { return 1; }
__attribute__((target_version("arch=+zbb"))) int foo5(void) { return 1; }
__attribute__((target_version("default"))) int foo5(void) { return 1; }
__attribute__((target_version("arch=+zba"))) int foo6(void) { return 1; }
__attribute__((target_version("arch=+zbb"))) int foo6(void) { return 1; }
__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo6(void) { return 1; }
__attribute__((target_version("default"))) int foo6(void) { return 1; }
__attribute__((target_version("priority=8;arch=+zba"))) int foo7(void) { return 1; }
__attribute__((target_version("arch=+zbb;priority=9"))) int foo7(void) { return 1; }
__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo7(void) { return 1; }
__attribute__((target_version("default"))) int foo7(void) { return 1; }
int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); }
//.
// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
// CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver
// CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver
//.
// CHECK-LABEL: define dso_local signext i32 @foo1._v(
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2097152
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2097152
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo1._v
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @foo1.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo1.default(
// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo2._zbb(
// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo2._zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo2._m
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @foo2.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo2._m(
// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo2.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb(
// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo3._c_zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo3._m
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @foo3.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo3._m(
// CHECK-SAME: ) #[[ATTR3]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo3.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo4._zba(
// CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo4._zba
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo4._zbb
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
// CHECK: resolver_return3:
// CHECK-NEXT: ret ptr @foo4._zba_zbb
// CHECK: resolver_else4:
// CHECK-NEXT: ret ptr @foo4.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo4._zbb(
// CHECK-SAME: ) #[[ATTR2]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo4._zba_zbb(
// CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo4.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo5._zba(
// CHECK-SAME: ) #[[ATTR5]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo5._zba
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 402653184
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 402653184
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo5._zba_zbb
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
// CHECK: resolver_return3:
// CHECK-NEXT: ret ptr @foo5._zbb
// CHECK: resolver_else4:
// CHECK-NEXT: ret ptr @foo5.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo5._zba_zbb(
// CHECK-SAME: ) #[[ATTR6]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo5._zbb(
// CHECK-SAME: ) #[[ATTR2]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo5.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo6._zba(
// CHECK-SAME: ) #[[ATTR5]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo6._zba_zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo6._zba
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
// CHECK: resolver_return3:
// CHECK-NEXT: ret ptr @foo6._zbb
// CHECK: resolver_else4:
// CHECK-NEXT: ret ptr @foo6.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo6._zbb(
// CHECK-SAME: ) #[[ATTR2]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo6._zba_zbb(
// CHECK-SAME: ) #[[ATTR6]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo6.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo7._zba(
// CHECK-SAME: ) #[[ATTR5]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define weak_odr ptr @foo7.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo7._zba_zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo7._zbb
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
// CHECK: resolver_return3:
// CHECK-NEXT: ret ptr @foo7._zba
// CHECK: resolver_else4:
// CHECK-NEXT: ret ptr @foo7.default
//
//
// CHECK-LABEL: define dso_local signext i32 @foo7._zbb(
// CHECK-SAME: ) #[[ATTR2]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb(
// CHECK-SAME: ) #[[ATTR6]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @foo7.default(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK-LABEL: define dso_local signext i32 @bar(
// CHECK-SAME: ) #[[ATTR1]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1()
// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2()
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3()
// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4()
// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5()
// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
// CHECK-NEXT: [[CALL8:%.*]] = call signext i32 @foo6()
// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
// CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7()
// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
// CHECK-NEXT: ret i32 [[ADD11]]
//
//.
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb,+zca" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba,+zbb" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
// CHECK: [[META3]] = !{!"rv64i2p1"}
// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
//.
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