vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
179 lines
7.8 KiB
C
179 lines
7.8 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \
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// RUN: -target-feature +cdecp0 -target-feature +cdecp1 \
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// RUN: -target-feature +mve.fp \
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// RUN: -mfloat-abi hard -O0 -disable-O0-optnone \
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// RUN: -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_cde.h>
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// CHECK-LABEL: @test_vcx1q_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
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// CHECK-NEXT: ret <16 x i8> [[TMP0]]
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//
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uint8x16_t test_vcx1q_u8(void) {
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return __arm_vcx1q_u8(0, 1111);
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}
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// CHECK-LABEL: @test_vcx1qa_1(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> [[ACC:%.*]], i32 1112)
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// CHECK-NEXT: ret <16 x i8> [[TMP0]]
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//
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uint8x16_t test_vcx1qa_1(uint8x16_t acc) {
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return __arm_vcx1qa(1, acc, 1112);
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}
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// CHECK-LABEL: @test_vcx1qa_2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[ACC:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> [[TMP0]], i32 1113)
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// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
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// CHECK-NEXT: ret <4 x i32> [[TMP2]]
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//
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int32x4_t test_vcx1qa_2(int32x4_t acc) {
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return __arm_vcx1qa(0, acc, 1113);
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}
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// CHECK-LABEL: @test_vcx2q_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 111)
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// CHECK-NEXT: ret <16 x i8> [[TMP1]]
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//
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uint8x16_t test_vcx2q_u8(float16x8_t n) {
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return __arm_vcx2q_u8(1, n, 111);
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}
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// CHECK-LABEL: @test_vcx2q(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> [[TMP0]], i32 112)
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// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
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// CHECK-NEXT: ret <4 x float> [[TMP2]]
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//
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float32x4_t test_vcx2q(float32x4_t n) {
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return __arm_vcx2q(1, n, 112);
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}
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// CHECK-LABEL: @test_vcx2qa(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[ACC:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 113)
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// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
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// CHECK-NEXT: ret <4 x float> [[TMP3]]
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//
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float32x4_t test_vcx2qa(float32x4_t acc, int64x2_t n) {
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return __arm_vcx2qa(0, acc, n, 113);
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}
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// CHECK-LABEL: @test_vcx3q_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 11)
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// CHECK-NEXT: ret <16 x i8> [[TMP2]]
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//
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uint8x16_t test_vcx3q_u8(uint16x8_t n, int32x4_t m) {
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return __arm_vcx3q_u8(0, n, m, 11);
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}
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// CHECK-LABEL: @test_vcx3q(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12)
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// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
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// CHECK-NEXT: ret <2 x i64> [[TMP3]]
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//
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uint64x2_t test_vcx3q(uint64x2_t n, float32x4_t m) {
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return __arm_vcx3q(1, n, m, 12);
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}
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// CHECK-LABEL: @test_vcx3qa(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[M:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> [[ACC:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 13)
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// CHECK-NEXT: ret <16 x i8> [[TMP2]]
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//
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int8x16_t test_vcx3qa(int8x16_t acc, uint16x8_t n, float32x4_t m) {
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return __arm_vcx3qa(1, acc, n, m, 13);
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}
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// CHECK-LABEL: @test_vcx1q_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], i32 1111, <8 x i1> [[TMP1]])
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// CHECK-NEXT: ret <8 x i16> [[TMP2]]
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//
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uint16x8_t test_vcx1q_m(uint16x8_t inactive, mve_pred16_t p) {
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return __arm_vcx1q_m(0, inactive, 1111, p);
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}
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// CHECK-LABEL: @test_vcx1qa_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> [[ACC:%.*]], i32 1112, <16 x i1> [[TMP1]])
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// CHECK-NEXT: ret <16 x i8> [[TMP2]]
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//
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uint8x16_t test_vcx1qa_m(uint8x16_t acc, mve_pred16_t p) {
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return __arm_vcx1qa_m(1, acc, 1112, p);
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}
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// CHECK-LABEL: @test_vcx2q_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], i32 111, <4 x i1> [[TMP2]])
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// CHECK-NEXT: ret <4 x i32> [[TMP3]]
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//
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int32x4_t test_vcx2q_m(int32x4_t inactive, float32x4_t n, mve_pred16_t p) {
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return __arm_vcx2q_m(0, inactive, n, 111, p);
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}
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// CHECK-LABEL: @test_vcx2qa_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> [[ACC:%.*]], <16 x i8> [[TMP0]], i32 112, <4 x i1> [[TMP2]])
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// CHECK-NEXT: ret <4 x float> [[TMP3]]
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//
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float32x4_t test_vcx2qa_m(float32x4_t acc, float16x8_t n, mve_pred16_t p) {
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return __arm_vcx2qa_m(0, acc, n, 112, p);
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}
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// CHECK-LABEL: @test_vcx3q_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.arm.cde.vcx3q.predicated.v2i64.v2i1(i32 1, <2 x i64> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[M:%.*]], i32 11, <2 x i1> [[TMP2]])
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// CHECK-NEXT: ret <2 x i64> [[TMP3]]
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//
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int64x2_t test_vcx3q_m(int64x2_t inactive, float32x4_t n, int8x16_t m, mve_pred16_t p) {
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return __arm_vcx3q_m(1, inactive, n, m, 11, p);
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}
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// CHECK-LABEL: @test_vcx3qa_m(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[N:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[M:%.*]] to <16 x i8>
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// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.arm.cde.vcx3qa.predicated.v4f32.v4i1(i32 1, <4 x float> [[INACTIVE:%.*]], <16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 12, <4 x i1> [[TMP3]])
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// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x float> [[TMP4]] to <8 x half>
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// CHECK-NEXT: ret <8 x half> [[TMP5]]
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//
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float16x8_t test_vcx3qa_m(float32x4_t inactive, float16x8_t n, uint32x4_t m, mve_pred16_t p) {
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return __arm_vcx3qa_m(1, inactive, n, m, 12, p);
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}
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