vasilito
e1f30d2cca
- Complete PCI enumeration (class 0x0C, subclass 0x03, prog-if 0x00) - I/O port register access (inb/outb style via volatile ptr) - BAR4: I/O port range for operational registers (USBCMD, USBSTS, etc.) - MMIO-mapped FLBASEADD for frame list base address - 1024-entry frame list with QH pointers - Control QH chain for transfer scheduling - Full controller reset and initialization sequence - Port polling with connect/disconnect detection - Device enumeration via control transfers (GET_DESCRIPTOR, SET_ADDRESS) - Port reset with proper timing (50ms hold, 10ms settle) - Transfer descriptor (TD) construction for setup/data/status phases - Wait-for-completion loop with error detection - All registers documented in registers.rs per UHCI spec - Scheme interface for scheme:usb access
base
@ dc04956a31
bootloader
@ c7cdcb5d25
installer
@ 101a836a92
kernel
@ 4b3f6e3e81
relibc
@ d7115781bf