vasilito a5577c0602 intel: Gen12 register table + DBUF registers (Phase 2) ...

Add regs_gen12.rs implementing IntelRegs trait for Gen12 (TGL/ADL)
and Gen12_7 (MTL/ARL) display engines. Gen12 shares most display
register offsets with Gen9 but has different forcewake and DMC.

- Gen12Regs: same pipe/plane/DDI/cursor/vblank offsets as Gen9
  but with Gen12 forcewake (0xa188/0xdfc) and DMC (0x80000+)
- Gen12DisplayRegs: Gen12-specific display registers:
  TRANS_DDI_FUNC_CTL (0x60400) — separate transcoder control
  DBUF_CTL_S1/S2 (0x45008/0x4500C) — display buffer slices
  PLANE_CTL/SURF/STRIDE at standard plane offsets

Update mod.rs generation selector: Gen12/Gen12_7 → Gen12Regs.
Xe2 continues to use Xe2Regs, Gen9 uses Gen9Regs.

Linux reference: intel_display_regs.h, xe_gt_regs.h

2026-05-30 09:00:03 +03:00

..

base @ 12eb4be1c7

intel: multi-generation power wells — Gen9 + Xe2

2026-05-30 08:22:43 +03:00

bootloader @ 4a678bab27

intel: Gen12 register table + DBUF registers (Phase 2)

2026-05-30 09:00:03 +03:00

installer @ 101a836a92

migrate: apply remaining patches to source forks, clean up

2026-05-29 22:48:03 +03:00

kernel @ 866dfad0af

migrate: restore fork repos from properly patched release archives

2026-05-29 23:07:54 +03:00

relibc @ 861bbb024a

migrate: restore fork repos from properly patched release archives

2026-05-29 23:07:54 +03:00