7f8f93146d
fbc.rs: Frame Buffer Compression FBC_CTL enable/compression/fence programming (Gen7+) FBC_STATUS compressed buffer tracking nuke() for frontbuffer invalidation on render drrs.rs: Display Refresh Rate Switching Transitions high→low refresh rate on idle timeout DRRS_CTL with idle frame count configuration mark_active() for compositor interaction psr2.rs: Panel Self Refresh v2 Selective update via sink DPCD capability probe PSR2_MAN_TRK_CTL for partial frame update tracking DP_PSR2_SUPPORT/EN_CFG2 sink communication regs_gen4_7.rs: Pre-Gen9 FDI register definitions Gen4-7 pipe/plane/DDI registers (PIPEACONF, DSPACNTR) GMBUS at 0x5100 base (pre-PCH offset) No DDI_BUF_CTL — these platforms use FDI display mod.rs: Wired FbcState, DrrsState alongside existing PsrState