vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
617 lines
23 KiB
C++
617 lines
23 KiB
C++
//===- MachineInstrTest.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/TargetParser/Triple.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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// Include helper functions to ease the manipulation of MachineFunctions.
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#include "MFCommon.inc"
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std::unique_ptr<MCContext> createMCContext(MCAsmInfo *AsmInfo) {
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Triple TheTriple(/*ArchStr=*/"", /*VendorStr=*/"", /*OSStr=*/"",
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/*EnvironmentStr=*/"elf");
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return std::make_unique<MCContext>(TheTriple, AsmInfo, nullptr, nullptr,
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nullptr, nullptr, false);
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}
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// This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
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// for various combinations of IgnoreDefs, and also that it is symmetrical.
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TEST(IsIdenticalToTest, DifferentDefs) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo[2];
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} Table = {
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{0, NumOps, NumDefs, 0, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef, 0},
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{{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}};
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// Create two MIs with different virtual reg defs and the same uses.
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unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
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unsigned VirtualDef2 = -43;
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unsigned VirtualUse = -44;
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auto MI1 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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auto MI2 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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// Check that they are identical when we ignore virtual register defs, but not
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// when we check defs.
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ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
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ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
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ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
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// Create two MIs with different virtual reg defs, and a def or use of a
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// sentinel register.
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unsigned SentinelReg = 0;
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auto MI3 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto MI4 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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// Check that they are never identical.
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
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}
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// Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
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// MachineInstrExpressionTrait::getHashValue
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void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
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bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
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bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
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ASSERT_EQ(IsEqual1, IsEqual2);
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auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
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auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
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ASSERT_EQ(IsEqual1, Hash1 == Hash2);
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}
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// This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
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// with MachineInstrExpressionTraits::getHashValue.
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TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo[2];
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} Table = {
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{0, NumOps, NumDefs, 0, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef, 0},
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{{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}};
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// Define a series of instructions with different kinds of operands and make
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// sure that the hash function is consistent with isEqual for various
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// combinations of them.
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unsigned VirtualDef1 = -42;
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unsigned VirtualDef2 = -43;
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unsigned VirtualReg = -44;
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unsigned SentinelReg = 0;
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unsigned PhysicalReg = 45;
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auto VD1VU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD2VU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD1SU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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auto VD1SD = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto VD2PU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
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auto VD2PD = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
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checkHashAndIsEqualMatch(VD1VU, VD2VU);
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checkHashAndIsEqualMatch(VD1VU, VD1SU);
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checkHashAndIsEqualMatch(VD1VU, VD1SD);
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checkHashAndIsEqualMatch(VD1VU, VD2PU);
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checkHashAndIsEqualMatch(VD1VU, VD2PD);
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checkHashAndIsEqualMatch(VD2VU, VD1SU);
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checkHashAndIsEqualMatch(VD2VU, VD1SD);
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checkHashAndIsEqualMatch(VD2VU, VD2PU);
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checkHashAndIsEqualMatch(VD2VU, VD2PD);
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checkHashAndIsEqualMatch(VD1SU, VD1SD);
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checkHashAndIsEqualMatch(VD1SU, VD2PU);
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checkHashAndIsEqualMatch(VD1SU, VD2PD);
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checkHashAndIsEqualMatch(VD1SD, VD2PU);
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checkHashAndIsEqualMatch(VD1SD, VD2PD);
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checkHashAndIsEqualMatch(VD2PU, VD2PD);
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}
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TEST(MachineInstrPrintingTest, DebugLocPrinting) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo;
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} Table = {{0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, MCOI::OPERAND_REGISTER, 0}};
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DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
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DISubprogram *DIS = DISubprogram::getDistinct(
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Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
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DISubprogram::SPFlagZero, nullptr);
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DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
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DebugLoc DL(DIL);
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MachineInstr *MI = MF->CreateMachineInstr(Table.MCID, DL);
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MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
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std::string str;
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raw_string_ostream OS(str);
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MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
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/*AddNewLine*/false);
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ASSERT_TRUE(StringRef(str).starts_with("$noreg = UNKNOWN debug-location "));
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ASSERT_TRUE(StringRef(str).ends_with("filename:1:5"));
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}
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TEST(MachineInstrSpan, DistanceBegin) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MII = MBB->begin();
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MachineInstrSpan MIS(MII, MBB);
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ASSERT_TRUE(MIS.empty());
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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MBB->insert(MII, MI);
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ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
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}
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TEST(MachineInstrSpan, DistanceEnd) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MII = MBB->end();
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MachineInstrSpan MIS(MII, MBB);
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ASSERT_TRUE(MIS.empty());
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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MBB->insert(MII, MI);
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ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
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}
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TEST(MachineInstrExtraInfo, AddExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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auto MC = createMCContext(&MAI);
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 8, Align(8));
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SmallVector<MachineMemOperand *, 2> MMOs;
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MMOs.push_back(MMO);
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MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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MDNode *HAM = MDNode::getDistinct(Ctx, {});
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MDNode *PCS = MDNode::getDistinct(Ctx, {});
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MDNode *MMRA = MMRAMetadata::getTagMD(Ctx, "foo", "bar");
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ASSERT_TRUE(MI->memoperands_empty());
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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ASSERT_FALSE(MI->getPCSections());
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setMemRefs(*MF, MMOs);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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ASSERT_FALSE(MI->getPCSections());
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setPreInstrSymbol(*MF, Sym1);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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ASSERT_FALSE(MI->getPCSections());
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setPostInstrSymbol(*MF, Sym2);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_FALSE(MI->getHeapAllocMarker());
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ASSERT_FALSE(MI->getPCSections());
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setHeapAllocMarker(*MF, HAM);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_FALSE(MI->getPCSections());
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setPCSections(*MF, PCS);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_TRUE(MI->getPCSections() == PCS);
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ASSERT_FALSE(MI->getMMRAMetadata());
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MI->setMMRAMetadata(*MF, MMRA);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_TRUE(MI->getPCSections() == PCS);
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ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
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// Check with nothing but MMRAs.
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MachineInstr *MMRAMI = MF->CreateMachineInstr(MCID, DebugLoc());
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ASSERT_FALSE(MMRAMI->getMMRAMetadata());
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MMRAMI->setMMRAMetadata(*MF, MMRA);
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ASSERT_TRUE(MMRAMI->getMMRAMetadata() == MMRA);
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}
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TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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auto MC = createMCContext(&MAI);
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 8, Align(8));
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SmallVector<MachineMemOperand *, 2> MMOs;
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MMOs.push_back(MMO);
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MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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MDNode *HAM = MDNode::getDistinct(Ctx, {});
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MDNode *PCS = MDNode::getDistinct(Ctx, {});
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MDNode *MMRA1 = MMRAMetadata::getTagMD(Ctx, "foo", "bar");
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MDNode *MMRA2 = MMRAMetadata::getTagMD(Ctx, "bar", "bux");
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MI->setMemRefs(*MF, MMOs);
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MI->setPreInstrSymbol(*MF, Sym1);
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MI->setPostInstrSymbol(*MF, Sym2);
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MI->setHeapAllocMarker(*MF, HAM);
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MI->setPCSections(*MF, PCS);
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MI->setMMRAMetadata(*MF, MMRA1);
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MMOs.push_back(MMO);
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MI->setMemRefs(*MF, MMOs);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_TRUE(MI->getPCSections() == PCS);
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ASSERT_TRUE(MI->getMMRAMetadata() == MMRA1);
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MI->setPostInstrSymbol(*MF, Sym1);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_TRUE(MI->getPCSections() == PCS);
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ASSERT_TRUE(MI->getMMRAMetadata() == MMRA1);
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MI->setMMRAMetadata(*MF, MMRA2);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
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ASSERT_TRUE(MI->getPCSections() == PCS);
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ASSERT_TRUE(MI->getMMRAMetadata() == MMRA2);
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}
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TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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|
auto MC = createMCContext(&MAI);
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|
auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
|
|
MachineMemOperand::MOLoad, 8, Align(8));
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|
SmallVector<MachineMemOperand *, 2> MMOs;
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|
MMOs.push_back(MMO);
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|
MMOs.push_back(MMO);
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|
MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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|
MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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|
MDNode *HAM = MDNode::getDistinct(Ctx, {});
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|
MDNode *PCS = MDNode::getDistinct(Ctx, {});
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|
|
|
MDNode *MMRA = MDTuple::get(Ctx, {});
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|
|
|
MI->setMemRefs(*MF, MMOs);
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|
MI->setPreInstrSymbol(*MF, Sym1);
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|
MI->setPostInstrSymbol(*MF, Sym2);
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|
MI->setHeapAllocMarker(*MF, HAM);
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|
MI->setPCSections(*MF, PCS);
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|
MI->setMMRAMetadata(*MF, MMRA);
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|
|
|
MI->setPostInstrSymbol(*MF, nullptr);
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|
ASSERT_TRUE(MI->memoperands().size() == 2);
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|
ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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|
ASSERT_FALSE(MI->getPostInstrSymbol());
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|
ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
|
|
ASSERT_TRUE(MI->getPCSections() == PCS);
|
|
ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
|
|
|
|
MI->setHeapAllocMarker(*MF, nullptr);
|
|
ASSERT_TRUE(MI->memoperands().size() == 2);
|
|
ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
|
|
ASSERT_FALSE(MI->getPostInstrSymbol());
|
|
ASSERT_FALSE(MI->getHeapAllocMarker());
|
|
ASSERT_TRUE(MI->getPCSections() == PCS);
|
|
ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
|
|
|
|
MI->setPCSections(*MF, nullptr);
|
|
ASSERT_TRUE(MI->memoperands().size() == 2);
|
|
ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
|
|
ASSERT_FALSE(MI->getPostInstrSymbol());
|
|
ASSERT_FALSE(MI->getHeapAllocMarker());
|
|
ASSERT_FALSE(MI->getPCSections());
|
|
ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
|
|
|
|
MI->setPreInstrSymbol(*MF, nullptr);
|
|
ASSERT_TRUE(MI->memoperands().size() == 2);
|
|
ASSERT_FALSE(MI->getPreInstrSymbol());
|
|
ASSERT_FALSE(MI->getPostInstrSymbol());
|
|
ASSERT_FALSE(MI->getHeapAllocMarker());
|
|
ASSERT_FALSE(MI->getPCSections());
|
|
ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
|
|
|
|
MI->setMemRefs(*MF, {});
|
|
ASSERT_TRUE(MI->memoperands_empty());
|
|
ASSERT_FALSE(MI->getPreInstrSymbol());
|
|
ASSERT_FALSE(MI->getPostInstrSymbol());
|
|
ASSERT_FALSE(MI->getHeapAllocMarker());
|
|
ASSERT_FALSE(MI->getPCSections());
|
|
ASSERT_TRUE(MI->getMMRAMetadata() == MMRA);
|
|
|
|
MI->setMMRAMetadata(*MF, nullptr);
|
|
ASSERT_TRUE(MI->memoperands_empty());
|
|
ASSERT_FALSE(MI->getPreInstrSymbol());
|
|
ASSERT_FALSE(MI->getPostInstrSymbol());
|
|
ASSERT_FALSE(MI->getHeapAllocMarker());
|
|
ASSERT_FALSE(MI->getPCSections());
|
|
ASSERT_FALSE(MI->getMMRAMetadata());
|
|
}
|
|
|
|
TEST(MachineInstrDebugValue, AddDebugValueOperand) {
|
|
LLVMContext Ctx;
|
|
Module Mod("Module", Ctx);
|
|
auto MF = createMachineFunction(Ctx, Mod);
|
|
|
|
for (const unsigned short Opcode :
|
|
{TargetOpcode::DBG_VALUE, TargetOpcode::DBG_VALUE_LIST,
|
|
TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI,
|
|
TargetOpcode::DBG_LABEL}) {
|
|
const MCInstrDesc MCID = {
|
|
Opcode, 0, 0, 0, 0,
|
|
0, 0, 0, 0, (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
|
|
0};
|
|
|
|
auto *MI = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false));
|
|
|
|
MI->addOperand(*MF, MachineOperand::CreateImm(0));
|
|
MI->getOperand(1).ChangeToRegister(0, false);
|
|
|
|
ASSERT_TRUE(MI->getOperand(0).isDebug());
|
|
ASSERT_TRUE(MI->getOperand(1).isDebug());
|
|
}
|
|
}
|
|
|
|
MATCHER_P(HasMIMetadata, MIMD, "") {
|
|
return arg->getDebugLoc() == MIMD.getDL() &&
|
|
arg->getPCSections() == MIMD.getPCSections();
|
|
}
|
|
|
|
TEST(MachineInstrBuilder, BuildMI) {
|
|
LLVMContext Ctx;
|
|
MDNode *PCS = MDNode::getDistinct(Ctx, {});
|
|
MDNode *DI = MDNode::getDistinct(Ctx, {});
|
|
DebugLoc DL(DI);
|
|
MIMetadata MIMD(DL, PCS);
|
|
EXPECT_EQ(MIMD.getDL(), DL);
|
|
EXPECT_EQ(MIMD.getPCSections(), PCS);
|
|
// Check common BuildMI() overloads propagate MIMetadata.
|
|
Module Mod("Module", Ctx);
|
|
auto MF = createMachineFunction(Ctx, Mod);
|
|
auto MBB = MF->CreateMachineBasicBlock();
|
|
MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
|
|
EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MBB, MBB->instr_end(), MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MBB, *MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(*MBB, &*MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
|
|
EXPECT_THAT(BuildMI(MBB, MIMD, MCID), HasMIMetadata(MIMD));
|
|
}
|
|
|
|
static_assert(std::is_trivially_copyable_v<MCOperand>, "trivially copyable");
|
|
|
|
TEST(MachineInstrTest, SpliceOperands) {
|
|
LLVMContext Ctx;
|
|
Module Mod("Module", Ctx);
|
|
std::unique_ptr<MachineFunction> MF = createMachineFunction(Ctx, Mod);
|
|
MachineBasicBlock *MBB = MF->CreateMachineBasicBlock();
|
|
MCInstrDesc MCID = {TargetOpcode::INLINEASM,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
(1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
|
|
0};
|
|
MachineInstr *MI = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
MBB->insert(MBB->begin(), MI);
|
|
MI->addOperand(MachineOperand::CreateImm(0));
|
|
MI->addOperand(MachineOperand::CreateImm(1));
|
|
MI->addOperand(MachineOperand::CreateImm(2));
|
|
MI->addOperand(MachineOperand::CreateImm(3));
|
|
MI->addOperand(MachineOperand::CreateImm(4));
|
|
|
|
MI->removeOperand(1);
|
|
EXPECT_EQ(MI->getOperand(1).getImm(), MachineOperand::CreateImm(2).getImm());
|
|
EXPECT_EQ(MI->getNumOperands(), 4U);
|
|
|
|
MachineOperand Ops[] = {
|
|
MachineOperand::CreateImm(42), MachineOperand::CreateImm(1024),
|
|
MachineOperand::CreateImm(2048), MachineOperand::CreateImm(4096),
|
|
MachineOperand::CreateImm(8192),
|
|
};
|
|
auto *It = MI->operands_begin();
|
|
++It;
|
|
MI->insert(It, Ops);
|
|
|
|
EXPECT_EQ(MI->getNumOperands(), 9U);
|
|
EXPECT_EQ(MI->getOperand(0).getImm(), MachineOperand::CreateImm(0).getImm());
|
|
EXPECT_EQ(MI->getOperand(1).getImm(), MachineOperand::CreateImm(42).getImm());
|
|
EXPECT_EQ(MI->getOperand(2).getImm(),
|
|
MachineOperand::CreateImm(1024).getImm());
|
|
EXPECT_EQ(MI->getOperand(3).getImm(),
|
|
MachineOperand::CreateImm(2048).getImm());
|
|
EXPECT_EQ(MI->getOperand(4).getImm(),
|
|
MachineOperand::CreateImm(4096).getImm());
|
|
EXPECT_EQ(MI->getOperand(5).getImm(),
|
|
MachineOperand::CreateImm(8192).getImm());
|
|
EXPECT_EQ(MI->getOperand(6).getImm(), MachineOperand::CreateImm(2).getImm());
|
|
EXPECT_EQ(MI->getOperand(7).getImm(), MachineOperand::CreateImm(3).getImm());
|
|
EXPECT_EQ(MI->getOperand(8).getImm(), MachineOperand::CreateImm(4).getImm());
|
|
|
|
// test tied operands
|
|
MCRegisterClass MRC{
|
|
0, 0, 0, 0, 0, 0, 0, 0, /*Allocatable=*/true, /*BaseClass=*/true};
|
|
TargetRegisterClass RC{&MRC, 0, 0, {}, 0, 0, 0, 0, 0, 0, 0, 0};
|
|
// MachineRegisterInfo will be very upset if these registers aren't
|
|
// allocatable.
|
|
assert(RC.isAllocatable() && "unusable TargetRegisterClass");
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
Register A = MRI.createVirtualRegister(&RC);
|
|
Register B = MRI.createVirtualRegister(&RC);
|
|
MI->getOperand(0).ChangeToRegister(A, /*isDef=*/true);
|
|
MI->getOperand(1).ChangeToRegister(B, /*isDef=*/false);
|
|
MI->tieOperands(0, 1);
|
|
EXPECT_TRUE(MI->getOperand(0).isTied());
|
|
EXPECT_TRUE(MI->getOperand(1).isTied());
|
|
EXPECT_EQ(MI->findTiedOperandIdx(0), 1U);
|
|
EXPECT_EQ(MI->findTiedOperandIdx(1), 0U);
|
|
MI->insert(&MI->getOperand(1), {MachineOperand::CreateImm(7)});
|
|
EXPECT_TRUE(MI->getOperand(0).isTied());
|
|
EXPECT_TRUE(MI->getOperand(1).isImm());
|
|
EXPECT_TRUE(MI->getOperand(2).isTied());
|
|
EXPECT_EQ(MI->findTiedOperandIdx(0), 2U);
|
|
EXPECT_EQ(MI->findTiedOperandIdx(2), 0U);
|
|
EXPECT_EQ(MI->getOperand(0).getReg(), A);
|
|
EXPECT_EQ(MI->getOperand(2).getReg(), B);
|
|
|
|
// bad inputs
|
|
EXPECT_EQ(MI->getNumOperands(), 10U);
|
|
MI->insert(MI->operands_begin(), {});
|
|
EXPECT_EQ(MI->getNumOperands(), 10U);
|
|
}
|
|
|
|
} // end namespace
|