vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
276 lines
7.2 KiB
C++
276 lines
7.2 KiB
C++
//===- MachineDomTreeUpdaterTest.cpp - MachineDomTreeUpdater unit tests ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineDomTreeUpdater.h"
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#include "llvm/Analysis/CGSCCPassManager.h"
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#include "llvm/Analysis/LoopAnalysisManager.h"
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#include "llvm/CodeGen/MIRParser/MIRParser.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachinePassManager.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Passes/PassBuilder.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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class MachineDomTreeUpdaterTest : public testing::Test {
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public:
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LLVMContext Context;
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std::unique_ptr<TargetMachine> TM;
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std::unique_ptr<Module> M;
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std::unique_ptr<MachineModuleInfo> MMI;
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std::unique_ptr<MIRParser> MIR;
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LoopAnalysisManager LAM;
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MachineFunctionAnalysisManager MFAM;
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FunctionAnalysisManager FAM;
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CGSCCAnalysisManager CGAM;
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ModuleAnalysisManager MAM;
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ModulePassManager MPM;
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FunctionPassManager FPM;
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MachineFunctionPassManager MFPM;
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static void SetUpTestCase() {
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InitializeAllTargets();
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InitializeAllTargetMCs();
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}
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void SetUp() override {
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Triple TargetTriple("x86_64-unknown-linux-gnu");
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
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if (!T)
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GTEST_SKIP();
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TargetOptions Options;
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TM = std::unique_ptr<TargetMachine>(
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T->createTargetMachine(TargetTriple, "", "", Options, std::nullopt));
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if (!TM)
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GTEST_SKIP();
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MMI = std::make_unique<MachineModuleInfo>(TM.get());
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PassBuilder PB(TM.get());
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PB.registerModuleAnalyses(MAM);
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PB.registerCGSCCAnalyses(CGAM);
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PB.registerFunctionAnalyses(FAM);
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PB.registerLoopAnalyses(LAM);
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PB.registerMachineFunctionAnalyses(MFAM);
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PB.crossRegisterProxies(LAM, FAM, CGAM, MAM, &MFAM);
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MAM.registerPass([&] { return MachineModuleAnalysis(*MMI); });
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}
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bool parseMIR(StringRef MIRCode) {
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SMDiagnostic Diagnostic;
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std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
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MIR = createMIRParser(std::move(MBuffer), Context);
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if (!MIR)
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return false;
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M = MIR->parseIRModule();
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M->setDataLayout(TM->createDataLayout());
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if (MIR->parseMachineFunctions(*M, MAM)) {
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M.reset();
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return false;
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}
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return true;
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}
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};
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TEST_F(MachineDomTreeUpdaterTest, EagerUpdateBasicOperations) {
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StringRef MIRString = R"(
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--- |
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define i64 @f0(i64 %i, ptr %p) {
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bb0:
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store i64 %i, ptr %p, align 4
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switch i64 %i, label %bb1 [
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i64 1, label %bb2
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i64 2, label %bb3
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]
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bb1: ; preds = %bb0
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ret i64 1
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bb2: ; preds = %bb0
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ret i64 2
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bb3: ; preds = %bb0
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ret i64 3
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}
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...
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---
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name: f0
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body: |
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bb.0.bb0:
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successors: %bb.2, %bb.4
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liveins: $rdi, $rsi
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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MOV64mr %1, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.p)
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%2:gr64 = SUB64ri32 %0, 1, implicit-def $eflags
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JCC_1 %bb.2, 4, implicit $eflags
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JMP_1 %bb.4
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bb.4.bb0:
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successors: %bb.3, %bb.1
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%3:gr64 = SUB64ri32 %0, 2, implicit-def $eflags
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JCC_1 %bb.3, 4, implicit $eflags
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JMP_1 %bb.1
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bb.1.bb1:
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%6:gr64 = MOV32ri64 1
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$rax = COPY %6
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RET 0, $rax
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bb.2.bb2:
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%5:gr64 = MOV32ri64 2
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$rax = COPY %5
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RET 0, $rax
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bb.3.bb3:
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%4:gr64 = MOV32ri64 3
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$rax = COPY %4
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RET 0, $rax
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...
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)";
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ASSERT_TRUE(parseMIR(MIRString));
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auto &MF =
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FAM.getResult<MachineFunctionAnalysis>(*M->getFunction("f0")).getMF();
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MachineDominatorTree DT(MF);
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MachinePostDominatorTree PDT(MF);
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MachineDomTreeUpdater DTU(DT, PDT,
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MachineDomTreeUpdater::UpdateStrategy::Eager);
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ASSERT_TRUE(DTU.hasDomTree());
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ASSERT_TRUE(DTU.hasPostDomTree());
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ASSERT_TRUE(DTU.isEager());
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ASSERT_FALSE(DTU.isLazy());
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ASSERT_TRUE(DTU.getDomTree().verify());
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ASSERT_TRUE(DTU.getPostDomTree().verify());
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ASSERT_FALSE(DTU.hasPendingUpdates());
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auto B = MF.begin();
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[[maybe_unused]] auto BB0 = B;
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auto BB1 = ++B;
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auto BB2 = ++B;
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[[maybe_unused]] auto BB3 = ++B;
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auto BB4 = ++B;
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EXPECT_EQ(BB1->succ_size(), 2u);
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB2));
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB4));
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BB1->removeSuccessor(&*BB4);
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DTU.deleteBB(&*BB4);
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EXPECT_EQ(BB1->succ_size(), 1u);
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB2));
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}
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TEST_F(MachineDomTreeUpdaterTest, LazyUpdateBasicOperations) {
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StringRef MIRString = R"(
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--- |
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define i64 @f0(i64 %i, ptr %p) {
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bb0:
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store i64 %i, ptr %p, align 4
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switch i64 %i, label %bb1 [
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i64 1, label %bb2
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i64 2, label %bb3
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]
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bb1: ; preds = %bb0
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ret i64 1
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bb2: ; preds = %bb0
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ret i64 2
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bb3: ; preds = %bb0
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ret i64 3
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}
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...
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---
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name: f0
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body: |
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bb.0.bb0:
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successors: %bb.2, %bb.4
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liveins: $rdi, $rsi
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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MOV64mr %1, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.p)
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%2:gr64 = SUB64ri32 %0, 1, implicit-def $eflags
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JCC_1 %bb.2, 4, implicit $eflags
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JMP_1 %bb.4
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bb.4.bb0:
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successors: %bb.3, %bb.1
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%3:gr64 = SUB64ri32 %0, 2, implicit-def $eflags
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JCC_1 %bb.3, 4, implicit $eflags
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JMP_1 %bb.1
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bb.1.bb1:
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%6:gr64 = MOV32ri64 1
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$rax = COPY %6
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RET 0, $rax
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bb.2.bb2:
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%5:gr64 = MOV32ri64 2
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$rax = COPY %5
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RET 0, $rax
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bb.3.bb3:
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%4:gr64 = MOV32ri64 3
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$rax = COPY %4
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RET 0, $rax
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...
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)";
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ASSERT_TRUE(parseMIR(MIRString));
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auto &MF =
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FAM.getResult<MachineFunctionAnalysis>(*M->getFunction("f0")).getMF();
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MachineDominatorTree DT(MF);
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MachinePostDominatorTree PDT(MF);
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MachineDomTreeUpdater DTU(DT, PDT,
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MachineDomTreeUpdater::UpdateStrategy::Lazy);
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ASSERT_TRUE(DTU.hasDomTree());
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ASSERT_TRUE(DTU.hasPostDomTree());
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ASSERT_FALSE(DTU.isEager());
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ASSERT_TRUE(DTU.isLazy());
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ASSERT_TRUE(DTU.getDomTree().verify());
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ASSERT_TRUE(DTU.getPostDomTree().verify());
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ASSERT_FALSE(DTU.hasPendingUpdates());
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auto B = MF.begin();
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[[maybe_unused]] auto BB0 = B;
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auto BB1 = ++B;
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auto BB2 = ++B;
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[[maybe_unused]] auto BB3 = ++B;
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auto BB4 = ++B;
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EXPECT_EQ(BB1->succ_size(), 2u);
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB2));
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB4));
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BB1->removeSuccessor(&*BB4);
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DTU.deleteBB(&*BB4);
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ASSERT_TRUE(DTU.hasPendingDeletedBB());
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EXPECT_EQ(BB1->succ_size(), 1u);
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ASSERT_TRUE(DT.dominates(&*BB1, &*BB2));
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ASSERT_NE(DT.getNode(&*BB4), nullptr);
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DTU.flush();
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}
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