vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
166 lines
5.6 KiB
C
166 lines
5.6 KiB
C
// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LINUX
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// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-WIN
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// RUN: %clang_cc1 -triple arm64_32-apple-ios13 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
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#include <stdint.h>
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void f0(void *a, void *b) {
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__clear_cache(a,b);
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// CHECK: call {{.*}} @__clear_cache
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}
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void *tp (void) {
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return __builtin_thread_pointer ();
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// CHECK-LINUX: call {{.*}} @llvm.thread.pointer.p0()
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}
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// CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)
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unsigned rbit(unsigned a) {
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return __builtin_arm_rbit(a);
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}
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// CHECK-WIN: [[A64:%[^ ]+]] = zext i32 %a to i64
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// CHECK-WIN: call i64 @llvm.bitreverse.i64(i64 [[A64]])
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// CHECK-LINUX: call i64 @llvm.bitreverse.i64(i64 %a)
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unsigned long rbitl(unsigned long a) {
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return __builtin_arm_rbit64(a);
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}
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// CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a)
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uint64_t rbit64(uint64_t a) {
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return __builtin_arm_rbit64(a);
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}
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void hints(void) {
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__builtin_arm_nop(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
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__builtin_arm_yield(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
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__builtin_arm_wfe(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)
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__builtin_arm_wfi(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)
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__builtin_arm_sev(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)
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__builtin_arm_sevl(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)
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}
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void barriers(void) {
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__builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.aarch64.dmb(i32 1)
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__builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.aarch64.dsb(i32 2)
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__builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.aarch64.isb(i32 3)
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}
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void prefetch(void) {
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__builtin_arm_prefetch(0, 1, 2, 0, 1); // pstl3keep
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// CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
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__builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1keep
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// CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
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__builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm
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// CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
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__builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep
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// CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
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__builtin_arm_prefetch(0, 0, 3, 0, 1); // pldslckeep
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// CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
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}
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__attribute__((target("v8.5a")))
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int32_t jcvt(double v) {
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//CHECK-LABEL: @jcvt(
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//CHECK: call i32 @llvm.aarch64.fjcvtzs
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return __builtin_arm_jcvt(v);
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}
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__typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);
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uint32_t rsr(void) {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
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// CHECK-NEXT: trunc i64 [[V0]] to i32
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return __builtin_arm_rsr("1:2:3:4:5");
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}
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__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);
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uint64_t rsr64(void) {
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// CHECK: call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
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return __builtin_arm_rsr64("1:2:3:4:5");
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}
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void *rsrp(void) {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
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// CHECK-NEXT: inttoptr i64 [[V0]] to ptr
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return __builtin_arm_rsrp("1:2:3:4:5");
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}
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__typeof__(__builtin_arm_wsr("1:2:3:4:5", 0)) wsr(unsigned);
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void wsr(unsigned v) {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64
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// CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
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__builtin_arm_wsr("1:2:3:4:5", v);
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}
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__typeof__(__builtin_arm_wsr64("1:2:3:4:5", 0)) wsr64(uint64_t);
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void wsr64(uint64_t v) {
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// CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)
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__builtin_arm_wsr64("1:2:3:4:5", v);
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}
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void wsrp(void *v) {
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// CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint ptr %v to i64
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// CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
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__builtin_arm_wsrp("1:2:3:4:5", v);
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}
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unsigned int cls(uint32_t v) {
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// CHECK: call i32 @llvm.aarch64.cls(i32 %v)
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return __builtin_arm_cls(v);
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}
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unsigned int clsl(unsigned long v) {
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// CHECK-WIN: [[V64:%[^ ]+]] = zext i32 %v to i64
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// CHECK-WIN: call i32 @llvm.aarch64.cls64(i64 [[V64]]
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// CHECK-LINUX: call i32 @llvm.aarch64.cls64(i64 %v)
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return __builtin_arm_cls64(v);
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}
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unsigned int clsll(uint64_t v) {
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// CHECK: call i32 @llvm.aarch64.cls64(i64 %v)
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return __builtin_arm_cls64(v);
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}
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// CHECK-LABEL: @rndr(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr()
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// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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// CHECK-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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// CHECK-NEXT: ret i32 [[TMP3]]
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//
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__attribute__((target("rand")))
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int rndr(uint64_t *__addr) {
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return __builtin_arm_rndr(__addr);
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}
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// CHECK-LABEL: @rndrrs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs()
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// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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// CHECK-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
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// CHECK-NEXT: ret i32 [[TMP3]]
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//
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__attribute__((target("rand")))
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int rndrrs(uint64_t *__addr) {
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return __builtin_arm_rndrrs(__addr);
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}
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// CHECK-LABEL: @trap(
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// CHECK: call void @llvm.aarch64.break(i32 42)
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void trap() {
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__builtin_arm_trap(42);
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}
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// CHECK: ![[M0]] = !{!"1:2:3:4:5"}
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