vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
74 lines
2.5 KiB
ReStructuredText
74 lines
2.5 KiB
ReStructuredText
.. _regbankselect:
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RegBankSelect
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-------------
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This pass constrains the :ref:`gmir-gvregs` operands of generic
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instructions to some :ref:`gmir-regbank`.
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It iteratively maps instructions to a set of per-operand bank assignment.
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The possible mappings are determined by the target-provided
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:ref:`RegisterBankInfo <api-registerbankinfo>`.
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The mapping is then applied, possibly introducing ``COPY`` instructions if
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necessary.
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It traverses the ``MachineFunction`` top down so that all operands are already
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mapped when analyzing an instruction.
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This pass could also remap target-specific instructions when beneficial.
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In the future, this could replace the ExeDepsFix pass, as we can directly
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select the best variant for an instruction that's available on multiple banks.
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.. _api-registerbankinfo:
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API: RegisterBankInfo
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^^^^^^^^^^^^^^^^^^^^^
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The ``RegisterBankInfo`` class describes multiple aspects of register banks.
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* **Banks**: ``addRegBankCoverage`` --- which register bank covers each
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register class.
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* **Cross-Bank Copies**: ``copyCost`` --- the cost of a ``COPY`` from one bank
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to another.
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* **Default Mapping**: ``getInstrMapping`` --- the default bank assignments for
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a given instruction.
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* **Alternative Mapping**: ``getInstrAlternativeMapping`` --- the other
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possible bank assignments for a given instruction.
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``TODO``:
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All this information should eventually be static and generated by TableGen,
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mostly using existing information augmented by bank descriptions.
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``TODO``:
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``getInstrMapping`` is currently separate from ``getInstrAlternativeMapping``
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because the latter is more expensive: as we move to static mapping info,
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both methods should be free, and we should merge them.
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.. _regbankselect-modes:
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RegBankSelect Modes
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^^^^^^^^^^^^^^^^^^^
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``RegBankSelect`` currently has two modes:
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* **Fast** --- For each instruction, pick a target-provided "default" bank
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assignment. This is the default at -O0.
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* **Greedy** --- For each instruction, pick the cheapest of several
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target-provided bank assignment alternatives.
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We intend to eventually introduce an additional optimizing mode:
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* **Global** --- Across multiple instructions, pick the cheapest combination of
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bank assignments.
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``NOTE``:
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On AArch64, we are considering using the Greedy mode even at -O0 (or perhaps at
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backend -O1): because :ref:`gmir-llt` doesn't distinguish floating point from
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integer scalars, the default assignment for loads and stores is the integer
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bank, introducing cross-bank copies on most floating point operations.
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