intel: proper Xe2 watermark calculations (Phase 2 DBUF complete)
Enhance display_watermark.rs with real watermark computations
based on display mode parameters for Xe2 platforms.
- program_for_mode(): compute and program per-pipe watermarks
from ModeInfo (pixel clock, resolution). Programs PLANE_BUF_CFG,
PLANE_WM, PLANE_WM_LINES (0x70244), PLANE_WM_BLOCKS (0x70248)
- compute_watermark_lines(): lines = (pixel_rate * hdisplay) /
(memory_bw / 1000), clamped to [4, 31]
- compute_watermark_blocks(): blocks = (pixel_rate * bytes_per_line) /
(memory_bw / 1000), clamped to [32, 512]
- WM_LINES_ENABLE/WM_BLOCKS_ENABLE bits with computed values
- disable_pipe(): clear all plane watermark registers
- XE2_MEMORY_BW_KBPS: 50 GB/s baseline for Arrow Lake LPDDR5
Wire program_for_mode() into IntelDriver::set_crtc after
transcoder configuration, before page flip.
Phase 2 (Gen12 Display) now at 4/4 — COMPLETE.
Linux reference: skl_watermark.c, intel_dbuf.c
vasilito
70872ef96e