Wren Turkal
65982d5e02
This change adds a structopt commandline interface to the pcid tool. This add some help for the arguments that pcid takes. Signed-off-by: Wren Turkal <wt@penguintechs.org>
614 lines
25 KiB
Rust
614 lines
25 KiB
Rust
#![feature(asm)]
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use std::fs::{File, metadata, read_dir};
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use std::io::prelude::*;
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use std::os::unix::io::{FromRawFd, RawFd};
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use std::process::Command;
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use std::sync::{Arc, Mutex};
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use std::{env, io, i64, thread};
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use syscall::iopl;
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use structopt::StructOpt;
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use log::{error, info, warn, trace};
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use redox_log::{OutputBuilder, RedoxLogger};
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use crate::config::Config;
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use crate::pci::{CfgAccess, Pci, PciIter, PciBar, PciBus, PciClass, PciDev, PciFunc, PciHeader, PciHeaderError, PciHeaderType};
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use crate::pci::cap::Capability as PciCapability;
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use crate::pcie::Pcie;
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mod config;
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mod driver_interface;
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mod pci;
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mod pcie;
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#[derive(StructOpt)]
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#[structopt(about)]
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struct Args {
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#[structopt(short, long,
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help="Increase logging level once for each arg.", parse(from_occurrences))]
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verbose: u8,
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#[structopt(
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help="A path to a pcid config file or a directory that contains pcid config files.")]
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config_path: Option<String>,
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}
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pub struct DriverHandler {
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config: config::DriverConfig,
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bus_num: u8,
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dev_num: u8,
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func_num: u8,
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header: PciHeader,
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capabilities: Vec<(u8, PciCapability)>,
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state: Arc<State>,
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}
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fn with_pci_func_raw<T, F: FnOnce(&PciFunc) -> T>(pci: &dyn CfgAccess, bus_num: u8, dev_num: u8, func_num: u8, function: F) -> T {
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let bus = PciBus {
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pci,
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num: bus_num,
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};
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let dev = PciDev {
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bus: &bus,
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num: dev_num,
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};
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let func = PciFunc {
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dev: &dev,
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num: func_num,
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};
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function(&func)
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}
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impl DriverHandler {
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fn with_pci_func_raw<T, F: FnOnce(&PciFunc) -> T>(&self, function: F) -> T {
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with_pci_func_raw(self.state.preferred_cfg_access(), self.bus_num, self.dev_num, self.func_num, function)
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}
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fn respond(&mut self, request: driver_interface::PcidClientRequest, args: &driver_interface::SubdriverArguments) -> driver_interface::PcidClientResponse {
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use driver_interface::*;
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use crate::pci::cap::{MsiCapability, MsixCapability};
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match request {
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PcidClientRequest::RequestConfig => {
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PcidClientResponse::Config(args.clone())
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}
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PcidClientRequest::RequestFeatures => {
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PcidClientResponse::AllFeatures(self.capabilities.iter().filter_map(|(_, capability)| match capability {
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PciCapability::Msi(msi) => Some((PciFeature::Msi, FeatureStatus::enabled(msi.enabled()))),
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PciCapability::MsiX(msix) => Some((PciFeature::MsiX, FeatureStatus::enabled(msix.msix_enabled()))),
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_ => None,
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}).collect())
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}
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PcidClientRequest::EnableFeature(feature) => match feature {
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PciFeature::Msi => {
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let (offset, capability): (u8, &mut MsiCapability) = match self.capabilities.iter_mut().find_map(|&mut (offset, ref mut capability)| capability.as_msi_mut().map(|cap| (offset, cap))) {
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Some(tuple) => tuple,
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None => return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature)),
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};
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unsafe {
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with_pci_func_raw(self.state.preferred_cfg_access(), self.bus_num, self.dev_num, self.func_num, |func| {
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capability.set_enabled(true);
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capability.write_message_control(func, offset);
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});
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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PciFeature::MsiX => {
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let (offset, capability): (u8, &mut MsixCapability) = match self.capabilities.iter_mut().find_map(|&mut (offset, ref mut capability)| capability.as_msix_mut().map(|cap| (offset, cap))) {
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Some(tuple) => tuple,
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None => return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature)),
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};
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unsafe {
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with_pci_func_raw(self.state.preferred_cfg_access(), self.bus_num, self.dev_num, self.func_num, |func| {
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capability.set_msix_enabled(true);
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capability.write_a(func, offset);
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});
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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}
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PcidClientRequest::FeatureStatus(feature) => PcidClientResponse::FeatureStatus(feature, match feature {
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PciFeature::Msi => self.capabilities.iter().find_map(|(_, capability)| if let PciCapability::Msi(msi) = capability {
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Some(FeatureStatus::enabled(msi.enabled()))
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} else {
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None
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}).unwrap_or(FeatureStatus::Disabled),
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PciFeature::MsiX => self.capabilities.iter().find_map(|(_, capability)| if let PciCapability::MsiX(msix) = capability {
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Some(FeatureStatus::enabled(msix.msix_enabled()))
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} else {
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None
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}).unwrap_or(FeatureStatus::Disabled),
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}),
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PcidClientRequest::FeatureInfo(feature) => PcidClientResponse::FeatureInfo(feature, match feature {
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PciFeature::Msi => if let Some(info) = self.capabilities.iter().find_map(|(_, capability)| capability.as_msi()) {
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PciFeatureInfo::Msi(*info)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature));
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}
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PciFeature::MsiX => if let Some(info) = self.capabilities.iter().find_map(|(_, capability)| capability.as_msix()) {
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PciFeatureInfo::MsiX(*info)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature));
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}
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}),
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PcidClientRequest::SetFeatureInfo(info_to_set) => match info_to_set {
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SetFeatureInfo::Msi(info_to_set) => if let Some((offset, info)) = self.capabilities.iter_mut().find_map(|(offset, capability)| Some((*offset, capability.as_msi_mut()?))) {
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if let Some(mme) = info_to_set.multi_message_enable {
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if info.multi_message_capable() < mme || mme > 0b101 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_multi_message_enable(mme);
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}
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if let Some(message_addr) = info_to_set.message_address {
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if message_addr & 0b11 != 0 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_message_address(message_addr);
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}
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if let Some(message_addr_upper) = info_to_set.message_upper_address {
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info.set_message_upper_address(message_addr_upper);
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}
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if let Some(message_data) = info_to_set.message_data {
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if message_data & ((1 << info.multi_message_enable()) - 1) != 0 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_message_data(message_data);
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}
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if let Some(mask_bits) = info_to_set.mask_bits {
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info.set_mask_bits(mask_bits);
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}
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unsafe {
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with_pci_func_raw(self.state.preferred_cfg_access(), self.bus_num, self.dev_num, self.func_num, |func| {
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info.write_all(func, offset);
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});
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::Msi)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(PciFeature::Msi));
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}
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SetFeatureInfo::MsiX { function_mask } => if let Some((offset, info)) = self.capabilities.iter_mut().find_map(|(offset, capability)| Some((*offset, capability.as_msix_mut()?))) {
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if let Some(mask) = function_mask {
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info.set_function_mask(mask);
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unsafe {
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with_pci_func_raw(self.state.preferred_cfg_access(), self.bus_num, self.dev_num, self.func_num, |func| {
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info.write_a(func, offset);
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});
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}
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::MsiX)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(PciFeature::MsiX));
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}
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}
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}
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}
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fn handle_spawn(mut self, pcid_to_client_write: Option<usize>, pcid_from_client_read: Option<usize>, args: driver_interface::SubdriverArguments) {
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use driver_interface::*;
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if let (Some(pcid_to_client_fd), Some(pcid_from_client_fd)) = (pcid_to_client_write, pcid_from_client_read) {
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let mut pcid_to_client = unsafe { File::from_raw_fd(pcid_to_client_fd as RawFd) };
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let mut pcid_from_client = unsafe { File::from_raw_fd(pcid_from_client_fd as RawFd) };
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while let Ok(msg) = recv(&mut pcid_from_client) {
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let response = self.respond(msg, &args);
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send(&mut pcid_to_client, &response).unwrap();
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}
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}
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}
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}
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pub struct State {
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threads: Mutex<Vec<thread::JoinHandle<()>>>,
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pci: Arc<Pci>,
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pcie: Option<Pcie>,
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}
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impl State {
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fn preferred_cfg_access(&self) -> &dyn CfgAccess {
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// TODO
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//self.pcie.as_ref().map(|pcie| pcie as &dyn CfgAccess).unwrap_or(&*self.pci as &dyn CfgAccess)
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&*self.pci as &dyn CfgAccess
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}
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}
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fn handle_parsed_header(state: Arc<State>, config: &Config, bus_num: u8,
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dev_num: u8, func_num: u8, header: PciHeader) {
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let pci = state.preferred_cfg_access();
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let raw_class: u8 = header.class().into();
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let mut string = format!("PCI {:>02X}/{:>02X}/{:>02X} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
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bus_num, dev_num, func_num, header.vendor_id(), header.device_id(), raw_class,
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header.subclass(), header.interface(), header.revision(), header.class());
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match header.class() {
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PciClass::Legacy if header.subclass() == 1 => string.push_str(" VGA CTL"),
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PciClass::Storage => match header.subclass() {
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0x01 => {
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string.push_str(" IDE");
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},
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0x06 => if header.interface() == 0 {
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string.push_str(" SATA VND");
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} else if header.interface() == 1 {
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string.push_str(" SATA AHCI");
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},
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_ => ()
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},
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PciClass::SerialBus => match header.subclass() {
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0x03 => match header.interface() {
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0x00 => {
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string.push_str(" UHCI");
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},
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0x10 => {
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string.push_str(" OHCI");
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},
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0x20 => {
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string.push_str(" EHCI");
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},
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0x30 => {
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string.push_str(" XHCI");
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},
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_ => ()
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},
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_ => ()
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},
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_ => ()
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}
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for (i, bar) in header.bars().iter().enumerate() {
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if !bar.is_none() {
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string.push_str(&format!(" {}={}", i, bar));
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}
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}
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info!("{}", string);
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for driver in config.drivers.iter() {
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if let Some(class) = driver.class {
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if class != raw_class { continue; }
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}
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if let Some(subclass) = driver.subclass {
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if subclass != header.subclass() { continue; }
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}
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if let Some(interface) = driver.interface {
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if interface != header.interface() { continue; }
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}
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if let Some(ref ids) = driver.ids {
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let mut device_found = false;
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for (vendor, devices) in ids {
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let vendor_without_prefix = vendor.trim_start_matches("0x");
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let vendor = i64::from_str_radix(vendor_without_prefix, 16).unwrap() as u16;
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if vendor != header.vendor_id() { continue; }
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for device in devices {
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if *device == header.device_id() {
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device_found = true;
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break;
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}
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}
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}
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if !device_found { continue; }
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} else {
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if let Some(vendor) = driver.vendor {
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if vendor != header.vendor_id() { continue; }
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}
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if let Some(device) = driver.device {
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if device != header.device_id() { continue; }
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}
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}
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if let Some(ref device_id_range) = driver.device_id_range {
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if header.device_id() < device_id_range.start ||
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device_id_range.end <= header.device_id() { continue; }
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}
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if let Some(ref args) = driver.command {
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// Enable bus mastering, memory space, and I/O space
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unsafe {
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let mut data = pci.read(bus_num, dev_num, func_num, 0x04);
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data |= 7;
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pci.write(bus_num, dev_num, func_num, 0x04, data);
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}
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// Set IRQ line to 9 if not set
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let mut irq;
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let mut interrupt_pin;
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unsafe {
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let mut data = pci.read(bus_num, dev_num, func_num, 0x3C);
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irq = (data & 0xFF) as u8;
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interrupt_pin = ((data & 0x0000_FF00) >> 8) as u8;
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if irq == 0xFF {
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irq = 9;
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}
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data = (data & 0xFFFFFF00) | irq as u32;
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pci.write(bus_num, dev_num, func_num, 0x3C, data);
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};
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// Find BAR sizes
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let mut bars = [PciBar::None; 6];
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let mut bar_sizes = [0; 6];
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unsafe {
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let count = match header.header_type() {
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PciHeaderType::GENERAL => 6,
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PciHeaderType::PCITOPCI => 2,
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_ => 0,
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};
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for i in 0..count {
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bars[i] = header.get_bar(i);
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let offset = 0x10 + (i as u8) * 4;
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let original = pci.read(bus_num, dev_num, func_num, offset.into());
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pci.write(bus_num, dev_num, func_num, offset.into(), 0xFFFFFFFF);
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let new = pci.read(bus_num, dev_num, func_num, offset.into());
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pci.write(bus_num, dev_num, func_num, offset.into(), original);
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let masked = if new & 1 == 1 {
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new & 0xFFFFFFFC
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} else {
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new & 0xFFFFFFF0
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};
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let size = !masked + 1;
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bar_sizes[i] = if size <= 1 {
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0
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} else {
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size
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};
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}
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}
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let capabilities = if header.status() & (1 << 4) != 0 {
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let bus = PciBus {
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pci: state.preferred_cfg_access(),
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num: bus_num,
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};
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let dev = PciDev {
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bus: &bus,
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num: dev_num
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};
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let func = PciFunc {
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dev: &dev,
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num: func_num,
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};
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crate::pci::cap::CapabilitiesIter { inner: crate::pci::cap::CapabilityOffsetsIter::new(header.cap_pointer(), &func) }.collect::<Vec<_>>()
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} else {
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Vec::new()
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};
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info!("PCI DEVICE CAPABILITIES for {}: {:?}", args.iter().map(|string| string.as_ref()).nth(0).unwrap_or("[unknown]"), capabilities);
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use driver_interface::LegacyInterruptPin;
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let legacy_interrupt_pin = match interrupt_pin {
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0 => None,
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1 => Some(LegacyInterruptPin::IntA),
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2 => Some(LegacyInterruptPin::IntB),
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3 => Some(LegacyInterruptPin::IntC),
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4 => Some(LegacyInterruptPin::IntD),
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other => {
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warn!("pcid: invalid interrupt pin: {}", other);
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None
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}
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};
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let func = driver_interface::PciFunction {
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bars,
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bar_sizes,
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bus_num,
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dev_num,
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func_num,
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devid: header.device_id(),
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legacy_interrupt_line: irq,
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legacy_interrupt_pin,
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venid: header.vendor_id(),
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};
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let subdriver_args = driver_interface::SubdriverArguments {
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func,
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};
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let mut args = args.iter();
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if let Some(program) = args.next() {
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let mut command = Command::new(program);
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for arg in args {
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let arg = match arg.as_str() {
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"$BUS" => format!("{:>02X}", bus_num),
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"$DEV" => format!("{:>02X}", dev_num),
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"$FUNC" => format!("{:>02X}", func_num),
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"$NAME" => func.name(),
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"$BAR0" => format!("{}", bars[0]),
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"$BAR1" => format!("{}", bars[1]),
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"$BAR2" => format!("{}", bars[2]),
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"$BAR3" => format!("{}", bars[3]),
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"$BAR4" => format!("{}", bars[4]),
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"$BAR5" => format!("{}", bars[5]),
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"$BARSIZE0" => format!("{:>08X}", bar_sizes[0]),
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"$BARSIZE1" => format!("{:>08X}", bar_sizes[1]),
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"$BARSIZE2" => format!("{:>08X}", bar_sizes[2]),
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"$BARSIZE3" => format!("{:>08X}", bar_sizes[3]),
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"$BARSIZE4" => format!("{:>08X}", bar_sizes[4]),
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"$BARSIZE5" => format!("{:>08X}", bar_sizes[5]),
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"$IRQ" => format!("{}", irq),
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"$VENID" => format!("{:>04X}", header.vendor_id()),
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"$DEVID" => format!("{:>04X}", header.device_id()),
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_ => arg.clone()
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};
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command.arg(&arg);
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}
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info!("PCID SPAWN {:?}", command);
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let (pcid_to_client_write, pcid_from_client_read, envs) = if driver.use_channel.unwrap_or(false) {
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let mut fds1 = [0usize; 2];
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let mut fds2 = [0usize; 2];
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syscall::pipe2(&mut fds1, 0).expect("pcid: failed to create pcid->client pipe");
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syscall::pipe2(&mut fds2, 0).expect("pcid: failed to create client->pcid pipe");
|
|
|
|
let [pcid_to_client_read, pcid_to_client_write] = fds1;
|
|
let [pcid_from_client_read, pcid_from_client_write] = fds2;
|
|
|
|
(Some(pcid_to_client_write), Some(pcid_from_client_read), vec! [("PCID_TO_CLIENT_FD", format!("{}", pcid_to_client_read)), ("PCID_FROM_CLIENT_FD", format!("{}", pcid_from_client_write))])
|
|
} else {
|
|
(None, None, vec! [])
|
|
};
|
|
|
|
match command.envs(envs).spawn() {
|
|
Ok(mut child) => {
|
|
let driver_handler = DriverHandler {
|
|
bus_num,
|
|
dev_num,
|
|
func_num,
|
|
config: driver.clone(),
|
|
header,
|
|
state: Arc::clone(&state),
|
|
capabilities,
|
|
};
|
|
let thread = thread::spawn(move || {
|
|
driver_handler.handle_spawn(pcid_to_client_write, pcid_from_client_read, subdriver_args);
|
|
});
|
|
match child.wait() {
|
|
Ok(_status) => (),
|
|
Err(err) => error!("pcid: failed to wait for {:?}: {}", command, err),
|
|
}
|
|
}
|
|
Err(err) => error!("pcid: failed to execute {:?}: {}", command, err)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
fn setup_logging(verbosity: u8) -> Option<&'static RedoxLogger> {
|
|
let log_level = match verbosity {
|
|
0 => log::LevelFilter::Info,
|
|
1 => log::LevelFilter::Debug,
|
|
_ => log::LevelFilter::Trace,
|
|
};
|
|
let mut logger = RedoxLogger::new()
|
|
.with_output(
|
|
OutputBuilder::stderr()
|
|
.with_ansi_escape_codes()
|
|
.with_filter(log_level)
|
|
.flush_on_newline(true)
|
|
.build()
|
|
);
|
|
|
|
match OutputBuilder::in_redox_logging_scheme("bus", "pci", "pcid.log") {
|
|
Ok(b) => logger = logger.with_output(
|
|
b.with_filter(log::LevelFilter::Trace)
|
|
.flush_on_newline(true)
|
|
.build()
|
|
),
|
|
Err(error) => eprintln!("pcid: failed to open pcid.log"),
|
|
}
|
|
match OutputBuilder::in_redox_logging_scheme("bus", "pci", "pcid.ansi.log") {
|
|
Ok(b) => logger = logger.with_output(
|
|
b.with_filter(log::LevelFilter::Trace)
|
|
.with_ansi_escape_codes()
|
|
.flush_on_newline(true)
|
|
.build()
|
|
),
|
|
Err(error) => eprintln!("pcid: failed to open pcid.ansi.log"),
|
|
}
|
|
|
|
match logger.enable() {
|
|
Ok(logger_ref) => {
|
|
eprintln!("pcid: enabled logger");
|
|
Some(logger_ref)
|
|
}
|
|
Err(error) => {
|
|
eprintln!("pcid: failed to set default logger: {}", error);
|
|
None
|
|
}
|
|
}
|
|
}
|
|
|
|
#[paw::main]
|
|
fn main(args: Args) {
|
|
let mut config = Config::default();
|
|
|
|
if let Some(config_path) = args.config_path {
|
|
if metadata(&config_path).unwrap().is_file() {
|
|
if let Ok(mut config_file) = File::open(&config_path) {
|
|
let mut config_data = String::new();
|
|
if let Ok(_) = config_file.read_to_string(&mut config_data) {
|
|
config = toml::from_str(&config_data).unwrap_or(Config::default());
|
|
}
|
|
}
|
|
} else {
|
|
let paths = read_dir(&config_path).unwrap();
|
|
|
|
let mut config_data = String::new();
|
|
|
|
for path in paths {
|
|
if let Ok(mut config_file) = File::open(&path.unwrap().path()) {
|
|
let mut tmp = String::new();
|
|
if let Ok(_) = config_file.read_to_string(&mut tmp) {
|
|
config_data.push_str(&tmp);
|
|
}
|
|
}
|
|
}
|
|
config = toml::from_str(&config_data).unwrap_or(Config::default());
|
|
}
|
|
}
|
|
|
|
let _logger_ref = setup_logging(args.verbose);
|
|
|
|
let pci = Arc::new(Pci::new());
|
|
|
|
let state = Arc::new(State {
|
|
pci: Arc::clone(&pci),
|
|
pcie: match Pcie::new(Arc::clone(&pci)) {
|
|
Ok(pcie) => Some(pcie),
|
|
Err(error) => {
|
|
info!("Couldn't retrieve PCIe info, perhaps the kernel is not compiled with acpi? Using the PCI 3.0 configuration space instead. Error: {:?}", error);
|
|
None
|
|
}
|
|
},
|
|
threads: Mutex::new(Vec::new()),
|
|
});
|
|
|
|
let pci = state.preferred_cfg_access();
|
|
|
|
info!("PCI BS/DV/FN VEND:DEVI CL.SC.IN.RV");
|
|
|
|
'bus: for bus in PciIter::new(pci) {
|
|
'dev: for dev in bus.devs() {
|
|
for func in dev.funcs() {
|
|
let func_num = func.num;
|
|
match PciHeader::from_reader(func) {
|
|
Ok(header) => {
|
|
handle_parsed_header(Arc::clone(&state), &config, bus.num, dev.num, func_num, header);
|
|
}
|
|
Err(PciHeaderError::NoDevice) => {
|
|
if func_num == 0 {
|
|
if dev.num == 0 {
|
|
trace!("PCI {:>02X}: no bus", bus.num);
|
|
continue 'bus;
|
|
} else {
|
|
trace!("PCI {:>02X}/{:>02X}: no dev", bus.num, dev.num);
|
|
continue 'dev;
|
|
}
|
|
}
|
|
},
|
|
Err(PciHeaderError::UnknownHeaderType(id)) => {
|
|
warn!("pcid: unknown header type: {}", id);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for thread in state.threads.lock().unwrap().drain(..) {
|
|
thread.join().unwrap();
|
|
}
|
|
}
|