bjorn3
300 lines
8.4 KiB
Rust
300 lines
8.4 KiB
Rust
#![feature(array_chunks)]
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#![feature(non_exhaustive_omitted_patterns_lint)]
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#![feature(iter_next_chunk)]
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#![feature(if_let_guard)]
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use std::collections::BTreeMap;
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use log::{debug, info, trace, warn};
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use pci_types::capability::PciCapability;
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use pci_types::{
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Bar as TyBar, CommandRegister, EndpointHeader, HeaderType, PciAddress,
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PciHeader as TyPciHeader, PciPciBridgeHeader,
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};
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use redox_scheme::{RequestKind, SignalBehavior};
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use crate::cfg_access::Pcie;
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use pcid_interface::{FullDeviceId, LegacyInterruptLine, PciBar, PciFunction};
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mod cfg_access;
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mod driver_handler;
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mod scheme;
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pub struct Func {
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inner: PciFunction,
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capabilities: Vec<PciCapability>,
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endpoint_header: EndpointHeader,
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enabled: bool,
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}
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fn handle_parsed_header(
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pcie: &Pcie,
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tree: &mut BTreeMap<PciAddress, Func>,
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endpoint_header: EndpointHeader,
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full_device_id: FullDeviceId,
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) {
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let mut bars = [PciBar::None; 6];
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let mut skip = false;
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for i in 0..6 {
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if skip {
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skip = false;
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continue;
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}
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match endpoint_header.bar(i, pcie) {
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Some(TyBar::Io { port }) => bars[i as usize] = PciBar::Port(port.try_into().unwrap()),
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Some(TyBar::Memory32 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory32 {
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addr: address,
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size,
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}
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}
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Some(TyBar::Memory64 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory64 {
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addr: address,
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size,
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};
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skip = true; // Each 64bit memory BAR occupies two slots
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}
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None => bars[i as usize] = PciBar::None,
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}
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}
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let mut string = String::new();
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for (i, bar) in bars.iter().enumerate() {
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if !bar.is_none() {
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string.push_str(&format!(" {i}={}", bar.display()));
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}
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}
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if !string.is_empty() {
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info!(" BAR{}", string);
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}
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let capabilities = if endpoint_header.status(pcie).has_capability_list() {
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endpoint_header.capabilities(pcie).collect::<Vec<_>>()
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} else {
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Vec::new()
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};
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debug!(
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"PCI DEVICE CAPABILITIES for {}: {:?}",
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endpoint_header.header().address(),
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capabilities
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);
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let func = Func {
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inner: pcid_interface::PciFunction {
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bars,
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addr: endpoint_header.header().address(),
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legacy_interrupt_line: None, // Will be filled in when enabling the device
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full_device_id: full_device_id.clone(),
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},
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capabilities,
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endpoint_header,
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enabled: false,
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};
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tree.insert(func.inner.addr, func);
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}
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fn enable_function(
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pcie: &Pcie,
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endpoint_header: &mut EndpointHeader,
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) -> Option<LegacyInterruptLine> {
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// Enable bus mastering, memory space, and I/O space
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endpoint_header.update_command(pcie, |cmd| {
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cmd | CommandRegister::BUS_MASTER_ENABLE
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| CommandRegister::MEMORY_ENABLE
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| CommandRegister::IO_ENABLE
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});
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// Set IRQ line to 9 if not set
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let mut irq = 0xFF;
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let mut interrupt_pin = 0xFF;
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endpoint_header.update_interrupt(pcie, |(pin, mut line)| {
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if line == 0xFF {
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line = 9;
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}
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irq = line;
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interrupt_pin = pin;
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(pin, line)
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});
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let legacy_interrupt_enabled = match interrupt_pin {
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0 => false,
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1 | 2 | 3 | 4 => true,
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other => {
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warn!("pcid: invalid interrupt pin: {}", other);
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false
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}
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};
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if legacy_interrupt_enabled {
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let pci_address = endpoint_header.header().address();
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let dt_address = ((pci_address.bus() as u32) << 16)
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| ((pci_address.device() as u32) << 11)
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| ((pci_address.function() as u32) << 8);
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let addr = [
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dt_address & pcie.interrupt_map_mask[0],
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0u32,
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0u32,
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interrupt_pin as u32 & pcie.interrupt_map_mask[3],
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];
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let mapping = pcie
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.interrupt_map
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.iter()
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.find(|x| x.addr == addr[0..3] && x.interrupt == addr[3]);
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let phandled = if let Some(mapping) = mapping {
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Some((
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mapping.parent_phandle,
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mapping.parent_interrupt,
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mapping.parent_interrupt_cells,
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))
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} else {
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None
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};
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if mapping.is_some() {
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debug!("found mapping: addr={:?} => {:?}", addr, phandled);
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}
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Some(LegacyInterruptLine { irq, phandled })
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} else {
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None
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}
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}
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fn main() {
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let mut args = pico_args::Arguments::from_env();
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let verbosity = (0..).find(|_| !args.contains("-v")).unwrap_or(0);
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let log_level = match verbosity {
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0 => log::LevelFilter::Info,
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1 => log::LevelFilter::Debug,
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_ => log::LevelFilter::Trace,
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};
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common::setup_logging("bus", "pci", "pcid", log_level, log::LevelFilter::Trace);
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redox_daemon::Daemon::new(move |daemon| main_inner(daemon)).unwrap();
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}
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fn main_inner(daemon: redox_daemon::Daemon) -> ! {
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let pcie = Pcie::new();
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let mut tree = BTreeMap::new();
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info!("PCI SG-BS:DV.F VEND:DEVI CL.SC.IN.RV");
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// FIXME Use full ACPI for enumerating the host bridges. MCFG only describes the first
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// host bridge, while multi-processor systems likely have a host bridge for each CPU.
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// See also https://www.kernel.org/doc/html/latest/PCI/acpi-info.html
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let mut bus_nums = vec![0];
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let mut bus_i = 0;
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while bus_i < bus_nums.len() {
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let bus_num = bus_nums[bus_i];
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bus_i += 1;
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for dev_num in 0..32 {
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scan_device(&mut tree, &pcie, &mut bus_nums, bus_num, dev_num);
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}
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}
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info!("Enumeration complete, now starting pci scheme");
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let mut scheme = scheme::PciScheme::new(pcie, tree);
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let socket = redox_scheme::Socket::create("pci").expect("failed to open pci scheme socket");
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let _ = daemon.ready();
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loop {
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let Some(request) = socket
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.next_request(SignalBehavior::Restart)
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.expect("pcid: failed to get next scheme request")
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else {
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break;
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};
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match request.kind() {
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RequestKind::Call(call) => {
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let response = call.handle_scheme(&mut scheme);
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socket
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.write_responses(&[response], SignalBehavior::Restart)
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.expect("pcid: failed to write next scheme response");
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}
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RequestKind::OnClose { id } => {
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scheme.on_close(id);
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}
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_ => (),
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}
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}
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println!("pcid: exit");
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std::process::exit(0);
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}
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fn scan_device(
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tree: &mut BTreeMap<PciAddress, Func>,
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pcie: &Pcie,
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bus_nums: &mut Vec<u8>,
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bus_num: u8,
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dev_num: u8,
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) {
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for func_num in 0..8 {
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let header = TyPciHeader::new(PciAddress::new(0, bus_num, dev_num, func_num));
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let (vendor_id, device_id) = header.id(pcie);
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if vendor_id == 0xffff && device_id == 0xffff {
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if func_num == 0 {
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trace!("PCI {:>02X}:{:>02X}: no dev", bus_num, dev_num);
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return;
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}
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continue;
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}
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let (revision, class, subclass, interface) = header.revision_and_class(pcie);
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let full_device_id = FullDeviceId {
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vendor_id,
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device_id,
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class,
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subclass,
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interface,
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revision,
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};
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info!("PCI {} {}", header.address(), full_device_id.display());
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let has_multiple_functions = header.has_multiple_functions(pcie);
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match header.header_type(pcie) {
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HeaderType::Endpoint => {
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handle_parsed_header(
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pcie,
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tree,
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EndpointHeader::from_header(header, pcie).unwrap(),
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full_device_id,
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);
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}
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HeaderType::PciPciBridge => {
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let bridge_header = PciPciBridgeHeader::from_header(header, pcie).unwrap();
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bus_nums.push(bridge_header.secondary_bus_number(pcie));
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}
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ty => {
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warn!("pcid: unknown header type: {ty:?}");
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}
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}
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if func_num == 0 && !has_multiple_functions {
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return;
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}
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}
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}
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