Jeremy Soller
236 lines
6.8 KiB
Rust
236 lines
6.8 KiB
Rust
use std::{
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sync::{Arc, Mutex},
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};
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use syscall::{
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error::{Error, Result, EIO},
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io::{Io, Pio, ReadOnly, WriteOnly},
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};
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use crate::ata::AtaCommand;
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#[cfg(target_arch = "aarch64")]
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#[inline(always)]
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pub(crate) unsafe fn pause() { std::arch::aarch64::__yield(); }
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#[cfg(target_arch = "x86")]
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#[inline(always)]
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pub(crate) unsafe fn pause() { std::arch::x86::_mm_pause(); }
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#[cfg(target_arch = "x86_64")]
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#[inline(always)]
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pub(crate) unsafe fn pause() { std::arch::x86_64::_mm_pause(); }
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pub struct Channel {
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pub data8: Pio<u8>,
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pub data32: Pio<u32>,
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pub error: ReadOnly<Pio<u8>>,
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pub features: WriteOnly<Pio<u8>>,
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pub sector_count: Pio<u8>,
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pub lba_0: Pio<u8>,
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pub lba_1: Pio<u8>,
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pub lba_2: Pio<u8>,
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pub device_select: Pio<u8>,
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pub status: ReadOnly<Pio<u8>>,
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pub command: WriteOnly<Pio<u8>>,
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pub alt_status: ReadOnly<Pio<u8>>,
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pub control: WriteOnly<Pio<u8>>,
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}
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impl Channel {
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pub fn new(base: u16, control_base: u16) -> Self {
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Self {
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data8: Pio::new(base + 0),
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data32: Pio::new(base + 0),
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error: ReadOnly::new(Pio::new(base + 1)),
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features: WriteOnly::new(Pio::new(base + 1)),
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sector_count: Pio::new(base + 2),
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lba_0: Pio::new(base + 3),
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lba_1: Pio::new(base + 4),
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lba_2: Pio::new(base + 5),
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device_select: Pio::new(base + 6),
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status: ReadOnly::new(Pio::new(base + 7)),
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command: WriteOnly::new(Pio::new(base + 7)),
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alt_status: ReadOnly::new(Pio::new(control_base)),
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control: WriteOnly::new(Pio::new(control_base)),
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}
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}
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pub fn primary_compat() -> Self {
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Self::new(0x1F0, 0x3F6)
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}
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pub fn secondary_compat() -> Self {
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Self::new(0x170, 0x376)
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}
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fn polling(&mut self, check: bool) -> Result<()> {
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/*
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#define ATA_SR_BSY 0x80 // Busy
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#define ATA_SR_DRDY 0x40 // Drive ready
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#define ATA_SR_DF 0x20 // Drive write fault
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#define ATA_SR_DSC 0x10 // Drive seek complete
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#define ATA_SR_DRQ 0x08 // Data request ready
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#define ATA_SR_CORR 0x04 // Corrected data
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#define ATA_SR_IDX 0x02 // Index
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#define ATA_SR_ERR 0x01 // Error
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*/
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for _ in 0..4 {
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// Doing this 4 times creates a 400ns delay
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self.alt_status.read();
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}
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while self.status.readf(0x80) {
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unsafe { pause(); }
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}
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if check {
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let status = self.status.read();
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if status & 0x01 != 0 {
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log::error!("IDE error");
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return Err(Error::new(EIO));
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}
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if status & 0x20 != 0 {
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log::error!("IDE device write fault");
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return Err(Error::new(EIO));
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}
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if status & 0x08 == 0 {
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log::error!("IDE data not ready");
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return Err(Error::new(EIO));
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}
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}
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Ok(())
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}
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}
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pub trait Disk {
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fn id(&self) -> usize;
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fn size(&mut self) -> u64;
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fn read(&mut self, block: u64, buffer: &mut [u8]) -> Result<Option<usize>>;
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fn write(&mut self, block: u64, buffer: &[u8]) -> Result<Option<usize>>;
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fn block_length(&mut self) -> Result<u32>;
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}
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pub struct AtaDisk {
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pub chan: Arc<Mutex<Channel>>,
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pub chan_i: usize,
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pub dev: u8,
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pub size: u64,
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}
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impl Disk for AtaDisk {
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fn id(&self) -> usize {
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self.chan_i << 1 | self.dev as usize
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}
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fn size(&mut self) -> u64 {
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self.size
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}
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fn read(&mut self, block: u64, buffer: &mut [u8]) -> Result<Option<usize>> {
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//TODO: support other LBA modes
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assert!(block < 0x1_0000_0000_0000);
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let sectors = buffer.len() / 512;
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assert!(sectors < 0x1_0000);
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let mut chan = self.chan.lock().unwrap();
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// Select drive
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chan.device_select.write(0xE0 | (self.dev << 4));
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// Set high sector count and LBA
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//TODO: only if LBA mode is 48-bit
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chan.control.writef(0x80, true);
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chan.sector_count.write((sectors >> 8) as u8);
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chan.lba_0.write((block >> 24) as u8);
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chan.lba_1.write((block >> 32) as u8);
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chan.lba_2.write((block >> 40) as u8);
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chan.control.writef(0x80, false);
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// Set low sector count and LBA
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chan.sector_count.write(sectors as u8);
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chan.lba_0.write(block as u8);
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chan.lba_1.write((block >> 8) as u8);
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chan.lba_2.write((block >> 16) as u8);
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// Send command
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//TODO: use DMA
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chan.command.write(AtaCommand::ReadPioExt as u8);
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// Read data
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for sector in 0..sectors {
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chan.polling(true)?;
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for i in 0..128 {
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let data = chan.data32.read();
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buffer[sector * 512 + i * 4 + 0] = (data >> 0) as u8;
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buffer[sector * 512 + i * 4 + 1] = (data >> 8) as u8;
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buffer[sector * 512 + i * 4 + 2] = (data >> 16) as u8;
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buffer[sector * 512 + i * 4 + 3] = (data >> 24) as u8;
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}
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}
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Ok(Some(sectors * 512))
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}
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fn write(&mut self, block: u64, buffer: &[u8]) -> Result<Option<usize>> {
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//TODO: support other LBA modes
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assert!(block < 0x1_0000_0000_0000);
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let sectors = buffer.len() / 512;
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assert!(sectors < 0x1_0000);
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let mut chan = self.chan.lock().unwrap();
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// Select drive
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chan.device_select.write(0xE0 | (self.dev << 4));
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// Set high sector count and LBA
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//TODO: only if LBA mode is 48-bit
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chan.control.writef(0x80, true);
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chan.sector_count.write((sectors >> 8) as u8);
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chan.lba_0.write((block >> 24) as u8);
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chan.lba_1.write((block >> 32) as u8);
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chan.lba_2.write((block >> 40) as u8);
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chan.control.writef(0x80, false);
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// Set low sector count and LBA
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chan.sector_count.write(sectors as u8);
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chan.lba_0.write(block as u8);
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chan.lba_1.write((block >> 8) as u8);
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chan.lba_2.write((block >> 16) as u8);
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// Send command
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//TODO: use DMA
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chan.command.write(AtaCommand::WritePioExt as u8);
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// Write data
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for sector in 0..sectors {
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chan.polling(false)?;
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for i in 0..128 {
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chan.data32.write(
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((buffer[sector * 512 + i * 4 + 0] as u32) << 0) |
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((buffer[sector * 512 + i * 4 + 1] as u32) << 8) |
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((buffer[sector * 512 + i * 4 + 2] as u32) << 16) |
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((buffer[sector * 512 + i * 4 + 3] as u32) << 24)
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);
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}
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}
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chan.command.write(AtaCommand::CacheFlushExt as u8);
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chan.polling(false)?;
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Ok(Some(sectors * 512))
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}
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fn block_length(&mut self) -> Result<u32> {
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Ok(512)
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}
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}
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