4lDO2
331 lines
11 KiB
Rust
331 lines
11 KiB
Rust
use core::num::NonZeroU8;
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use core::sync::atomic::{AtomicU64, Ordering};
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use core::mem;
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use alloc::boxed::Box;
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use alloc::collections::BTreeMap;
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use x86::segmentation::Descriptor as X86IdtEntry;
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use x86::dtables::{self, DescriptorTablePointer};
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use crate::interrupt::*;
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use crate::ipi::IpiKind;
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use spin::RwLock;
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pub static mut INIT_IDTR: DescriptorTablePointer<X86IdtEntry> = DescriptorTablePointer {
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limit: 0,
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base: 0 as *const X86IdtEntry
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};
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pub type IdtEntries = [IdtEntry; 256];
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pub type IdtReservations = [AtomicU64; 4];
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#[repr(C)]
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pub struct Idt {
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entries: IdtEntries,
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reservations: IdtReservations,
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}
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impl Idt {
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pub const fn new() -> Self {
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Self {
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entries: [IdtEntry::new(); 256],
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reservations: new_idt_reservations(),
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}
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}
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#[inline]
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pub fn is_reserved(&self, index: u8) -> bool {
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let byte_index = index / 64;
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let bit = index % 64;
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{ &self.reservations[usize::from(byte_index)] }.load(Ordering::Acquire) & (1 << bit) != 0
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}
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#[inline]
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pub fn set_reserved(&self, index: u8, reserved: bool) {
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let byte_index = index / 64;
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let bit = index % 64;
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{ &self.reservations[usize::from(byte_index)] }.fetch_or(u64::from(reserved) << bit, Ordering::AcqRel);
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}
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#[inline]
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pub fn is_reserved_mut(&mut self, index: u8) -> bool {
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let byte_index = index / 64;
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let bit = index % 64;
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*{ &mut self.reservations[usize::from(byte_index)] }.get_mut() & (1 << bit) != 0
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}
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#[inline]
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pub fn set_reserved_mut(&mut self, index: u8, reserved: bool) {
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let byte_index = index / 64;
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let bit = index % 64;
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*{ &mut self.reservations[usize::from(byte_index)] }.get_mut() |= u64::from(reserved) << bit;
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}
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}
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static mut INIT_BSP_IDT: Idt = Idt::new();
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// TODO: VecMap?
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pub static IDTS: RwLock<Option<BTreeMap<usize, &'static mut Idt>>> = RwLock::new(None);
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#[inline]
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pub fn is_reserved(cpu_id: usize, index: u8) -> bool {
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let byte_index = index / 64;
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let bit = index % 64;
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{ &IDTS.read().as_ref().unwrap().get(&cpu_id).unwrap().reservations[usize::from(byte_index)] }.load(Ordering::Acquire) & (1 << bit) != 0
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}
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#[inline]
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pub fn set_reserved(cpu_id: usize, index: u8, reserved: bool) {
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let byte_index = index / 64;
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let bit = index % 64;
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{ &IDTS.read().as_ref().unwrap().get(&cpu_id).unwrap().reservations[usize::from(byte_index)] }.fetch_or(u64::from(reserved) << bit, Ordering::AcqRel);
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}
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pub fn allocate_interrupt() -> Option<NonZeroU8> {
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let cpu_id = crate::cpu_id();
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for number in 50..=254 {
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if ! is_reserved(cpu_id, number) {
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set_reserved(cpu_id, number, true);
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return Some(unsafe { NonZeroU8::new_unchecked(number) });
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}
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}
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None
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}
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pub fn available_irqs_iter(cpu_id: usize) -> impl Iterator<Item = u8> + 'static {
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(32..=254).filter(move |&index| !is_reserved(cpu_id, index))
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}
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macro_rules! use_irq(
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( $idt: expr, $number:literal, $func:ident ) => {{
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$idt[$number].set_func($func);
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}}
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);
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macro_rules! use_default_irqs(
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($idt:expr) => {{
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use crate::interrupt::irq::*;
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default_irqs!($idt, use_irq);
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}}
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);
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pub unsafe fn init() {
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dtables::lidt(&INIT_IDTR);
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}
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const fn new_idt_reservations() -> [AtomicU64; 4] {
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[AtomicU64::new(0), AtomicU64::new(0), AtomicU64::new(0), AtomicU64::new(0)]
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}
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/// Initialize the IDT for a
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pub unsafe fn init_paging_post_heap(is_bsp: bool, cpu_id: usize) {
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let mut idts_guard = IDTS.write();
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let idts_btree = idts_guard.get_or_insert_with(BTreeMap::new);
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if is_bsp {
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idts_btree.insert(cpu_id, &mut INIT_BSP_IDT);
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} else {
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let idt = idts_btree.entry(cpu_id).or_insert_with(|| Box::leak(Box::new(Idt::new())));
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init_generic(is_bsp, idt);
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}
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}
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/// Initializes a fully functional IDT for use before it be moved into the map. This is ONLY called
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/// on the BSP, since the kernel heap is ready for the APs.
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pub unsafe fn init_paging_bsp() {
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init_generic(true, &mut INIT_BSP_IDT);
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}
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/// Initializes an IDT for any type of processor.
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pub unsafe fn init_generic(is_bsp: bool, idt: &mut Idt) {
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let (current_idt, current_reservations) = (&mut idt.entries, &mut idt.reservations);
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let idtr: DescriptorTablePointer<X86IdtEntry> = DescriptorTablePointer {
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limit: (current_idt.len() * mem::size_of::<IdtEntry>() - 1) as u16,
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base: current_idt.as_ptr() as *const X86IdtEntry,
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};
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let backup_ist = {
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// We give Non-Maskable Interrupts, Double Fault, and Machine Check exceptions separate
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// stacks, since these (unless we are going to set up NMI watchdogs like Linux does) are
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// considered the most fatal, especially Double Faults which are caused by errors __when
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// accessing the system IDT__. If that goes wrong, then kernel memory may be partially
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// corrupt, and we want a separate stack.
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//
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// Note that each CPU has its own "backup interrupt stack".
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let index = 1_u8;
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// Allocate 64 KiB of stack space for the backup stack.
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const BACKUP_STACK_SIZE: usize = 65536;
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assert_eq!(BACKUP_STACK_SIZE % crate::memory::PAGE_SIZE, 0);
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let page_count = BACKUP_STACK_SIZE / crate::memory::PAGE_SIZE;
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let frames = crate::memory::allocate_frames(page_count)
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.expect("failed to allocate pages for backup interrupt stack");
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use crate::paging::{RmmA, RmmArch};
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// Physical pages are mapped linearly. So is the linearly mapped virtual memory.
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let base_address = RmmA::phys_to_virt(frames.start_address());
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// Stack always grows downwards.
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let address = base_address.data() + BACKUP_STACK_SIZE;
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// Put them in the 1st entry of the IST.
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(*crate::gdt::pcr()).tss.ist[usize::from(index - 1)] = address as u64;
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index
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};
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// Set up exceptions
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current_idt[0].set_func(exception::divide_by_zero);
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current_idt[1].set_func(exception::debug);
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current_idt[2].set_func(exception::non_maskable);
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current_idt[2].set_ist(backup_ist);
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current_idt[3].set_func(exception::breakpoint);
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current_idt[3].set_flags(IdtFlags::PRESENT | IdtFlags::RING_3 | IdtFlags::INTERRUPT);
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current_idt[4].set_func(exception::overflow);
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current_idt[5].set_func(exception::bound_range);
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current_idt[6].set_func(exception::invalid_opcode);
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current_idt[7].set_func(exception::device_not_available);
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current_idt[8].set_func(exception::double_fault);
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current_idt[8].set_ist(backup_ist);
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// 9 no longer available
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current_idt[10].set_func(exception::invalid_tss);
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current_idt[11].set_func(exception::segment_not_present);
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current_idt[12].set_func(exception::stack_segment);
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current_idt[13].set_func(exception::protection);
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current_idt[14].set_func(exception::page);
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// 15 reserved
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current_idt[16].set_func(exception::fpu_fault);
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current_idt[17].set_func(exception::alignment_check);
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current_idt[18].set_func(exception::machine_check);
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current_idt[18].set_ist(backup_ist);
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current_idt[19].set_func(exception::simd);
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current_idt[20].set_func(exception::virtualization);
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// 21 through 29 reserved
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current_idt[30].set_func(exception::security);
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// 31 reserved
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// reserve bits 31:0, i.e. the first 32 interrupts, which are reserved for exceptions
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*current_reservations[0].get_mut() |= 0x0000_0000_FFFF_FFFF;
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if is_bsp {
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// Set up IRQs
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current_idt[32].set_func(irq::pit_stack);
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current_idt[33].set_func(irq::keyboard);
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current_idt[34].set_func(irq::cascade);
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current_idt[35].set_func(irq::com2);
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current_idt[36].set_func(irq::com1);
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current_idt[37].set_func(irq::lpt2);
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current_idt[38].set_func(irq::floppy);
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current_idt[39].set_func(irq::lpt1);
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current_idt[40].set_func(irq::rtc);
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current_idt[41].set_func(irq::pci1);
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current_idt[42].set_func(irq::pci2);
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current_idt[43].set_func(irq::pci3);
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current_idt[44].set_func(irq::mouse);
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current_idt[45].set_func(irq::fpu);
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current_idt[46].set_func(irq::ata1);
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current_idt[47].set_func(irq::ata2);
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current_idt[48].set_func(irq::lapic_timer);
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current_idt[49].set_func(irq::lapic_error);
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// reserve bits 49:32, which are for the standard IRQs, and for the local apic timer and error.
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*current_reservations[0].get_mut() |= 0x0003_FFFF_0000_0000;
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} else {
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// TODO: use_default_irqs! but also the legacy IRQs that are only needed on one CPU
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current_idt[49].set_func(irq::lapic_error);
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// reserve bit 49
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*current_reservations[0].get_mut() |= 1 << 49;
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}
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use_default_irqs!(current_idt);
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// Set IPI handlers
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current_idt[IpiKind::Wakeup as usize].set_func(ipi::wakeup);
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current_idt[IpiKind::Switch as usize].set_func(ipi::switch);
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current_idt[IpiKind::Tlb as usize].set_func(ipi::tlb);
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current_idt[IpiKind::Pit as usize].set_func(ipi::pit);
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idt.set_reserved_mut(IpiKind::Wakeup as u8, true);
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idt.set_reserved_mut(IpiKind::Switch as u8, true);
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idt.set_reserved_mut(IpiKind::Tlb as u8, true);
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idt.set_reserved_mut(IpiKind::Pit as u8, true);
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let current_idt = &mut idt.entries;
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// Set syscall function
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current_idt[0x80].set_func(syscall::syscall);
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current_idt[0x80].set_flags(IdtFlags::PRESENT | IdtFlags::RING_3 | IdtFlags::INTERRUPT);
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idt.set_reserved_mut(0x80, true);
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dtables::lidt(&idtr);
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}
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bitflags! {
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pub struct IdtFlags: u8 {
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const PRESENT = 1 << 7;
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const RING_0 = 0 << 5;
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const RING_1 = 1 << 5;
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const RING_2 = 2 << 5;
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const RING_3 = 3 << 5;
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const SS = 1 << 4;
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const INTERRUPT = 0xE;
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const TRAP = 0xF;
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}
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}
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#[derive(Copy, Clone, Debug, Default)]
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#[repr(packed)]
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pub struct IdtEntry {
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offsetl: u16,
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selector: u16,
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zero: u8,
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attribute: u8,
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offsetm: u16,
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offseth: u32,
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_zero2: u32
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}
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impl IdtEntry {
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pub const fn new() -> IdtEntry {
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IdtEntry {
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offsetl: 0,
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selector: 0,
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zero: 0,
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attribute: 0,
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offsetm: 0,
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offseth: 0,
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_zero2: 0
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}
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}
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pub fn set_flags(&mut self, flags: IdtFlags) {
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self.attribute = flags.bits;
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}
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pub fn set_ist(&mut self, ist: u8) {
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assert_eq!(ist & 0x07, ist, "interrupt stack table must be within 0..=7");
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self.zero &= 0xF8;
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self.zero |= ist;
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}
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pub fn set_offset(&mut self, selector: u16, base: usize) {
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self.selector = selector;
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self.offsetl = base as u16;
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self.offsetm = (base >> 16) as u16;
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self.offseth = ((base as u64) >> 32) as u32;
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}
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// A function to set the offset more easily
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pub fn set_func(&mut self, func: unsafe extern fn()) {
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self.set_flags(IdtFlags::PRESENT | IdtFlags::RING_0 | IdtFlags::INTERRUPT);
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self.set_offset((crate::gdt::GDT_KERNEL_CODE as u16) << 3, func as usize);
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}
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}
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