Red Bear OS
324 lines
10 KiB
Rust
324 lines
10 KiB
Rust
use common::{
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io::{Io, MmioPtr},
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timeout::Timeout,
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};
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use syscall::error::{Error, Result, EIO};
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use super::MmioRegion;
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#[derive(Clone, Copy)]
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pub struct PowerWell {
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pub name: &'static str,
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pub depends: &'static [&'static str],
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pub ddis: &'static [&'static str],
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pub pipes: &'static [&'static str],
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pub transcoders: &'static [&'static str],
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pub request: u32,
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pub state: u32,
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pub fuse_status: u32,
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}
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pub struct PowerWells {
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pub ctl: MmioPtr<u32>,
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pub ctl_aux: MmioPtr<u32>,
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pub ctl_ddi: MmioPtr<u32>,
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pub fuse_status: MmioPtr<u32>,
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pub fuse_status_pg0: u32,
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pub wells: Vec<PowerWell>,
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}
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impl PowerWells {
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//TODO: return guard?
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pub fn enable_well(&mut self, name: &'static str) -> Result<()> {
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// Wait 20us for distribution of PG0
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{
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let timeout = Timeout::from_micros(20);
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while !self.fuse_status.readf(self.fuse_status_pg0) {
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timeout.run().map_err(|()| {
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log::warn!("timeout on distribution of power well 0");
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Error::new(EIO)
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})?;
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}
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}
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// self.wells iter copied to allow mutable self.enable_well later
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for well in self.wells.iter().copied() {
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if well.name == name {
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// Enable dependent wells
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for depend in well.depends.iter() {
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self.enable_well(depend)?;
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}
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if !self.ctl.readf(well.request) {
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log::info!("enabling power well {}", well.name);
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}
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// Set request bit
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self.ctl.writef(well.request, true);
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// Wait 100us for enabled state
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{
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let timeout = Timeout::from_micros(100);
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while !self.ctl.readf(well.state) {
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timeout.run().map_err(|()| {
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log::warn!("timeout enabling power well {}", well.name);
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Error::new(EIO)
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})?;
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}
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}
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// Wait 20us for distribution
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{
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let timeout = Timeout::from_micros(20);
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while !self.fuse_status.readf(well.fuse_status) {
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timeout.run().map_err(|()| {
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log::warn!("timeout on distribution of power well {}", well.name);
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Error::new(EIO)
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})?;
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}
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}
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return Ok(());
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}
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}
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log::warn!("power well {} not found", name);
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Err(Error::new(EIO))
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}
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pub fn enable_well_by_ddi(&mut self, name: &'static str) -> Result<()> {
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for well in self.wells.iter() {
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if well.ddis.contains(&name) {
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return self.enable_well(well.name);
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}
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}
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log::warn!("power well for DDI {} not found", name);
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Err(Error::new(EIO))
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}
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pub fn enable_well_by_pipe(&mut self, name: &'static str) -> Result<()> {
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for well in self.wells.iter() {
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if well.pipes.contains(&name) {
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return self.enable_well(well.name);
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}
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}
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log::warn!("power well for pipe {} not found", name);
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Err(Error::new(EIO))
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}
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pub fn enable_well_by_transcoder(&mut self, name: &'static str) -> Result<()> {
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for well in self.wells.iter() {
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if well.transcoders.contains(&name) {
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return self.enable_well(well.name);
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}
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}
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log::warn!("power well for transcoder {} not found", name);
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Err(Error::new(EIO))
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}
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pub fn kabylake(gttmm: &MmioRegion) -> Result<Self> {
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// IHD-OS-KBL-Vol 2c-1.17 PWR_WELL_CTL
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let ctl = unsafe { gttmm.mmio(0x45404)? };
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// Hack since these power ctl registers are combined
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let ctl_aux = unsafe { gttmm.mmio(0x45404)? };
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let ctl_ddi = unsafe { gttmm.mmio(0x45404)? };
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// IHD-OS-KBL-Vol 2c-1.17 FUSE_STATUS
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let fuse_status = unsafe { gttmm.mmio(0x42000)? };
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let fuse_status_pg0 = 1 << 27;
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let wells = vec![
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PowerWell {
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name: "1",
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depends: &[],
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ddis: &["A"],
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pipes: &["A"],
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transcoders: &["EDP"],
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request: 1 << 29,
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state: 1 << 28,
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fuse_status: 1 << 26,
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},
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PowerWell {
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name: "2",
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depends: &["1"],
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ddis: &["B", "C", "D", "E"],
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pipes: &["B", "C"],
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transcoders: &["A", "B", "C"],
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request: 1 << 31,
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state: 1 << 30,
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fuse_status: 1 << 25,
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},
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];
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Ok(Self {
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ctl,
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ctl_aux,
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ctl_ddi,
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fuse_status,
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fuse_status_pg0,
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wells,
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})
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}
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pub fn tigerlake(gttmm: &MmioRegion) -> Result<Self> {
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// IHD-OS-TGL-Vol 2c-12.21 PWR_WELL_CTL
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let ctl = unsafe { gttmm.mmio(0x45404)? };
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// IHD-OS-TGL-Vol 2c-12.21 PWR_WELL_CTL_AUX
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let ctl_aux = unsafe { gttmm.mmio(0x45444)? };
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// IHD-OS-TGL-Vol 2c-12.21 PWR_WELL_CTL_DDI
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let ctl_ddi = unsafe { gttmm.mmio(0x45454)? };
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// IHD-OS-TGL-Vol 2c-12.21 FUSE_STATUS
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let fuse_status = unsafe { gttmm.mmio(0x42000)? };
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let fuse_status_pg0 = 1 << 27;
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let wells = vec![
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// DBUF functionality, Pipe A, Transcoder A and DSI, DDI A-C, FBC, DSS
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PowerWell {
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name: "1",
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depends: &[],
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ddis: &["A", "B", "C"],
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pipes: &["A"],
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transcoders: &["A"],
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request: 1 << 1,
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state: 1 << 0,
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fuse_status: 1 << 26,
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},
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// VDSC for pipe A
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PowerWell {
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name: "2",
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depends: &["1"],
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ddis: &[],
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pipes: &[],
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transcoders: &[],
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request: 1 << 3,
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state: 1 << 2,
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fuse_status: 1 << 25,
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},
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// Pipe B, Audio, Transcoder WD, VGA, Transcoder B, DDI USBC1-6, KVMR
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PowerWell {
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name: "3",
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depends: &["2"],
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ddis: &["USBC1", "USBC2", "USBC3", "USBC4", "USBC5", "USBC6"],
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pipes: &["B"],
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transcoders: &["B"],
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request: 1 << 5,
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state: 1 << 4,
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fuse_status: 1 << 24,
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},
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// Pipe C, Transcoder C
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PowerWell {
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name: "4",
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depends: &["3"],
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ddis: &[],
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pipes: &["C"],
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transcoders: &["C"],
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request: 1 << 7,
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state: 1 << 6,
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fuse_status: 1 << 23,
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},
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// Pipe D, Transcoder D
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PowerWell {
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name: "5",
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depends: &["4"],
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ddis: &[],
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pipes: &["D"],
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transcoders: &["D"],
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request: 1 << 9,
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state: 1 << 8,
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fuse_status: 1 << 22,
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},
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];
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Ok(Self {
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ctl,
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ctl_aux,
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ctl_ddi,
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fuse_status,
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fuse_status_pg0,
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wells,
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})
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}
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pub fn alchemist(gttmm: &MmioRegion) -> Result<Self> {
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// IHD-OS-ACM-Vol 2c-3.23 PWR_WELL_CTL
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let ctl = unsafe { gttmm.mmio(0x45404)? };
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// IHD-OS-ACM-Vol 2c-3.23 PWR_WELL_CTL_AUX
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let ctl_aux = unsafe { gttmm.mmio(0x45444)? };
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// IHD-OS-ACM-Vol 2c-3.23 PWR_WELL_CTL_DDI
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let ctl_ddi = unsafe { gttmm.mmio(0x45454)? };
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// IHD-OS-ACM-Vol 2c-3.23 FUSE_STATUS
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let fuse_status = unsafe { gttmm.mmio(0x42000)? };
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let fuse_status_pg0 = 1 << 27;
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let wells = vec![
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// DBUF functionality, Transcoder A, DDI A-B
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PowerWell {
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name: "1",
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depends: &[],
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ddis: &["A", "B"],
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pipes: &[],
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transcoders: &["A"],
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request: 1 << 1,
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state: 1 << 0,
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fuse_status: 1 >> 26,
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},
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// Audio playback, Transcoder WD, VGA, DDI C-E, Type-C, KVMR
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PowerWell {
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name: "2",
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depends: &["1"],
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ddis: &["C", "D", "E", "USBC1", "USBC2", "USBC3", "USBC4"],
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pipes: &[],
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transcoders: &[],
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request: 1 << 3,
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state: 1 << 2,
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fuse_status: 1 << 25,
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},
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// Pipe A, FBC
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PowerWell {
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name: "A",
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depends: &["1"],
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ddis: &[],
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pipes: &["A"],
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transcoders: &[],
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request: 1 << 11,
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state: 1 << 10,
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fuse_status: 1 << 21,
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},
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// Pipe B, Transcoder B
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PowerWell {
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name: "B",
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depends: &["2"],
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ddis: &[],
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pipes: &["B"],
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transcoders: &["B"],
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request: 1 << 13,
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state: 1 << 12,
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fuse_status: 1 << 20,
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},
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// Pipe C, Transcoder C
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PowerWell {
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name: "C",
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depends: &["2"],
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ddis: &[],
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pipes: &["C"],
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transcoders: &["C"],
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request: 1 << 15,
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state: 1 << 14,
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fuse_status: 1 << 19,
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},
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// Pipe D, Transcoder D
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PowerWell {
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name: "D",
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depends: &["2"],
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ddis: &[],
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pipes: &["D"],
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transcoders: &["D"],
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request: 1 << 17,
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state: 1 << 16,
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fuse_status: 1 << 18,
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},
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];
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Ok(Self {
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ctl,
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ctl_aux,
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ctl_ddi,
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fuse_status,
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fuse_status_pg0,
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wells,
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})
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}
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}
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