intel: batch buffer + fence timeline (Phase 4 render path)
Add batch.rs — GPU command buffer construction helpers.
- BatchBuffer: append-style command builder for MI_BATCH_BUFFER_START,
MI_FLUSH_DW, MI_STORE_DWORD_IMM, MI_STORE_DATA_IMM,
MI_USER_INTERRUPT, MI_ARB_CHECK, MI_NOOP, PIPE_CONTROL
(flush L3 + CS stall + global GTT write + store data index)
- mi_flush_dw_cmd(), mi_batch_buffer_end_cmd() helpers
- PPGTT directory init helper
Add fence.rs — GPU/CPU synchronization.
- FenceTimeline: atomic seqno allocation and signal tracking
compare_exchange for lock-free concurrent signaling
- Fence: per-submission fence with signal() and wait_timeout()
Spin-wait with configurable timeout
- Send + Sync for cross-thread fence passing
Modules declared but not yet wired into IntelDriver struct.
Linux reference: i915_sw_fence.c, i915_gem_execbuffer.c
vasilito
493555b105