dp_link.rs: expanded rate table to 7 entries
HBR2 (8.1Gbps), HBR3 (8.1Gbps), UHBR10/13.5/20 for DP 2.0
rate_to_khz handles all 7 rates including UHBR (1-2M kHz)
display.rs: distinct HDMI vs DP enable paths in set_mode
connector_type parameter branches DP link retrain vs HDMI
HDMI paths skip link training (uses TMDS clock instead)
mod.rs: multi-engine ring initialization
Blitter (BCS) and VideoEnhance (VECS) rings alongside Render (RCS)
Optional init — gracefully handled if ring creation fails
Stored as Mutex<Option<IntelRing>> for lazy access
vasilito
442d450ae7