Investigation confirmed Intel display register offsets are IDENTICAL from
Gen8 (Skylake) through Gen14 (Meteor Lake): PIPECONF=0x70008,
PLANE_CTL=0x70180, PLANE_SURF=0x7019C, DDI_BUF_CTL=0x64000, HTOTAL=0x60000.
The only Gen14-specific branch is CHICKEN_TRANS. The original Phase 3.2
hypothesis (per-gen register offset tables) was therefore wrong.
The real gap for MTL was DMC (Display Microcontroller) firmware loading,
which is required for MTL display bringup. This commit adds:
- dmc.rs: Full DMC firmware parser supporting both v1 and v3 header
formats. Parses CSS header, package header, DMC header, validates
magic/version/checksum, then loads payload via MMIO into the DMC
SRAM regions defined by the DMC_PROGRAM() macro.
- DisplayPlatform enum (Gen9/11/12/13/14) with device-id-based
detection covering SKL, KBL, ICL, TGL, ADL, RPL, MTL platforms.
- try_load_dmc() entry point wired into IntelDriver::new() between
forcewake init and display init, matching the Linux i915 sequence.
- 5 unit tests covering header parsing, platform detection, and
payload validation.
Also fixes 4 pre-existing _mmio -> mmio references in virtio test code
that were blocking all test compilation in the redox-drm crate.
Verified: cargo check clean (zero errors, zero warnings from new code).
vasilito
40c3977552