vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
46 lines
2.6 KiB
Plaintext
46 lines
2.6 KiB
Plaintext
#------------------------------------------------------------------------------
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# $File: ringdove,v 1.1 2022/08/16 12:04:30 christos Exp $
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# ringdove: file(1) magic for RingdoveEDA data files
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# librnd and global
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0 regex/128l ha:rnd-menu-v[0-9]+[\ \t\r\n]*[{] librnd menu system (lihata)
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0 regex/128l ha:rnd-menu-patch-v[0-9]+[\ \t\r\n]*[{] librnd menu patch (lihata)
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0 regex/128l ha:coraleda-project-v[0-9]+[\ \t\r\n]*[{] CoralEDA/Ringdove project file (lihata)
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0 regex/128l ha:ringdove-project-v[0-9]+[\ \t\r\n]*[{] Ringdove project file (lihata)
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# pcb-rnd
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0 regex/128l ha:pcb-rnd-board-v[0-9]+[\ \t\r\n]*[{] pcb-rnd board file (lihata)
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0 regex/128l li:pcb-rnd-subcircuit-v[0-9]+[\ \t\r\n]*[{] pcb-rnd subcircuit/footprint file (lihata)
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0 regex/128l ha:pcb-rnd-buffer-v[0-9]+[\ \t\r\n]*[{] pcb-rnd paste buffer content (lihata)
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0 regex/128l li:pcb-rnd-conf-v[0-9]+[\ \t\r\n]*[{] pcb-rnd configuration (lihata)
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0 regex/128l ha:pcb-rnd-drc-query-v[0-9]+[\ \t\r\n]*[{] pcb-rnd drc query string (lihata)
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0 regex/128l li:pcb-rnd-font-v[0-9]+[\ \t\r\n]*[{] pcb-rnd vector font (lihata)
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0 regex/128l ha:pcb-rnd-log-v[0-9]+[\ \t\r\n]*[{] pcb-rnd message log dump (lihata)
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0 regex/128l ha:pcb-rnd-padstack-v[0-9]+[\ \t\r\n]*[{] pcb-rnd padstack (lihata)
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0 regex/128l li:pcb-rnd-view-list-v[0-9]+[\ \t\r\n]*[{] pcb-rnd view list (lihata)
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0 regex/128l li:view-list-v[0-9]+[\ \t\r\n]*[{] pcb-rnd view list (lihata)
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0 search Netlist(Freeze) pcb-rnd or gEDA/PCB netlist forward annotation action script
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# sch-rnd (cschem data model)
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0 regex/128l li:cschem-buffer-v[0-9]+[\ \t\r\n]*[{] sch-rnd/cschem buffer content (lihata)
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0 regex/128l li:sch-rnd-conf-v[0-9]+[\ \t\r\n]*[{] sch-rnd configuration (lihata)
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0 regex/128l ha:std_devmap.v[0-9]+[\ \t\r\n]*[{] sch-rnd devmap (device mapping; lihata)
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0 regex/128l li:cschem-group-v[0-9]+[\ \t\r\n]*[{] sch-rnd/cschem group or symbol (lihata)
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0 regex/128l ha:cschem-sheet-v[0-9]+[\ \t\r\n]*[{] sch-rnd/cschem schematic sheet (lihata)
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# tEDAx (modular format)
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0 regex/1l tEDAx[\ \t\r\n]v tEDAx (Trivial EDA eXchange)
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>0 regex begin\ symbol\ v with schematic symbol
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>0 regex begin\ board\ v with Printed Circuit Board
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>0 regex begin\ route_req\ v with PCB routing request
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>0 regex begin\ route_res\ v with PCB routing result
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>0 regex begin\ camv_layer\ v with camv-rnd exported layer
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>0 regex begin\ netlist\ v with netlist
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>0 regex begin\ backann\ v with Ringdove EDA back annotation
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>0 regex begin\ footprint\ v with PCB footprint
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>0 regex begin\ drc\ v with PCB DRC script
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>0 regex begin\ drc_query_rule\ v with pcb-rnd drc_query rules
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>0 regex begin\ drc_query_def\ v with pcb-rnd drc_query value/config definitions
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>0 regex begin\ etest\ v with PCB electric test
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