vasilito
cee25393d8
- Fix P15-8-init-cycle-detection.patch: replace visiting+error with seen+silent-skip to eliminate 11 false-positive 'dependency cycle detected' errors on shared deps - Fix P0-daemon-fix-init-notify-unwrap.patch: remove eprintln! for missing INIT_NOTIFY (expected for oneshot_async services, ~7 daemons affected) - Fix driver-manager hotplug loop: add PERMANENTLY_SKIPPED static set shared between hotplug handler and DriverConfig::probe() to stop infinite re-probing of Fatal/NotSupported/deferred-exhausted device+driver pairs (e.g. ided) - Fix driver-manager log_timeline: suppress repeated EPIPE/ENOENT errors with AtomicI32 dedup and AtomicBool one-shot guards for boot timeline JSON - Add driver-manager SIGTERM handler, ACPI bus registration, --status mode, driver reap loop, graceful shutdown, and reduced deferred retries (30→3)
273 lines
10 KiB
Diff
273 lines
10 KiB
Diff
--- a/src/acpi/madt/arch/x86.rs
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+++ b/src/acpi/madt/arch/x86.rs
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@@ -3,6 +3,8 @@
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sync::atomic::{AtomicU8, Ordering},
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};
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+use x86::time::rdtsc;
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+
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use crate::{
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arch::{
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device::local_apic::the_local_apic,
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@@ -18,6 +20,7 @@
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use super::{Madt, MadtEntry};
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+use alloc::collections::BTreeSet;
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use alloc::vec::Vec;
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/// Maximum number of APIC→CPU mappings we track for NUMA topology.
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@@ -45,6 +48,67 @@
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const TRAMPOLINE: usize = 0x8000;
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static TRAMPOLINE_DATA: &[u8] = include_bytes!(concat!(env!("OUT_DIR"), "/trampoline"));
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+/// Estimate TSC frequency in MHz from CPUID.
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+///
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+/// Tries CPUID leaf 0x16 (Processor Frequency Information) first,
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+/// then CPUID leaf 0x15 (TSC/Core Crystal Clock Ratio).
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+/// Returns None if frequency cannot be determined.
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+fn tsc_freq_mhz_cpuid() -> Option<u64> {
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+ let max_leaf = unsafe { core::arch::x86_64::__cpuid(0).eax as u32 };
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+
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+ // CPUID leaf 0x16: EAX = Core Base Frequency in MHz (Intel)
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+ if max_leaf >= 0x16 {
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+ let mhz = unsafe { core::arch::x86_64::__cpuid(0x16) }.eax as u64;
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+ if mhz > 0 {
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+ return Some(mhz);
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+ }
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+ }
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+
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+ // CPUID leaf 0x15: EAX = denominator, EBX = numerator, ECX = crystal Hz
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+ if max_leaf >= 0x15 {
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+ let res = unsafe { core::arch::x86_64::__cpuid(0x15) };
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+ let denom = res.eax as u64;
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+ let numer = res.ebx as u64;
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+ let crystal_hz = res.ecx as u64;
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+ if denom > 0 && numer > 0 && crystal_hz > 0 {
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+ // TSC freq = crystal_hz * numer / denom
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+ let tsc_hz = crystal_hz * numer / denom;
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+ return Some(tsc_hz / 1_000_000); // Hz → MHz
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+ }
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+ }
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+
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+ None
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+}
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+
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+/// Early-boot microsecond delay using the Time Stamp Counter.
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+///
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+/// Uses CPUID-based TSC frequency estimation when available.
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+/// Falls back to a conservative spin loop calibrated for the
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+/// minimum expected CPU speed (1 GHz).
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+///
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+/// # Safety
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+/// Must only be called after the BSP TSC is running (always true
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+/// after CPU reset on x86).
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+fn early_udelay(us: u64) {
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+ if let Some(mhz) = tsc_freq_mhz_cpuid() {
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+ // TSC-based delay: precise on invariant TSC (all modern x86).
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+ // MHz = cycles per µs.
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+ let target = unsafe { rdtsc() } + us * mhz;
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+ while unsafe { rdtsc() } < target {
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+ hint::spin_loop();
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+ }
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+ } else {
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+ // Fallback: conservative spin loop.
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+ // spin_loop() (PAUSE) is ~40 cycles on modern Intel, ~1 on AMD.
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+ // At 1 GHz minimum: 1000 cycles/µs ÷ 40 cycles/iter = 25 iters/µs.
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+ // Use 50 iters/µs for safety margin on slower/variable CPUs.
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+ let iters = us.saturating_mul(50);
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+ for _ in 0..iters {
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+ hint::spin_loop();
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+ }
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+ }
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+}
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+
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fn current_x2apic_processor_uid(madt: &Madt, apic_id: u32) -> Option<u32> {
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madt.iter().find_map(|entry| match entry {
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MadtEntry::LocalX2Apic(x2apic) if x2apic.x2apic_id == apic_id => Some(x2apic.processor_uid),
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@@ -133,6 +197,31 @@
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crate::profiling::allocate(preliminary_cpu_count as u32);
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}
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+ // Firmware bug detection: check for duplicate APIC IDs in MADT.
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+ // Some firmware (especially on early BIOS/UEFI) may list the same
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+ // processor multiple times. Keep first occurrence, warn on duplicates.
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+ let mut seen_apic_ids: BTreeSet<u32> = BTreeSet::new();
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+ {
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+ let _ = seen_apic_ids.insert(me.get()); // BSP
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+ for entry in madt.iter() {
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+ match entry {
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+ MadtEntry::LocalApic(local) if local.flags & 1 == 1 => {
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+ let id = u32::from(local.id);
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+ if !seen_apic_ids.insert(id) {
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+ warn!("MADT: duplicate APIC ID {} in LocalApic entry, firmware bug", id);
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+ }
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+ }
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+ MadtEntry::LocalX2Apic(local) if local.flags & 1 == 1 => {
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+ let id = local.x2apic_id;
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+ if !seen_apic_ids.insert(id) {
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+ warn!("MADT: duplicate x2APIC ID {} in LocalX2Apic entry, firmware bug", id);
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+ }
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+ }
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+ _ => {}
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+ }
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+ }
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+ }
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+
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for madt_entry in madt.iter() {
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debug!(" {:x?}", madt_entry);
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if let MadtEntry::LocalApic(ap_local_apic) = madt_entry {
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@@ -192,9 +281,14 @@
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};
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AP_READY.store(false, Ordering::SeqCst);
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- // Send INIT IPI
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+ // Clear APIC Error Status Register before starting AP.
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+ // Intel SDM §8.4.4: ESR should be cleared before sending SIPI.
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+ unsafe { local_apic.esr(); }
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+
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+ // Send INIT IPI (Assert)
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{
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- let mut icr = 0x4500;
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+ // ICR: Delivery Mode=INIT(101), Level=Assert, Trigger=Edge
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+ let mut icr = 0x4500u64;
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if local_apic.x2 {
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icr |= u64::from(ap_local_apic.id) << 32;
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} else {
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@@ -203,20 +297,53 @@
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local_apic.set_icr(icr);
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}
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- // Send START IPI
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+ // Intel SDM Vol 3A §8.4.4: wait 10ms after INIT deassert
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+ // before sending first SIPI. Modern CPUs may need less,
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+ // but 10ms is the safe specification-compliant value.
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+ early_udelay(10_000);
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+
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+ // Send START IPI #1
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{
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let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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- let mut icr = 0x4600 | ap_segment as u64;
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-
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+ // ICR: Delivery Mode=StartUp(110), Vector=ap_segment
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+ // Note: bit 14 (Level) must be 0 for SIPI per Intel SDM.
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+ let mut icr = 0x0600 | ap_segment as u64;
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if local_apic.x2 {
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icr |= u64::from(ap_local_apic.id) << 32;
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} else {
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icr |= u64::from(ap_local_apic.id) << 56;
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}
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+ local_apic.set_icr(icr);
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+ }
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+
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+ // Intel SDM: wait 200µs between SIPIs
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+ early_udelay(200);
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+ // Send START IPI #2 (recommended for compatibility)
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+ {
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+ let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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+ let mut icr = 0x0600 | ap_segment as u64;
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+ if local_apic.x2 {
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+ icr |= u64::from(ap_local_apic.id) << 32;
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+ } else {
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+ icr |= u64::from(ap_local_apic.id) << 56;
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+ }
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local_apic.set_icr(icr);
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}
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+ // Wait briefly for SIPI to be accepted
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+ early_udelay(200);
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+
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+ // Check ESR for delivery errors after SIPI sequence.
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+ // Bit 5 = Send Accept Error, Bit 6 = Send Illegal Vector.
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+ let esr_val = unsafe { local_apic.esr() };
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+ if esr_val != 0 {
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+ println!(
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+ "KERNEL AP: CPU {} SIPI delivery error (ESR={:#x}), continuing",
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+ ap_local_apic.id, esr_val
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+ );
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+ }
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+
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// Wait for trampoline ready with timeout
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let mut trampoline_ready = false;
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for _ in 0..AP_SPIN_LIMIT {
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@@ -311,34 +438,50 @@
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}
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AP_READY.store(false, Ordering::SeqCst);
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+ // Clear APIC Error Status Register before starting AP.
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+ unsafe { local_apic.esr(); }
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+
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+ // Send INIT IPI (Assert)
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{
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let mut icr = 0x4500u64;
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icr |= u64::from(apic_id) << 32;
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local_apic.set_icr(icr);
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}
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- for _ in 0..100_000 {
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- hint::spin_loop();
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- }
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+ // Intel SDM Vol 3A §8.4.4: wait 10ms after INIT
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+ early_udelay(10_000);
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+ // Send START IPI #1
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{
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let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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- let mut icr = 0x4600u64 | ap_segment as u64;
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+ let mut icr = 0x0600u64 | ap_segment as u64;
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icr |= u64::from(apic_id) << 32;
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local_apic.set_icr(icr);
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}
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- for _ in 0..2_000_000 {
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- hint::spin_loop();
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- }
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+ // Intel SDM: wait 200µs between SIPIs
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+ early_udelay(200);
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+ // Send START IPI #2 (recommended for compatibility)
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{
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let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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- let mut icr = 0x4600u64 | ap_segment as u64;
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+ let mut icr = 0x0600u64 | ap_segment as u64;
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icr |= u64::from(apic_id) << 32;
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local_apic.set_icr(icr);
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}
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+ // Wait briefly for SIPI acceptance
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+ early_udelay(200);
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+
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+ // Check ESR for delivery errors.
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+ let esr_val = unsafe { local_apic.esr() };
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+ if esr_val != 0 {
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+ println!(
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+ "KERNEL AP: CPU {} SIPI delivery error (ESR={:#x}), continuing",
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+ apic_id, esr_val
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+ );
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+ }
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+
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let mut trampoline_ready = false;
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for _ in 0..AP_SPIN_LIMIT {
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if unsafe { (*ap_ready.cast::<AtomicU8>()).load(Ordering::SeqCst) } != 0 {
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@@ -407,6 +550,19 @@
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crate::percpu::PercpuBlock::current().numa_node.set(node);
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}
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+ // Log final CPU count vs maximum
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+ let cpu_count = crate::CPU_COUNT.load(Ordering::SeqCst);
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+ info!(
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+ "SMP: {} CPUs online (max {})",
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+ cpu_count, crate::cpu_set::MAX_CPU_COUNT
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+ );
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+ if cpu_count > crate::cpu_set::MAX_CPU_COUNT * 80 / 100 {
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+ warn!(
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+ "SMP: CPU count approaching MAX_CPU_COUNT limit ({}/{})",
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+ cpu_count, crate::cpu_set::MAX_CPU_COUNT
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+ );
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+ }
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+
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// Unmap trampoline
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if let Some((_frame, _, flush)) = unsafe {
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KernelMapper::lock_rw()
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