Add display_dpll.rs — pixel clock PLL management.
Gen9 (SKL/KBL/CFL): enable LCPLL1/LCPLL2 at 0x46010/0x46014
and WRPLL1 at 0x46040 with WRPLL_REF_BCLK reference clock.
Poll PLL_LOCK bit for confirmation.
Xe2 (ARL/BMG): enable DPLL_CTRL1/DPLL_CTRL2 at 0x6C058/0x6C05C
with PLL_POWER_ENABLE. get_pll_for_clock() returns pdiv=1 or 2
based on pixel clock threshold (300 MHz).
Wire into IntelDriver constructor between CDCLK and display init.
Linux reference: intel_dpll_mgr.c (skl_wrpll, icl_dpll)
vasilito
2f18b35122