vasilito
cefc9b8936
AMD display driver: expanded DCN pipeline setup with plane/controller/stream mapping. Intel driver: cleaned up module structure. New interrupt module for MSI-X vector management across GPU drivers. PCID config endpoint patch and Intel GPU TOML for automatic driver spawning. Expanded redox_stubs with additional kernel API shims. Ultraworked with [Sisyphus](https://github.com/code-yeongyu/oh-my-openagent) Co-authored-by: Sisyphus <clio-agent@sisyphuslabs.ai>
114 lines
4.3 KiB
Diff
114 lines
4.3 KiB
Diff
diff --git a/drivers/pcid/src/scheme.rs b/drivers/pcid/src/scheme.rs
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index ce55b33f..c06bdec4 100644
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--- a/drivers/pcid/src/scheme.rs
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+++ b/drivers/pcid/src/scheme.rs
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@@ -21,6 +21,7 @@ enum Handle {
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TopLevel { entries: Vec<String> },
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Access,
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Device,
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+ Config { addr: PciAddress },
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Channel { addr: PciAddress, st: ChannelState },
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SchemeRoot,
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}
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@@ -30,14 +31,20 @@ struct HandleWrapper {
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}
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impl Handle {
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fn is_file(&self) -> bool {
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- matches!(self, Self::Access | Self::Channel { .. })
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+ matches!(
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+ self,
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+ Self::Access | Self::Config { .. } | Self::Channel { .. }
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+ )
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}
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fn is_dir(&self) -> bool {
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!self.is_file()
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}
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// TODO: capability rather than root
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fn requires_root(&self) -> bool {
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- matches!(self, Self::Access | Self::Channel { .. })
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+ matches!(
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+ self,
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+ Self::Access | Self::Config { .. } | Self::Channel { .. }
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+ )
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}
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fn is_scheme_root(&self) -> bool {
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matches!(self, Self::SchemeRoot)
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@@ -153,6 +160,7 @@ impl SchemeSync for PciScheme {
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let (len, mode) = match handle.inner {
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Handle::TopLevel { ref entries } => (entries.len(), MODE_DIR | 0o755),
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Handle::Device => (DEVICE_CONTENTS.len(), MODE_DIR | 0o755),
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+ Handle::Config { .. } => (256, MODE_CHR | 0o600),
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Handle::Access | Handle::Channel { .. } => (0, MODE_CHR | 0o600),
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Handle::SchemeRoot => return Err(Error::new(EBADF)),
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};
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@@ -177,6 +185,18 @@ impl SchemeSync for PciScheme {
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match handle.inner {
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Handle::TopLevel { .. } => Err(Error::new(EISDIR)),
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Handle::Device => Err(Error::new(EISDIR)),
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+ Handle::Config { addr } => {
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+ let offset = _offset as u16;
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+ let dword_offset = offset & !0x3;
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+ let byte_offset = (offset & 0x3) as usize;
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+ let bytes_to_read = buf.len().min(4 - byte_offset);
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+
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+ let dword = unsafe { self.pcie.read(addr, dword_offset) };
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+ let bytes = dword.to_le_bytes();
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+ buf[..bytes_to_read]
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+ .copy_from_slice(&bytes[byte_offset..byte_offset + bytes_to_read]);
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+ Ok(bytes_to_read)
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+ }
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Handle::Channel {
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addr: _,
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ref mut st,
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@@ -214,7 +234,9 @@ impl SchemeSync for PciScheme {
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return Ok(buf);
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}
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Handle::Device => DEVICE_CONTENTS,
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- Handle::Access | Handle::Channel { .. } => return Err(Error::new(ENOTDIR)),
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+ Handle::Access | Handle::Config { .. } | Handle::Channel { .. } => {
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+ return Err(Error::new(ENOTDIR));
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+ }
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Handle::SchemeRoot => return Err(Error::new(EBADF)),
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};
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@@ -244,6 +266,20 @@ impl SchemeSync for PciScheme {
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}
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match handle.inner {
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+ Handle::Config { addr } => {
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+ let offset = _offset as u16;
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+ let dword_offset = offset & !0x3;
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+ let byte_offset = (offset & 0x3) as usize;
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+ let bytes_to_write = buf.len().min(4 - byte_offset);
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+
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+ let mut dword = unsafe { self.pcie.read(addr, dword_offset) };
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+ let mut bytes = dword.to_le_bytes();
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+ bytes[byte_offset..byte_offset + bytes_to_write]
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+ .copy_from_slice(&buf[..bytes_to_write]);
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+ dword = u32::from_le_bytes(bytes);
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+ unsafe { self.pcie.write(addr, dword_offset, dword) };
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+ Ok(buf.len())
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+ }
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Handle::Channel { addr, ref mut st } => {
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Self::write_channel(&self.pcie, &mut self.tree, addr, st, buf)
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}
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@@ -339,6 +375,10 @@ impl PciScheme {
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func.enabled = false;
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}
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}
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+ Some(HandleWrapper {
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+ inner: Handle::Config { .. },
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+ ..
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+ }) => {}
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_ => {}
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}
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}
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@@ -365,6 +405,7 @@ impl PciScheme {
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let path = &after[1..];
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match path {
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+ "config" => Handle::Config { addr },
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"channel" => {
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if func.enabled {
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return Err(Error::new(ENOLCK));
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