vasilito
1e71b37bdb
Finalize all non-artifact changes accumulated from other sessions: - config updates, recipe changes, source edits, patches - pkgar/cache artifacts intentionally excluded (build outputs) This is the maximum achievable scope for this session. Hardware-accelerated KDE blocked by: QML gate, KWin/Plasma builds, hardware GPU validation — all require build system + physical GPU.
347 lines
11 KiB
Rust
347 lines
11 KiB
Rust
#![allow(dead_code)]
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use core::mem::size_of;
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// EHCI (USB 2.0) MMIO Register Layout
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// References: Intel EHCI 1.0 Specification (March 2002), sections 2.1-2.2
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// USB 2.0 Specification, sections 5.2-5.3
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pub const CAPLENGTH: usize = 0x00;
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pub const HCSPARAMS: usize = 0x04;
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pub const HCCPARAMS: usize = 0x08;
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pub const HCSP_PORT_ROUTE: usize = 0x0C;
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pub const HCCPARAMS_64BIT: u32 = 1 << 0;
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pub fn op_base(caplength: u8) -> usize {
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caplength as usize
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}
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pub const USBCMD: usize = 0x00;
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pub const USBSTS: usize = 0x04;
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pub const USBINTR: usize = 0x08;
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pub const FRINDEX: usize = 0x0C;
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pub const CTRLDSSEGMENT: usize = 0x10;
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pub const PERIODICLISTBASE: usize = 0x14;
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pub const ASYNCLISTADDR: usize = 0x18;
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pub const CONFIGFLAG: usize = 0x40;
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pub const PORTSC_BASE: usize = 0x44;
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pub const CMD_RUN_STOP: u32 = 1 << 0;
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pub const CMD_HCRESET: u32 = 1 << 1;
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pub const CMD_FRAME_LIST_SIZE_MASK: u32 = 0x3 << 2;
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pub const CMD_FRAME_LIST_SIZE_1024: u32 = 0x0 << 2;
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pub const CMD_FRAME_LIST_SIZE_512: u32 = 0x1 << 2;
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pub const CMD_FRAME_LIST_SIZE_256: u32 = 0x2 << 2;
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pub const CMD_PERIODIC_SCHEDULE_ENABLE: u32 = 1 << 4;
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pub const CMD_ASYNC_SCHEDULE_ENABLE: u32 = 1 << 5;
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pub const CMD_INTERRUPT_ON_ASYNC_ADVANCE: u32 = 1 << 6;
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pub const CMD_LIGHT_HOST_CONTROLLER_RESET: u32 = 1 << 7;
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pub const CMD_ASYNC_SCHEDULE_PARK_MODE_COUNT: u32 = 0x3 << 8;
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pub const CMD_ASYNC_SCHEDULE_PARK_MODE_ENABLE: u32 = 1 << 11;
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pub const CMD_INTERRUPT_THRESHOLD_CONTROL: u32 = 0xFF << 16;
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pub const STS_USB_INTERRUPT: u32 = 1 << 0;
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pub const STS_USB_ERROR_INTERRUPT: u32 = 1 << 1;
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pub const STS_PORT_CHANGE_DETECT: u32 = 1 << 2;
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pub const STS_FRAME_LIST_ROLLOVER: u32 = 1 << 3;
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pub const STS_HOST_SYSTEM_ERROR: u32 = 1 << 4;
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pub const STS_INTERRUPT_ON_ASYNC_ADVANCE: u32 = 1 << 5;
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pub const STS_HC_HALTED: u32 = 1 << 12;
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pub const STS_RECLAMATION: u32 = 1 << 13;
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pub const STS_PERIODIC_SCHEDULE_STATUS: u32 = 1 << 14;
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pub const STS_ASYNC_SCHEDULE_STATUS: u32 = 1 << 15;
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pub const INTR_USB_INTERRUPT_ENABLE: u32 = 1 << 0;
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pub const INTR_USB_ERROR_INTERRUPT_ENABLE: u32 = 1 << 1;
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pub const INTR_PORT_CHANGE_ENABLE: u32 = 1 << 2;
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pub const INTR_FRAME_LIST_ROLLOVER_ENABLE: u32 = 1 << 3;
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pub const INTR_HOST_SYSTEM_ERROR_ENABLE: u32 = 1 << 4;
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pub const INTR_ASYNC_ADVANCE_ENABLE: u32 = 1 << 5;
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pub const CF_FLAG: u32 = 1 << 0;
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pub const PORT_CONNECT: u32 = 1 << 0;
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pub const PORT_CONNECT_CHANGE: u32 = 1 << 1;
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pub const PORT_ENABLE: u32 = 1 << 2;
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pub const PORT_ENABLE_CHANGE: u32 = 1 << 3;
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pub const PORT_OVER_CURRENT_ACTIVE: u32 = 1 << 4;
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pub const PORT_OVER_CURRENT_CHANGE: u32 = 1 << 5;
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pub const PORT_FORCE_PORT_RESUME: u32 = 1 << 6;
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pub const PORT_SUSPEND: u32 = 1 << 7;
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pub const PORT_RESET: u32 = 1 << 8;
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pub const PORT_LINE_STATUS: u32 = 0x3 << 10;
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pub const PORT_LINE_STATUS_K: u32 = 0x1 << 10;
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pub const PORT_LINE_STATUS_J: u32 = 0x2 << 10;
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pub const PORT_POWER: u32 = 1 << 12;
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pub const PORT_OWNER: u32 = 1 << 13;
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pub const PORT_INDICATOR: u32 = 0x3 << 14;
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pub const PORT_TEST_CONTROL: u32 = 0xF << 16;
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pub const PORT_WAKE_CONNECT: u32 = 1 << 20;
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pub const PORT_WAKE_DISCONNECT: u32 = 1 << 21;
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pub const PORT_WAKE_OVER_CURRENT: u32 = 1 << 22;
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pub const PORTSC_CHANGE_BITS: u32 =
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PORT_CONNECT_CHANGE | PORT_ENABLE_CHANGE | PORT_OVER_CURRENT_CHANGE;
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pub const PORTSC_WRITE_MASK: u32 = PORT_ENABLE
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| PORT_FORCE_PORT_RESUME
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| PORT_SUSPEND
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| PORT_RESET
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| PORT_POWER
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| PORT_OWNER
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| PORT_INDICATOR
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| PORT_TEST_CONTROL
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| PORT_WAKE_CONNECT
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| PORT_WAKE_DISCONNECT
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| PORT_WAKE_OVER_CURRENT;
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pub fn portsc_offset(port: usize) -> usize {
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PORTSC_BASE + (port * 4)
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}
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#[derive(Debug)]
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pub struct HcCapParams {
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pub n_ports: u8,
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pub port_routing_rules: bool,
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pub n_cc: u8,
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pub n_pcc: u8,
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pub port_route: u32,
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}
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impl HcCapParams {
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pub fn from_hcsparams(hcsparams: u32) -> Self {
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HcCapParams {
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n_ports: (hcsparams & 0xF) as u8,
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port_routing_rules: (hcsparams >> 4) & 1 != 0,
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n_cc: ((hcsparams >> 8) & 0xF) as u8,
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n_pcc: ((hcsparams >> 12) & 0xF) as u8,
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port_route: 0,
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}
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}
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}
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pub struct EhciRegisters {
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pub mmio_base: usize,
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pub mmio_size: usize,
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pub op_base: usize,
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pub n_ports: u8,
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pub frame_list_size: u32,
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pub has_64bit: bool,
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}
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impl EhciRegisters {
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pub fn read32(&self, offset: usize) -> u32 {
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let addr = self.mmio_base + offset;
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unsafe { (addr as *const u32).read_volatile() }
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}
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pub fn write32(&self, offset: usize, value: u32) {
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let addr = self.mmio_base + offset;
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unsafe { (addr as *mut u32).write_volatile(value) }
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}
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pub fn read_op32(&self, offset: usize) -> u32 {
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self.read32(self.op_base + offset)
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}
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pub fn write_op32(&self, offset: usize, value: u32) {
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self.write32(self.op_base + offset, value)
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(C, align(64))]
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pub struct QueueHead {
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pub horiz_link: u32,
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pub caps: [u32; 2],
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pub current_qtd: u32,
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pub overlay: [u32; 8],
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}
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pub const QH_TERMINATE: u32 = 1;
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pub const QH_HEAD_MASK: u32 = !0x1F;
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pub const QH_LINK_TYPE_QH: u32 = 0x2;
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pub const QH_ENDPOINT_DTC: u32 = 1 << 14;
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pub const QH_ENDPOINT_HEAD: u32 = 1 << 15;
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pub const QH_ENDPOINT_SPEED_HIGH: u32 = 0x2 << 12;
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pub const QH_NAK_RELOAD_4: u32 = 0x4 << 28;
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pub const QH_CAP_MULT_ONE: u32 = 0x1 << 30;
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impl QueueHead {
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pub fn new() -> Self {
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QueueHead {
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horiz_link: QH_TERMINATE,
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caps: [0; 2],
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current_qtd: 0,
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overlay: [TD_TERMINATE, TD_TERMINATE, 0, 0, 0, 0, 0, 0],
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}
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(C, align(32))]
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pub struct TransferDescriptor {
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pub next_qtd: u32,
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pub alt_qtd: u32,
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pub token: u32,
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pub buffers: [u32; 5],
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}
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pub const TD_TERMINATE: u32 = 1;
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pub const TD_ACTIVE: u32 = 1 << 7;
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pub const TD_HALTED: u32 = 1 << 6;
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pub const TD_BUFERR: u32 = 1 << 5;
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pub const TD_BABBLE: u32 = 1 << 4;
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pub const TD_XACTERR: u32 = 1 << 3;
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pub const TD_MISSED: u32 = 1 << 2;
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pub const TD_C_PAGE_MASK: u32 = 0x7 << 12;
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pub const TD_IOC: u32 = 1 << 15;
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pub const TD_ERROR_COUNTER_3: u32 = 0x3 << 10;
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pub const TD_TOTAL_BYTES_SHIFT: u32 = 16;
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pub const TD_TOTAL_BYTES_MASK: u32 = 0x7FFF << TD_TOTAL_BYTES_SHIFT;
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pub const TD_PID_IN: u32 = 1 << 8;
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pub const TD_PID_OUT: u32 = 0 << 8;
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pub const TD_PID_SETUP: u32 = 2 << 8;
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pub const TD_PID_MASK: u32 = 3 << 8;
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pub fn qh_link_pointer(phys_addr: u64) -> u32 {
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((phys_addr as u32) & QH_HEAD_MASK) | QH_LINK_TYPE_QH
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}
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pub fn qh_endpoint_characteristics(
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device_address: u8,
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endpoint: u8,
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max_packet_size: u16,
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head_of_reclamation: bool,
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) -> u32 {
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let mut value = u32::from(device_address & 0x7F)
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| (u32::from(endpoint & 0x0F) << 8)
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| QH_ENDPOINT_SPEED_HIGH
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| QH_ENDPOINT_DTC
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| (u32::from(max_packet_size & 0x07FF) << 16)
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| QH_NAK_RELOAD_4;
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if head_of_reclamation {
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value |= QH_ENDPOINT_HEAD;
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}
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value
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}
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pub fn qh_endpoint_capabilities() -> u32 {
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QH_CAP_MULT_ONE
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}
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fn fill_qtd_buffers(td: &mut TransferDescriptor, phys_addr: u64) {
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let addr = phys_addr as u32;
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td.buffers[0] = addr;
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let page_base = addr & !0xFFF;
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for (index, slot) in td.buffers.iter_mut().enumerate().skip(1) {
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*slot = page_base.wrapping_add((index as u32) * 0x1000);
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}
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}
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pub fn build_setup_td(phys_addr: u64, _setup_data: &[u8; 8], toggle: bool) -> TransferDescriptor {
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let mut td = TransferDescriptor {
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next_qtd: TD_TERMINATE,
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alt_qtd: TD_TERMINATE,
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token: TD_ACTIVE | TD_PID_SETUP | TD_ERROR_COUNTER_3 | (8 << TD_TOTAL_BYTES_SHIFT),
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buffers: [0; 5],
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};
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fill_qtd_buffers(&mut td, phys_addr);
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if toggle {
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td.token |= 1 << 31;
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}
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td
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}
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pub fn build_data_td(phys_addr: u64, len: usize, dir_in: bool, toggle: bool) -> TransferDescriptor {
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let pid = if dir_in { TD_PID_IN } else { TD_PID_OUT };
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let mut td = TransferDescriptor {
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next_qtd: TD_TERMINATE,
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alt_qtd: TD_TERMINATE,
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token: TD_ACTIVE
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| pid
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| TD_ERROR_COUNTER_3
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| (((len as u32) & 0x7FFF) << TD_TOTAL_BYTES_SHIFT),
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buffers: [0; 5],
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};
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fill_qtd_buffers(&mut td, phys_addr);
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if toggle {
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td.token |= 1 << 31;
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}
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td
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}
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pub fn build_status_td(dir_in: bool) -> TransferDescriptor {
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let pid = if dir_in { TD_PID_OUT } else { TD_PID_IN };
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TransferDescriptor {
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next_qtd: TD_TERMINATE,
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alt_qtd: TD_TERMINATE,
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token: TD_ACTIVE | pid | TD_ERROR_COUNTER_3 | TD_IOC | (1 << 31),
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buffers: [0; 5],
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}
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}
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fn td_phys(td_pool_phys: u64, index: usize) -> Option<u32> {
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let offset = index.checked_mul(size_of::<TransferDescriptor>())?;
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let phys = td_pool_phys.checked_add(offset as u64)?;
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Some((phys as u32) & !0x1F)
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}
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pub fn build_control_transfer(
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setup_phys: u64,
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setup_data: &[u8; 8],
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data_phys: u64,
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data_len: usize,
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dir_in: bool,
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td_pool: &mut [TransferDescriptor],
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td_pool_phys: u64,
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) -> Option<u32> {
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if td_pool.len() < 2 {
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return None;
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}
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let td_count = if data_len > 0 { 3 } else { 2 };
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if td_pool.len() < td_count {
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return None;
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}
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let setup_td_phys = td_phys(td_pool_phys, 0)?;
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let status_td_phys = td_phys(td_pool_phys, td_count - 1)?;
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td_pool[0] = build_setup_td(setup_phys, setup_data, false);
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if data_len > 0 {
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let data_td_phys = td_phys(td_pool_phys, 1)?;
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td_pool[0].next_qtd = data_td_phys;
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td_pool[1] = build_data_td(data_phys, data_len, dir_in, true);
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td_pool[1].next_qtd = status_td_phys;
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td_pool[1].alt_qtd = status_td_phys;
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td_pool[2] = build_status_td(dir_in);
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} else {
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td_pool[0].next_qtd = status_td_phys;
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td_pool[1] = build_status_td(dir_in);
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}
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Some(setup_td_phys)
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}
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pub fn build_bulk_transfer(data_phys: u64, data_len: usize, dir_in: bool, tds: &mut [TransferDescriptor], td_phys: u64) -> u32 {
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let pid = if dir_in { TD_PID_IN } else { TD_PID_OUT };
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tds[0] = TransferDescriptor { next_qtd: 0, alt_qtd: 0, token: TD_ACTIVE | pid | ((data_len as u32 & 0x7FFF) << 16), buffers: [0; 5] };
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tds[0].buffers[0] = data_phys as u32;
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let next = (td_phys as u32 + size_of::<TransferDescriptor>() as u32) & !0x1F;
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tds[0].next_qtd = next;
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tds[1] = TransferDescriptor { next_qtd: TD_TERMINATE, alt_qtd: TD_TERMINATE, token: TD_ACTIVE | (1 << 15) | 0x8000_0000 /* IOC */, buffers: [0; 5] };
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td_phys as u32
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}
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pub fn build_intr_td(data_phys: u64, data_len: usize, _td_phys: u64) -> TransferDescriptor {
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let mut td = TransferDescriptor { next_qtd: TD_TERMINATE, alt_qtd: TD_TERMINATE, token: TD_ACTIVE | TD_PID_IN | ((data_len as u32 & 0x7FFF) << 16), buffers: [0; 5] };
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td.buffers[0] = data_phys as u32;
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td
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}
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