Andrey Turkin
320 lines
9.2 KiB
Rust
320 lines
9.2 KiB
Rust
use crate::{memory::ArchIntCtx, syscall::IntRegisters};
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use core::mem::size_of;
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#[derive(Default)]
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#[repr(C)]
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pub struct Registers {
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pub x1: usize, // ra
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pub x2: usize, // sp
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pub x3: usize, // gp
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pub x4: usize, // tp
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pub x5: usize, // t0
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pub x6: usize, // t1
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pub x7: usize, // t2
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pub x8: usize, // s0/fp
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pub x9: usize, // s1
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pub x10: usize, // a0...
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pub x11: usize,
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pub x12: usize,
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pub x13: usize,
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pub x14: usize,
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pub x15: usize,
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pub x16: usize,
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pub x17: usize, // a7
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pub x18: usize, // s2...
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pub x19: usize,
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pub x20: usize,
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pub x21: usize,
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pub x22: usize,
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pub x23: usize,
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pub x24: usize,
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pub x25: usize,
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pub x26: usize,
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pub x27: usize, // s11
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pub x28: usize, // t3...
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pub x29: usize,
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pub x30: usize,
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pub x31: usize, // t6
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}
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impl Registers {
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pub fn dump(&self) {
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println!("X1: {:>016X}", { self.x1 });
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println!("X2: {:>016X}", { self.x2 });
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println!("X3: {:>016X}", { self.x3 });
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println!("X4: {:>016X}", { self.x4 });
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println!("X5: {:>016X}", { self.x5 });
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println!("X6: {:>016X}", { self.x6 });
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println!("X7: {:>016X}", { self.x7 });
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println!("X8: {:>016X}", { self.x8 });
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println!("X9: {:>016X}", { self.x9 });
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println!("X10: {:>016X}", { self.x10 });
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println!("X11: {:>016X}", { self.x11 });
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println!("X12: {:>016X}", { self.x12 });
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println!("X13: {:>016X}", { self.x13 });
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println!("X14: {:>016X}", { self.x14 });
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println!("X15: {:>016X}", { self.x15 });
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println!("X16: {:>016X}", { self.x16 });
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println!("X17: {:>016X}", { self.x17 });
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println!("X18: {:>016X}", { self.x18 });
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println!("X19: {:>016X}", { self.x19 });
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println!("X20: {:>016X}", { self.x20 });
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println!("X21: {:>016X}", { self.x21 });
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println!("X22: {:>016X}", { self.x22 });
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println!("X23: {:>016X}", { self.x23 });
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println!("X24: {:>016X}", { self.x24 });
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println!("X25: {:>016X}", { self.x25 });
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println!("X26: {:>016X}", { self.x26 });
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println!("X27: {:>016X}", { self.x27 });
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println!("X28: {:>016X}", { self.x28 });
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println!("X29: {:>016X}", { self.x29 });
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println!("X30: {:>016X}", { self.x30 });
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println!("X31: {:>016X}", { self.x31 });
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}
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}
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#[derive(Default)]
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#[repr(C)]
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pub struct IretRegisters {
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pub sepc: usize,
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}
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impl IretRegisters {
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pub fn dump(&self) {
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println!("SEPC: {:>016X}", { self.sepc });
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}
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}
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// NOTE: Layout of this structure must be synced with assembly code in exception.rs
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#[derive(Default)]
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#[repr(C)]
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pub struct InterruptStack {
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pub registers: Registers,
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pub iret: IretRegisters,
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}
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impl InterruptStack {
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pub fn init(&mut self) {
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const {
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assert!(32 * 8 == size_of::<InterruptStack>());
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}
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}
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pub fn set_stack_pointer(&mut self, sp: usize) {
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self.registers.x2 = sp;
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}
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pub fn stack_pointer(&self) -> usize {
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self.registers.x2
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}
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pub fn set_instr_pointer(&mut self, ip: usize) {
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self.iret.sepc = ip;
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}
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pub fn instr_pointer(&self) -> usize {
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self.iret.sepc
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}
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pub fn sig_archdep_reg(&self) -> usize {
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self.registers.x5
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}
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pub fn set_syscall_ret_reg(&mut self, ret: usize) {
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self.registers.x10 = ret;
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}
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pub fn dump(&self) {
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self.iret.dump();
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self.registers.dump();
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}
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/// Saves all registers to a struct used by the proc:
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/// scheme to read/write registers.
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pub fn save(&self, all: &mut IntRegisters) {
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all.pc = self.iret.sepc;
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all.x31 = self.registers.x31;
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all.x30 = self.registers.x30;
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all.x29 = self.registers.x29;
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all.x28 = self.registers.x28;
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all.x27 = self.registers.x27;
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all.x26 = self.registers.x26;
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all.x25 = self.registers.x25;
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all.x24 = self.registers.x24;
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all.x23 = self.registers.x23;
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all.x22 = self.registers.x22;
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all.x21 = self.registers.x21;
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all.x20 = self.registers.x20;
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all.x19 = self.registers.x19;
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all.x18 = self.registers.x18;
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all.x17 = self.registers.x17;
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all.x16 = self.registers.x16;
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all.x15 = self.registers.x15;
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all.x14 = self.registers.x14;
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all.x13 = self.registers.x13;
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all.x12 = self.registers.x12;
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all.x11 = self.registers.x11;
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all.x10 = self.registers.x10;
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all.x9 = self.registers.x9;
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all.x8 = self.registers.x8;
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all.x7 = self.registers.x7;
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all.x6 = self.registers.x6;
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all.x5 = self.registers.x5;
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all.x2 = self.registers.x2;
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all.x1 = self.registers.x1;
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}
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/// Loads all registers from a struct used by the proc:
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/// scheme to read/write registers.
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pub fn load(&mut self, all: &IntRegisters) {
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self.iret.sepc = all.pc;
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self.registers.x31 = all.x31;
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self.registers.x30 = all.x30;
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self.registers.x29 = all.x29;
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self.registers.x28 = all.x28;
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self.registers.x27 = all.x27;
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self.registers.x26 = all.x26;
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self.registers.x25 = all.x25;
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self.registers.x24 = all.x24;
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self.registers.x23 = all.x23;
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self.registers.x22 = all.x22;
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self.registers.x21 = all.x21;
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self.registers.x20 = all.x20;
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self.registers.x19 = all.x19;
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self.registers.x18 = all.x18;
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self.registers.x17 = all.x17;
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self.registers.x16 = all.x16;
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self.registers.x15 = all.x15;
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self.registers.x14 = all.x14;
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self.registers.x13 = all.x13;
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self.registers.x12 = all.x12;
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self.registers.x11 = all.x11;
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self.registers.x10 = all.x10;
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self.registers.x9 = all.x9;
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self.registers.x8 = all.x8;
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self.registers.x7 = all.x7;
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self.registers.x6 = all.x6;
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self.registers.x5 = all.x5;
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self.registers.x2 = all.x2;
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self.registers.x1 = all.x1;
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}
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//TODO
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pub fn is_singlestep(&self) -> bool {
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false
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}
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pub fn set_singlestep(&mut self, _singlestep: bool) {}
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}
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impl ArchIntCtx for InterruptStack {
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fn ip(&self) -> usize {
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self.iret.sepc
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}
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fn recover_and_efault(&mut self) {
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// Set the return value to nonzero to indicate usercopy failure (EFAULT), and emulate the
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// return instruction by setting the return pointer to the saved LR value.
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self.iret.sepc = self.registers.x1; // ra
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self.registers.x10 = 1; // a0
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}
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}
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/// Except for sp and tp
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#[macro_export]
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macro_rules! push_registers {
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() => {
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"
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addi sp, sp, -32 * 8
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sd x1, (0 * 8)(sp)
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// skip sp
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sd x3, (2 * 8)(sp)
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// skip tp
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sd x5, (4 * 8)(sp)
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sd x6, (5 * 8)(sp)
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sd x7, (6 * 8)(sp)
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sd x8, (7 * 8)(sp)
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sd x9, (8 * 8)(sp)
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sd x10, (9 * 8)(sp)
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sd x11, (10 * 8)(sp)
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sd x12, (11 * 8)(sp)
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sd x13, (12 * 8)(sp)
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sd x14, (13 * 8)(sp)
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sd x15, (14 * 8)(sp)
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sd x16, (15 * 8)(sp)
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sd x17, (16 * 8)(sp)
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sd x18, (17 * 8)(sp)
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sd x19, (18 * 8)(sp)
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sd x20, (19 * 8)(sp)
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sd x21, (20 * 8)(sp)
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sd x22, (21 * 8)(sp)
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sd x23, (22 * 8)(sp)
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sd x24, (23 * 8)(sp)
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sd x25, (24 * 8)(sp)
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sd x26, (25 * 8)(sp)
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sd x27, (26 * 8)(sp)
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sd x28, (27 * 8)(sp)
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sd x29, (28 * 8)(sp)
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sd x30, (29 * 8)(sp)
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sd x31, (30 * 8)(sp)
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csrr t0, sepc
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sd t0, (31 * 8)(sp)
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"
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}; // keep sepc value in t0 on exit
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}
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#[macro_export]
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macro_rules! pop_registers {
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() => {
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"
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ld t0, (31 * 8)(sp)
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csrw sepc, t0
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ld x1, (0 * 8)(sp)
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// skip sp, it'll be restored later
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ld x3, (2 * 8)(sp)
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ld x4, (3 * 8)(sp)
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ld x5, (4 * 8)(sp)
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ld x6, (5 * 8)(sp)
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ld x7, (6 * 8)(sp)
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ld x8, (7 * 8)(sp)
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ld x9, (8 * 8)(sp)
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ld x10, (9 * 8)(sp)
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ld x11, (10 * 8)(sp)
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ld x12, (11 * 8)(sp)
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ld x13, (12 * 8)(sp)
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ld x14, (13 * 8)(sp)
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ld x15, (14 * 8)(sp)
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ld x16, (15 * 8)(sp)
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ld x17, (16 * 8)(sp)
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ld x18, (17 * 8)(sp)
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ld x19, (18 * 8)(sp)
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ld x20, (19 * 8)(sp)
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ld x21, (20 * 8)(sp)
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ld x22, (21 * 8)(sp)
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ld x23, (22 * 8)(sp)
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ld x24, (23 * 8)(sp)
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ld x25, (24 * 8)(sp)
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ld x26, (25 * 8)(sp)
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ld x27, (26 * 8)(sp)
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ld x28, (27 * 8)(sp)
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ld x29, (28 * 8)(sp)
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ld x30, (29 * 8)(sp)
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ld x31, (30 * 8)(sp)
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ld sp, (1 * 8)(sp)
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"
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};
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}
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#[naked]
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pub unsafe extern "C" fn enter_usermode() -> ! {
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core::arch::asm!(
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concat!(
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"jalr s11\n",
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"li t0, 1 << 8\n", // force U mode on sret
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"csrc sstatus, t0\n",
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"li t0, 0x6000\n", // set FS to dirty (enable FPU in U mode)
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"csrs sstatus, t0\n",
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"addi t0, sp, 32 * 8\n", // save S mode stack to percpu
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"sd t0, 8(tp)\n",
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pop_registers!(),
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"sret\n",
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),
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options(noreturn)
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)
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}
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