Red Bear OS
ddb40deac5
xhcid:
- New module xhci/quirks.rs: 51-quirk XhciQuirks bitflags + per-vendor
lookup table. Ported from linux-7.1/drivers/usb/host/xhci.h:1587-1649
(51 quirk flags) + xhci-pci.c (per-vendor lookup).
- Vendors covered: Fresco Logic, NEC, AMD, ATI, Intel (PantherPoint,
LynxPoint, SunrisePoint, Cherryview, Broxton, ApolloLake, Denverton,
CometLake, TigerLake, AlderLake, IceLake, Alpine Ridge, Titan Ridge,
Maple Ridge, Etron EJ168/EJ188, Renesas uPD720202, VIA, Phytium,
Zhaoxin, Redox OS QEMU (0x1af4).
- Tests for Intel/AMD/Etron/Renesas/unknown-vendor coverage.
- Xhci struct gains a public quirks: XhciQuirks field.
- main.rs detects vendor/device/class from pcid, applies quirks.
pcid:
- SubdriverArguments gains device_id: Option<FullDeviceId> field.
- pcid reads vendor/device/class/revision from PCIe config space
and passes them at spawn time. Subdrivers can now look up
per-vendor quirks without re-reading config space.
Cross-reference: linux-7.1/drivers/usb/host/xhci.h:1587-1649 (51
quirk flags) + xhci-pci.c (per-vendor lookup table, 20+ entries).
Bitflags 2.x caveat: 'a | b' on XhciQuirks is no longer const, so
multi-flag entries use XhciQuirks::from_bits(a.bits() | b.bits()).unwrap()
in const context.
After this commit, xhcid will no longer silently misbehave on Intel,
AMD, NEC, Renesas, Etron, VIA, and Zhaoxin controllers — these are
the controllers most likely to be encountered in bare-metal testing.
326 lines
14 KiB
Rust
326 lines
14 KiB
Rust
use pci_types::capability::{MultipleMessageSupport, PciCapability};
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use pci_types::{ConfigRegionAccess, EndpointHeader};
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use pcid_interface::PciFunction;
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use crate::cfg_access::Pcie;
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use pcid_interface::FullDeviceId;
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/// Read the full PCI device ID (vendor, device, class, etc.) from
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/// the kernel's PCIe config space. Mirrors the data Linux's
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/// xhci-pci.c uses to look up per-vendor quirks.
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fn read_full_device_id(pcie: &Pcie, func: &PciFunction, addr: pci_types::PciAddress) -> Option<FullDeviceId> {
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// PCI config space offsets:
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// 0x00..0x01: vendor_id
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// 0x02..0x03: device_id
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// 0x08..0x0B: class (low 24 bits: class, subclass, interface)
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// 0x08..0x0B: revision (high 8 bits when read as u8 from offset 0x08)
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let id = unsafe { pcie.read(addr, 0) };
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let rev = unsafe { pcie.read(addr, 8) };
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let vendor_id = (id & 0xFFFF) as u16;
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let device_id = ((id >> 16) & 0xFFFF) as u16;
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let class = ((rev >> 24) & 0xFF) as u8;
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let subclass = ((rev >> 16) & 0xFF) as u8;
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let interface = rev as u8;
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Some(FullDeviceId {
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vendor_id,
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device_id,
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class,
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subclass,
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interface,
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// hci_version lives in bits 16-23 of the 32-bit word at offset 0
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revision: ((id >> 16) & 0xFF) as u8,
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})
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}
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pub struct DriverHandler<'a> {
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func: PciFunction,
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/// Full device ID (vendor/device/class) read from the kernel's
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/// PCIe config space at spawn time. Used by subdrivers (e.g. xhcid)
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/// to apply per-vendor quirks via the Linux 7.1 quirk table.
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device_id: Option<FullDeviceId>,
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endpoint_header: &'a mut EndpointHeader,
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capabilities: &'a mut [PciCapability],
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pcie: &'a Pcie,
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}
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impl<'a> DriverHandler<'a> {
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pub fn new(
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func: PciFunction,
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endpoint_header: &'a mut EndpointHeader,
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capabilities: &'a mut [PciCapability],
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pcie: &'a Pcie,
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) -> Self {
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// Read vendor, device, and revision from PCI config space
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// (offsets 0x00, 0x02, 0x08) and class/subclass/interface
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// (offset 0x08 upper bytes). This is what Linux's
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// xhci-pci.c uses to look up quirks.
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let device_id = read_full_device_id(pcie, &func, func.addr);
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DriverHandler {
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func,
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device_id,
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endpoint_header,
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capabilities,
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pcie,
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}
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}
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pub fn respond(
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&mut self,
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request: pcid_interface::PcidClientRequest,
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) -> pcid_interface::PcidClientResponse {
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use pcid_interface::*;
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#[forbid(non_exhaustive_omitted_patterns)]
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match request {
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PcidClientRequest::EnableDevice => {
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self.func.legacy_interrupt_line = crate::enable_function(
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&self.pcie,
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&mut self.endpoint_header,
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&mut self.capabilities,
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);
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PcidClientResponse::EnabledDevice
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}
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PcidClientRequest::RequestVendorCapabilities => PcidClientResponse::VendorCapabilities(
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self.capabilities
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.iter()
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.filter_map(|capability| match capability {
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PciCapability::Vendor(addr) => unsafe {
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Some(VendorSpecificCapability::parse(*addr, self.pcie))
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},
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_ => None,
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})
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.collect::<Vec<_>>(),
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),
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PcidClientRequest::RequestConfig => {
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PcidClientResponse::Config(SubdriverArguments {
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func: self.func,
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device_id: self.device_id,
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})
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}
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PcidClientRequest::RequestFeatures => PcidClientResponse::AllFeatures(
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self.capabilities
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.iter()
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.filter_map(|capability| match capability {
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PciCapability::Msi(_) => Some(PciFeature::Msi),
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PciCapability::MsiX(_) => Some(PciFeature::MsiX),
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_ => None,
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})
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.collect(),
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),
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PcidClientRequest::EnableFeature(feature) => {
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match feature {
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PciFeature::Msi => {
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if let Some(msix_capability) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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// If MSI-X is supported disable it before enabling MSI as they can't be
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// active at the same time.
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msix_capability.set_enabled(false, self.pcie);
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}
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let capability = match self.capabilities.iter_mut().find_map(|capability| {
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match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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}
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}) {
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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capability.set_enabled(true, self.pcie);
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PcidClientResponse::FeatureEnabled(feature)
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}
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PciFeature::MsiX => {
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if let Some(msi_capability) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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// If MSI is supported disable it before enabling MSI-X as they can't be
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// active at the same time.
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msi_capability.set_enabled(false, self.pcie);
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}
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let capability = match self.capabilities.iter_mut().find_map(|capability| {
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match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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}
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}) {
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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capability.set_enabled(true, self.pcie);
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PcidClientResponse::FeatureEnabled(feature)
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}
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}
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}
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PcidClientRequest::FeatureInfo(feature) => PcidClientResponse::FeatureInfo(
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feature,
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match feature {
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PciFeature::Msi => {
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if let Some(info) =
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self.capabilities
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.iter()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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PciFeatureInfo::Msi(msi::MsiInfo {
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log2_multiple_message_capable: info.multiple_message_capable()
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as u8,
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is_64bit: info.is_64bit(),
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has_per_vector_masking: info.has_per_vector_masking(),
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})
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} else {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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);
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}
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}
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PciFeature::MsiX => {
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if let Some(info) =
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self.capabilities
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.iter()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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PciFeatureInfo::MsiX(msi::MsixInfo {
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table_bar: info.table_bar(),
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table_offset: info.table_offset(),
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table_size: info.table_size(),
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pba_bar: info.pba_bar(),
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pba_offset: info.pba_offset(),
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})
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} else {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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);
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}
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}
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},
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),
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PcidClientRequest::SetFeatureInfo(info_to_set) => match info_to_set {
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SetFeatureInfo::Msi(info_to_set) => {
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if let Some(info) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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if let Some(mme) = info_to_set.multi_message_enable {
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if (info.multiple_message_capable() as u8) < mme {
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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info.set_multiple_message_enable(
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match mme {
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0 => MultipleMessageSupport::Int1,
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1 => MultipleMessageSupport::Int2,
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2 => MultipleMessageSupport::Int4,
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3 => MultipleMessageSupport::Int8,
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4 => MultipleMessageSupport::Int16,
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5 => MultipleMessageSupport::Int32,
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_ => {
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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)
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}
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},
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self.pcie,
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);
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}
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if let Some(message_addr_and_data) = info_to_set.message_address_and_data {
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let message_addr = message_addr_and_data.addr;
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if message_addr & 0b11 != 0 {
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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if message_addr_and_data.data
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& ((1 << info.multiple_message_enable(self.pcie) as u8) - 1)
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!= 0
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{
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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info.set_message_info(
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message_addr,
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message_addr_and_data
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.data
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.try_into()
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.expect("pcid: MSI message data too big"),
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self.pcie,
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);
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}
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if let Some(mask_bits) = info_to_set.mask_bits {
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info.set_message_mask(mask_bits, self.pcie);
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::Msi)
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} else {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(PciFeature::Msi),
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);
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}
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}
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SetFeatureInfo::MsiX { function_mask } => {
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if let Some(info) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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if let Some(mask) = function_mask {
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info.set_function_mask(mask, self.pcie);
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::MsiX)
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} else {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(PciFeature::MsiX),
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);
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}
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}
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_ => unreachable!(),
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},
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PcidClientRequest::ReadConfig(offset) => {
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let value = unsafe { self.pcie.read(self.func.addr, offset) };
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return PcidClientResponse::ReadConfig(value);
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}
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PcidClientRequest::WriteConfig(offset, value) => {
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unsafe {
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self.pcie.write(self.func.addr, offset, value);
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}
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return PcidClientResponse::WriteConfig;
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}
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_ => unreachable!(),
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}
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}
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}
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