vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
308 lines
12 KiB
C++
308 lines
12 KiB
C++
//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Common/CodeGenInstruction.h"
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#include "Common/CodeGenTarget.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TGTimer.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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#define DEBUG_TYPE "pseudo-lowering"
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namespace {
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class PseudoLoweringEmitter {
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struct OpData {
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enum MapKind { Operand, Imm, Reg } Kind;
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union {
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unsigned OpNo; // Operand number mapped to.
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uint64_t ImmVal; // Integer immedate value.
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const Record *RegRec; // Physical register.
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};
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};
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struct PseudoExpansion {
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CodeGenInstruction Source; // The source pseudo instruction definition.
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CodeGenInstruction Dest; // The destination instruction to lower to.
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IndexedMap<OpData> OperandMap;
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PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
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IndexedMap<OpData> &m)
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: Source(s), Dest(d), OperandMap(m) {}
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};
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const RecordKeeper &Records;
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// It's overkill to have an instance of the full CodeGenTarget object,
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// but it loads everything on demand, not in the constructor, so it's
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// lightweight in performance, so it works out OK.
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const CodeGenTarget Target;
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SmallVector<PseudoExpansion, 64> Expansions;
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void addOperandMapping(unsigned MIOpNo, unsigned NumOps, const Record *Rec,
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const DagInit *Dag, unsigned DagIdx,
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const Record *OpRec, IndexedMap<OpData> &OperandMap,
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const StringMap<unsigned> &SourceOperands,
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const CodeGenInstruction &SourceInsn);
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void evaluateExpansion(const Record *Pseudo);
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void emitLoweringEmitter(raw_ostream &o);
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public:
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PseudoLoweringEmitter(const RecordKeeper &R) : Records(R), Target(R) {}
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/// run - Output the pseudo-lowerings.
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void run(raw_ostream &o);
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};
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} // End anonymous namespace
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void PseudoLoweringEmitter::addOperandMapping(
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unsigned MIOpNo, unsigned NumOps, const Record *Rec, const DagInit *Dag,
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unsigned DagIdx, const Record *OpRec, IndexedMap<OpData> &OperandMap,
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const StringMap<unsigned> &SourceOperands,
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const CodeGenInstruction &SourceInsn) {
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const Init *DagArg = Dag->getArg(DagIdx);
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if (const DefInit *DI = dyn_cast<DefInit>(DagArg)) {
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// Physical register reference. Explicit check for the special case
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// "zero_reg" definition.
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if (DI->getDef()->isSubClassOf("Register") ||
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DI->getDef()->getName() == "zero_reg") {
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Reg;
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Entry.RegRec = DI->getDef();
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return;
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}
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if (DI->getDef() != OpRec)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand type '" + DI->getDef()->getName() +
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"' does not match expansion operand type '" +
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OpRec->getName() + "'");
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StringMap<unsigned>::const_iterator SourceOp =
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SourceOperands.find(Dag->getArgNameStr(DagIdx));
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if (SourceOp == SourceOperands.end())
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', output operand '" +
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Dag->getArgNameStr(DagIdx) +
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"' has no matching source operand");
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const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];
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if (NumOps != SrcOpnd.MINumOperands)
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PrintFatalError(
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Rec,
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"In pseudo instruction '" + Rec->getName() + "', output operand '" +
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OpRec->getName() +
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"' has a different number of sub operands than source operand '" +
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SrcOpnd.Rec->getName() + "'");
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// Source operand maps to destination operand. Do it for each corresponding
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// MachineInstr operand, not just the first.
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for (unsigned I = 0, E = NumOps; I != E; ++I) {
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auto &Entry = OperandMap[MIOpNo + I];
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Entry.Kind = OpData::Operand;
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Entry.OpNo = SrcOpnd.MIOperandNo + I;
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}
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LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << DagIdx
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<< "\n");
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} else if (const auto *II = dyn_cast<IntInit>(DagArg)) {
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assert(NumOps == 1);
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Imm;
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Entry.ImmVal = II->getValue();
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} else if (const auto *BI = dyn_cast<BitsInit>(DagArg)) {
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assert(NumOps == 1);
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Imm;
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Entry.ImmVal = *BI->convertInitializerToInt();
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} else {
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llvm_unreachable("Unhandled pseudo-expansion argument type!");
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}
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}
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void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
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LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
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// Validate that the result pattern has the corrent number and types
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// of arguments for the instruction it references.
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const DagInit *Dag = Rec->getValueAsDag("ResultInst");
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assert(Dag && "Missing result instruction in pseudo expansion!");
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LLVM_DEBUG(dbgs() << " Result: " << *Dag << "\n");
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const DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
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if (!OpDef)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator is not a record");
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const Record *Operator = OpDef->getDef();
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if (!Operator->isSubClassOf("Instruction"))
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' is not an instruction");
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CodeGenInstruction Insn(Operator);
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if (Insn.isCodeGenOnly || Insn.isPseudo)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' cannot be a pseudo instruction");
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if (Insn.Operands.size() != Dag->getNumArgs())
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', result operator '" + Operator->getName() +
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"' has the wrong number of operands");
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// If there are more operands that weren't in the DAG, they have to
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// be operands that have default values, or we have an error. Currently,
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// Operands that are a subclass of OperandWithDefaultOp have default values.
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// Validate that each result pattern argument has a matching (by name)
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// argument in the source instruction, in either the (outs) or (ins) list.
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// Also check that the type of the arguments match.
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//
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// Record the mapping of the source to result arguments for use by
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// the lowering emitter.
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CodeGenInstruction SourceInsn(Rec);
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StringMap<unsigned> SourceOperands;
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for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands))
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SourceOperands[SrcOp.Name] = Idx;
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unsigned NumMIOperands = 0;
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for (const auto &Op : Insn.Operands)
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NumMIOperands += Op.MINumOperands;
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IndexedMap<OpData> OperandMap;
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OperandMap.grow(NumMIOperands);
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// FIXME: This pass currently can only expand a pseudo to a single
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// instruction. The pseudo expansion really should take a list of dags, not
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// just a single dag, so we can do fancier things.
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LLVM_DEBUG(dbgs() << " Operand mapping:\n");
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for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) {
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unsigned MIOpNo = DstOp.MIOperandNo;
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if (const auto *SubDag = dyn_cast<DagInit>(Dag->getArg(Idx))) {
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if (!DstOp.MIOperandInfo || DstOp.MIOperandInfo->getNumArgs() == 0)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand '" + DstOp.Rec->getName() +
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"' does not have suboperands");
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if (DstOp.MINumOperands != SubDag->getNumArgs()) {
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PrintFatalError(
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Rec, "In pseudo instruction '" + Rec->getName() + "', '" +
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SubDag->getAsString() +
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"' has wrong number of operands for operand type '" +
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DstOp.Rec->getName() + "'");
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}
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for (unsigned I = 0, E = DstOp.MINumOperands; I != E; ++I) {
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auto *OpndRec = cast<DefInit>(DstOp.MIOperandInfo->getArg(I))->getDef();
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addOperandMapping(MIOpNo + I, 1, Rec, SubDag, I, OpndRec, OperandMap,
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SourceOperands, SourceInsn);
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}
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} else {
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addOperandMapping(MIOpNo, DstOp.MINumOperands, Rec, Dag, Idx, DstOp.Rec,
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OperandMap, SourceOperands, SourceInsn);
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}
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}
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Expansions.emplace_back(SourceInsn, Insn, OperandMap);
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}
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void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
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// Emit file header.
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emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
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o << "bool " << Target.getName() + "AsmPrinter::\n"
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<< "lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst) {\n";
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if (!Expansions.empty()) {
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o << " Inst.clear();\n"
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<< " switch (MI->getOpcode()) {\n"
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<< " default: return false;\n";
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for (auto &Expansion : Expansions) {
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CodeGenInstruction &Source = Expansion.Source;
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CodeGenInstruction &Dest = Expansion.Dest;
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o << " case " << Source.Namespace << "::" << Source.TheDef->getName()
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<< ": {\n"
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<< " MCOperand MCOp;\n"
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<< " Inst.setOpcode(" << Dest.Namespace
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<< "::" << Dest.TheDef->getName() << ");\n";
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// Copy the operands from the source instruction.
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// FIXME: Instruction operands with defaults values (predicates and cc_out
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// in ARM, for example shouldn't need explicit values in the
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// expansion DAG.
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for (const auto &DestOperand : Dest.Operands) {
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o << " // Operand: " << DestOperand.Name << "\n";
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unsigned MIOpNo = DestOperand.MIOperandNo;
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for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
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switch (Expansion.OperandMap[MIOpNo + i].Kind) {
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case OpData::Operand:
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o << " lowerOperand(MI->getOperand("
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<< Expansion.OperandMap[MIOpNo + i].OpNo << "), MCOp);\n"
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<< " Inst.addOperand(MCOp);\n";
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break;
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case OpData::Imm:
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o << " Inst.addOperand(MCOperand::createImm("
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<< Expansion.OperandMap[MIOpNo + i].ImmVal << "));\n";
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break;
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case OpData::Reg: {
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const Record *Reg = Expansion.OperandMap[MIOpNo + i].RegRec;
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o << " Inst.addOperand(MCOperand::createReg(";
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// "zero_reg" is special.
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if (Reg->getName() == "zero_reg")
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o << "0";
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else
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o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
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o << "));\n";
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break;
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}
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}
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}
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}
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if (Dest.Operands.isVariadic) {
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unsigned LastOpNo = 0;
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for (const auto &Op : Source.Operands)
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LastOpNo += Op.MINumOperands;
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o << " // variable_ops\n";
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o << " for (unsigned i = " << LastOpNo
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<< ", e = MI->getNumOperands(); i != e; ++i)\n"
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<< " if (lowerOperand(MI->getOperand(i), MCOp))\n"
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<< " Inst.addOperand(MCOp);\n";
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}
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o << " break;\n"
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<< " }\n";
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}
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o << " }\n return true;";
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} else {
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o << " return false;";
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}
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o << "\n}\n\n";
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}
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void PseudoLoweringEmitter::run(raw_ostream &OS) {
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StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};
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// Process the pseudo expansion definitions, validating them as we do so.
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TGTimer &Timer = Records.getTimer();
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Timer.startTimer("Process definitions");
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for (const Record *Inst : Records.getAllDerivedDefinitions(Classes))
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evaluateExpansion(Inst);
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// Generate expansion code to lower the pseudo to an MCInst of the real
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// instruction.
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Timer.startTimer("Emit expansion code");
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emitLoweringEmitter(OS);
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}
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static TableGen::Emitter::OptClass<PseudoLoweringEmitter>
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X("gen-pseudo-lowering", "Generate pseudo instruction lowering");
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