vasilito
facf0c92e0
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354 lines
8.4 KiB
C
354 lines
8.4 KiB
C
/* Spin locks for communication between threads and signal handlers.
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Copyright (C) 2020-2024 Free Software Foundation, Inc.
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This file is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation; either version 2.1 of the
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License, or (at your option) any later version.
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This file is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>. */
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/* Written by Bruno Haible <bruno@clisp.org>, 2020. */
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#include <config.h>
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/* Specification. */
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#include "asyncsafe-spin.h"
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#include <stdlib.h>
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#if defined _AIX
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# include <sys/atomic_op.h>
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#endif
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#if 0x590 <= __SUNPRO_C && __STDC__
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# define asm __asm
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#endif
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#if defined _WIN32 && ! defined __CYGWIN__
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/* Use Windows threads. */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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glwthread_spin_init (lock);
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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glwthread_spin_lock (lock);
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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if (glwthread_spin_unlock (lock))
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abort ();
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}
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void
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asyncsafe_spin_destroy (asyncsafe_spinlock_t *lock)
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{
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glwthread_spin_destroy (lock);
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}
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#else
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# if HAVE_PTHREAD_H
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/* Use POSIX threads. */
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/* We don't use semaphores (although sem_post() is allowed in signal handlers),
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because it would require to link with -lrt on HP-UX 11, OSF/1, Solaris 10,
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and also because on macOS only named semaphores work.
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We don't use the C11 <stdatomic.h> (available in GCC >= 4.9) because it would
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require to link with -latomic. */
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# if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 7) \
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|| __clang_major__ > 3 || (__clang_major__ == 3 && __clang_minor__ >= 1)) \
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&& !defined __ibmxl__
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/* Use GCC built-ins (available in GCC >= 4.7 and clang >= 3.1) that operate on
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the first byte of the lock.
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Documentation:
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<https://gcc.gnu.org/onlinedocs/gcc-4.7.0/gcc/_005f_005fatomic-Builtins.html>
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*/
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# if 1
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/* An implementation that verifies the unlocks. */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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__atomic_store_n (lock, 0, __ATOMIC_SEQ_CST);
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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/* Wait until *lock becomes 0, then replace it with 1. */
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asyncsafe_spinlock_t zero;
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while (!(zero = 0,
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__atomic_compare_exchange_n (lock, &zero, 1, false,
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)))
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;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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/* If *lock is 1, then replace it with 0. */
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asyncsafe_spinlock_t one = 1;
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if (!__atomic_compare_exchange_n (lock, &one, 0, false,
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
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abort ();
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}
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# else
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/* An implementation that is a little bit more optimized, but does not verify
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the unlocks. */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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__atomic_clear (lock, __ATOMIC_SEQ_CST);
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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while (__atomic_test_and_set (lock, __ATOMIC_SEQ_CST))
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;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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__atomic_clear (lock, __ATOMIC_SEQ_CST);
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}
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# endif
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# elif (((__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1)) \
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|| __clang_major__ >= 3) \
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&& HAVE_ATOMIC_COMPARE_AND_SWAP_GCC41)
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/* Use GCC built-ins (available on many platforms with GCC >= 4.1 or
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clang >= 3.0).
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Documentation:
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<https://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html> */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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*vp = 0;
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__sync_synchronize ();
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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/* Wait until *lock becomes 0, then replace it with 1. */
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while (__sync_val_compare_and_swap (lock, 0, 1) != 0)
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;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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/* If *lock is 1, then replace it with 0. */
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if (__sync_val_compare_and_swap (lock, 1, 0) != 1)
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abort ();
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}
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# elif defined _AIX
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/* AIX */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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atomic_p vp = (int *) lock;
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_clear_lock (vp, 0);
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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atomic_p vp = (int *) lock;
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while (_check_lock (vp, 0, 1))
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;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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atomic_p vp = (int *) lock;
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if (_check_lock (vp, 1, 0))
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abort ();
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}
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# elif ((defined __GNUC__ || defined __clang__ || defined __SUNPRO_C) && (defined __sparc || defined __i386 || defined __x86_64__)) || (defined __TINYC__ && (defined __i386 || defined __x86_64__))
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/* For older versions of GCC or clang, use inline assembly.
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GCC, clang, and the Oracle Studio C 12 compiler understand GCC's extended
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asm syntax, but the plain Oracle Studio C 11 compiler understands only
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simple asm. */
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/* An implementation that verifies the unlocks. */
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static void
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memory_barrier (void)
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{
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# if defined __GNUC__ || defined __clang__ || __SUNPRO_C >= 0x590 || defined __TINYC__
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# if defined __i386 || defined __x86_64__
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# if defined __TINYC__ && defined __i386
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/* Cannot use the SSE instruction "mfence" with this compiler. */
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asm volatile ("lock orl $0,(%esp)");
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# else
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asm volatile ("mfence");
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# endif
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# endif
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# if defined __sparc
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asm volatile ("membar 2");
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# endif
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# else
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# if defined __i386 || defined __x86_64__
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asm ("mfence");
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# endif
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# if defined __sparc
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asm ("membar 2");
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# endif
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# endif
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}
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/* Store NEWVAL in *VP if the old value *VP is == CMP.
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Return the old value. */
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static unsigned int
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atomic_compare_and_swap (volatile unsigned int *vp, unsigned int cmp,
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unsigned int newval)
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{
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# if defined __GNUC__ || defined __clang__ || __SUNPRO_C >= 0x590 || defined __TINYC__
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unsigned int oldval;
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# if defined __i386 || defined __x86_64__
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asm volatile (" lock\n cmpxchgl %3,(%1)"
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: "=a" (oldval) : "r" (vp), "a" (cmp), "r" (newval) : "memory");
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# endif
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# if defined __sparc
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asm volatile (" cas [%1],%2,%3\n"
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" mov %3,%0"
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: "=r" (oldval) : "r" (vp), "r" (cmp), "r" (newval) : "memory");
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# endif
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return oldval;
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# else /* __SUNPRO_C */
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# if defined __x86_64__
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asm (" movl %esi,%eax\n"
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" lock\n cmpxchgl %edx,(%rdi)");
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# elif defined __i386
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asm (" movl 16(%ebp),%ecx\n"
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" movl 12(%ebp),%eax\n"
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" movl 8(%ebp),%edx\n"
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" lock\n cmpxchgl %ecx,(%edx)");
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# endif
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# if defined __sparc
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asm (" cas [%i0],%i1,%i2\n"
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" mov %i2,%i0");
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# endif
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# endif
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}
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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*vp = 0;
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memory_barrier ();
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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while (atomic_compare_and_swap (vp, 0, 1) != 0)
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;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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if (atomic_compare_and_swap (vp, 1, 0) != 1)
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abort ();
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}
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# else
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/* Fallback code. It has some race conditions. */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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*vp = 0;
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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while (*vp)
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;
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*vp = 1;
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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volatile unsigned int *vp = lock;
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*vp = 0;
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}
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# endif
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# else
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/* Provide a dummy implementation for single-threaded applications. */
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void
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asyncsafe_spin_init (asyncsafe_spinlock_t *lock)
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{
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}
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static inline void
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do_lock (asyncsafe_spinlock_t *lock)
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{
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}
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static inline void
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do_unlock (asyncsafe_spinlock_t *lock)
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{
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}
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# endif
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void
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asyncsafe_spin_destroy (asyncsafe_spinlock_t *lock)
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{
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}
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#endif
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void
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asyncsafe_spin_lock (asyncsafe_spinlock_t *lock,
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const sigset_t *mask, sigset_t *saved_mask)
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{
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sigprocmask (SIG_BLOCK, mask, saved_mask); /* equivalent to pthread_sigmask */
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do_lock (lock);
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}
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void
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asyncsafe_spin_unlock (asyncsafe_spinlock_t *lock, const sigset_t *saved_mask)
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{
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do_unlock (lock);
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sigprocmask (SIG_SETMASK, saved_mask, NULL); /* equivalent to pthread_sigmask */
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}
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