vasilito
ff4ff35918
Red Bear OS is a full fork. All sources must be available from git clone with zero network access. Removed gitignore rules that excluded fetched source trees under recipes/*/source/, local/recipes/kde/*/source/, local/recipes/qt/*/source/, and vendor source trees. Build artifacts (target/, build/, source.tar, *.o, *.so) remain excluded. 127291 files added — kernel, relibc, base, bootloader, pkgar, all KDE/Qt frameworks, mesa, wayland, DRM drivers, and every other recipe source.
75 lines
2.6 KiB
Plaintext
75 lines
2.6 KiB
Plaintext
Copyright 2003, 2004, 2006, 2008 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of either:
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* the GNU Lesser General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your
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option) any later version.
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or
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* the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any
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later version.
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or both in parallel, as here.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received copies of the GNU General Public License and the
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GNU Lesser General Public License along with the GNU MP Library. If not,
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see https://www.gnu.org/licenses/.
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AMD64 MPN SUBROUTINES
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This directory contains mpn functions for AMD64 chips. It is also useful
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for 64-bit Pentiums, and "Core 2".
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RELEVANT OPTIMIZATION ISSUES
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The Opteron and Athlon64 can sustain up to 3 instructions per cycle, but in
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practice that is only possible for integer instructions. But almost any
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three integer instructions can issue simultaneously, including any 3 ALU
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operations, including shifts. Up to two memory operations can issue each
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cycle.
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Scheduling typically requires that load-use instructions are split into
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separate load and use instructions. That requires more decode resources,
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and it is rarely a win. Opteron/Athlon64 have deep out-of-order core.
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Optimizing for 64-bit Pentium4 is probably a waste of time, as the most
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critical instructions are very poorly implemented here. Perhaps we could
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save a cycle or two, but the most common loops now run at between 10 and 22
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cycles, so a saved cycle isn't too exciting.
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The new spin of the venerable P6 core, the "Core 2" is much better than the
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Pentium4 for the GMP loops. Its integer pipeline is somewhat similar to to
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the Opteron/Athlon64 pipeline, except that the GMP favourites ADC/SBB and
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MUL are slower. Furthermore, an INC/DEC followed by ADC/SBB incur a
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pipeline stall of around 10 cycles. The default mpn_add_n and mpn_sub_n
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code suffers badly from the stall. The code in the core2 subdirectory uses
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the almost forgotten instruction JRCXZ for loop control, and updates the
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induction variable using LEA.
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REFERENCES
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"System V Application Binary Interface AMD64 Architecture Processor
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Supplement", draft version 0.99, December 2007.
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http://www.x86-64.org/documentation/abi.pdf
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