vasilito
ff4ff35918
Red Bear OS is a full fork. All sources must be available from git clone with zero network access. Removed gitignore rules that excluded fetched source trees under recipes/*/source/, local/recipes/kde/*/source/, local/recipes/qt/*/source/, and vendor source trees. Build artifacts (target/, build/, source.tar, *.o, *.so) remain excluded. 127291 files added — kernel, relibc, base, bootloader, pkgar, all KDE/Qt frameworks, mesa, wayland, DRM drivers, and every other recipe source.
709 lines
12 KiB
NASM
709 lines
12 KiB
NASM
dnl PowerPC-64 mpn_mul_basecase.
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dnl Copyright 1999-2001, 2003-2006, 2008 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C POWER3/PPC630 6-18
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C POWER4/PPC970 8
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C POWER5 8
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C POWER6 24
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C INPUT PARAMETERS
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define(`rp', `r3')
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define(`up', `r4')
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define(`un', `r5')
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define(`vp', `r6')
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define(`vn', `r7')
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define(`v0', `r25')
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define(`outer_rp', `r22')
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define(`outer_up', `r23')
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ASM_START()
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PROLOGUE(mpn_mul_basecase)
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C Special code for un <= 2, for efficiency of these important cases,
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C and since it simplifies the default code.
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cmpdi cr0, un, 2
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bgt cr0, L(un_gt2)
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cmpdi cr6, vn, 1
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ld r7, 0(vp)
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ld r5, 0(up)
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mulld r8, r5, r7 C weight 0
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mulhdu r9, r5, r7 C weight 1
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std r8, 0(rp)
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beq cr0, L(2x)
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std r9, 8(rp)
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blr
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ALIGN(16)
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L(2x): ld r0, 8(up)
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mulld r8, r0, r7 C weight 1
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mulhdu r10, r0, r7 C weight 2
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addc r9, r9, r8
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addze r10, r10
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bne cr6, L(2x2)
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std r9, 8(rp)
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std r10, 16(rp)
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blr
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ALIGN(16)
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L(2x2): ld r6, 8(vp)
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nop
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mulld r8, r5, r6 C weight 1
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mulhdu r11, r5, r6 C weight 2
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addc r9, r9, r8
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std r9, 8(rp)
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adde r11, r11, r10
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mulld r12, r0, r6 C weight 2
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mulhdu r0, r0, r6 C weight 3
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addze r0, r0
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addc r11, r11, r12
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addze r0, r0
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std r11, 16(rp)
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std r0, 24(rp)
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blr
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L(un_gt2):
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std r31, -8(r1)
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std r30, -16(r1)
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std r29, -24(r1)
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std r28, -32(r1)
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std r27, -40(r1)
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std r26, -48(r1)
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std r25, -56(r1)
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std r24, -64(r1)
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std r23, -72(r1)
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std r22, -80(r1)
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mr outer_rp, rp
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mr outer_up, up
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ld v0, 0(vp) C new v limb
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addi vp, vp, 8
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ld r26, 0(up)
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rldicl. r0, un, 0,62 C r0 = n & 3, set cr0
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cmpdi cr6, r0, 2
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addi un, un, 1 C compute count...
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srdi un, un, 2 C ...for ctr
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mtctr un C copy inner loop count into ctr
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beq cr0, L(b0)
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blt cr6, L(b1)
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beq cr6, L(b2)
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ALIGN(16)
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L(b3): mulld r0, r26, v0
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mulhdu r12, r26, v0
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addic r0, r0, 0
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std r0, 0(rp)
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ld r26, 8(up)
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ld r27, 16(up)
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bdz L(end_m_3)
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ALIGN(16)
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L(lo_m_3):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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ld r26, 24(up)
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nop
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r27, 32(up)
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nop
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adde r0, r0, r12
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adde r24, r24, r31
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mulld r9, r26, v0
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mulhdu r10, r26, v0
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ld r26, 40(up)
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nop
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mulld r11, r27, v0
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mulhdu r12, r27, v0
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ld r27, 48(up)
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std r0, 8(rp)
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adde r9, r9, r8
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std r24, 16(rp)
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adde r11, r11, r10
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std r9, 24(rp)
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addi up, up, 32
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std r11, 32(rp)
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addi rp, rp, 32
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bdnz L(lo_m_3)
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ALIGN(16)
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L(end_m_3):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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adde r0, r0, r12
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adde r24, r24, r31
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std r0, 8(rp)
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std r24, 16(rp)
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addze r8, r8
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std r8, 24(rp)
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addic. vn, vn, -1
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beq L(ret)
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ALIGN(16)
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L(outer_lo_3):
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mtctr un C copy inner loop count into ctr
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addi rp, outer_rp, 8
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mr up, outer_up
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addi outer_rp, outer_rp, 8
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ld v0, 0(vp) C new v limb
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addi vp, vp, 8
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ld r26, 0(up)
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ld r28, 0(rp)
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mulld r0, r26, v0
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mulhdu r12, r26, v0
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addc r0, r0, r28
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std r0, 0(rp)
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ld r26, 8(up)
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ld r27, 16(up)
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bdz L(end_3)
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ALIGN(16) C registers dying
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L(lo_3):
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mulld r0, r26, v0 C
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mulhdu r10, r26, v0 C 26
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ld r26, 24(up) C
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ld r28, 8(rp) C
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mulld r24, r27, v0 C
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mulhdu r8, r27, v0 C 27
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ld r27, 32(up) C
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ld r29, 16(rp) C
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adde r0, r0, r12 C 0 12
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adde r24, r24, r10 C 24 10
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mulld r9, r26, v0 C
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mulhdu r10, r26, v0 C 26
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ld r26, 40(up) C
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ld r30, 24(rp) C
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mulld r11, r27, v0 C
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mulhdu r12, r27, v0 C 27
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ld r27, 48(up) C
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ld r31, 32(rp) C
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adde r9, r9, r8 C 8 9
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adde r11, r11, r10 C 10 11
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addze r12, r12 C 12
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addc r0, r0, r28 C 0 28
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std r0, 8(rp) C 0
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adde r24, r24, r29 C 7 29
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std r24, 16(rp) C 7
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adde r9, r9, r30 C 9 30
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std r9, 24(rp) C 9
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adde r11, r11, r31 C 11 31
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std r11, 32(rp) C 11
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addi up, up, 32 C
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addi rp, rp, 32 C
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bdnz L(lo_3) C
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ALIGN(16)
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L(end_3):
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mulld r0, r26, v0
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mulhdu r10, r26, v0
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ld r28, 8(rp)
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nop
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r29, 16(rp)
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nop
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adde r0, r0, r12
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adde r24, r24, r10
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addze r8, r8
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addc r0, r0, r28
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std r0, 8(rp)
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adde r24, r24, r29
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std r24, 16(rp)
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addze r8, r8
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std r8, 24(rp)
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addic. vn, vn, -1
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bne L(outer_lo_3)
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b L(ret)
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ALIGN(16)
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L(b0): ld r27, 8(up)
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addi up, up, 8
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mulld r0, r26, v0
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mulhdu r10, r26, v0
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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addc r24, r24, r10
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addze r12, r8
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std r0, 0(rp)
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std r24, 8(rp)
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addi rp, rp, 8
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ld r26, 8(up)
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ld r27, 16(up)
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bdz L(end_m_0)
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ALIGN(16)
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L(lo_m_0):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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ld r26, 24(up)
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nop
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r27, 32(up)
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nop
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adde r0, r0, r12
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adde r24, r24, r31
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mulld r9, r26, v0
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mulhdu r10, r26, v0
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ld r26, 40(up)
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nop
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mulld r11, r27, v0
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mulhdu r12, r27, v0
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ld r27, 48(up)
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std r0, 8(rp)
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adde r9, r9, r8
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std r24, 16(rp)
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adde r11, r11, r10
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std r9, 24(rp)
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addi up, up, 32
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std r11, 32(rp)
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addi rp, rp, 32
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bdnz L(lo_m_0)
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ALIGN(16)
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L(end_m_0):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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adde r0, r0, r12
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adde r24, r24, r31
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std r0, 8(rp)
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addze r8, r8
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std r24, 16(rp)
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addic. vn, vn, -1
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std r8, 24(rp)
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nop
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beq L(ret)
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ALIGN(16)
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L(outer_lo_0):
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mtctr un C copy inner loop count into ctr
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addi rp, outer_rp, 16
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addi up, outer_up, 8
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addi outer_rp, outer_rp, 8
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ld v0, 0(vp) C new v limb
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addi vp, vp, 8
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ld r26, -8(up)
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ld r27, 0(up)
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ld r28, -8(rp)
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ld r29, 0(rp)
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nop
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nop
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mulld r0, r26, v0
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mulhdu r10, r26, v0
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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addc r24, r24, r10
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addze r12, r8
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addc r0, r0, r28
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std r0, -8(rp)
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adde r24, r24, r29
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std r24, 0(rp)
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ld r26, 8(up)
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ld r27, 16(up)
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bdz L(end_0)
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ALIGN(16) C registers dying
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L(lo_0):
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mulld r0, r26, v0 C
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mulhdu r10, r26, v0 C 26
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ld r26, 24(up) C
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ld r28, 8(rp) C
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mulld r24, r27, v0 C
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mulhdu r8, r27, v0 C 27
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ld r27, 32(up) C
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ld r29, 16(rp) C
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adde r0, r0, r12 C 0 12
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adde r24, r24, r10 C 24 10
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mulld r9, r26, v0 C
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mulhdu r10, r26, v0 C 26
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ld r26, 40(up) C
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ld r30, 24(rp) C
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mulld r11, r27, v0 C
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mulhdu r12, r27, v0 C 27
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ld r27, 48(up) C
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ld r31, 32(rp) C
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adde r9, r9, r8 C 8 9
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adde r11, r11, r10 C 10 11
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addze r12, r12 C 12
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addc r0, r0, r28 C 0 28
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std r0, 8(rp) C 0
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adde r24, r24, r29 C 7 29
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std r24, 16(rp) C 7
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adde r9, r9, r30 C 9 30
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std r9, 24(rp) C 9
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adde r11, r11, r31 C 11 31
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std r11, 32(rp) C 11
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addi up, up, 32 C
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addi rp, rp, 32 C
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bdnz L(lo_0) C
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ALIGN(16)
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L(end_0):
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mulld r0, r26, v0
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mulhdu r10, r26, v0
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ld r28, 8(rp)
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nop
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r29, 16(rp)
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nop
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adde r0, r0, r12
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adde r24, r24, r10
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addze r8, r8
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addic. vn, vn, -1
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addc r0, r0, r28
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std r0, 8(rp)
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adde r24, r24, r29
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std r24, 16(rp)
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addze r8, r8
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std r8, 24(rp)
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bne L(outer_lo_0)
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b L(ret)
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ALIGN(16)
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L(b1): ld r27, 8(up)
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nop
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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ld r26, 16(up)
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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mulld r9, r26, v0
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mulhdu r10, r26, v0
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addc r24, r24, r31
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adde r9, r9, r8
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addze r12, r10
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std r0, 0(rp)
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std r24, 8(rp)
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std r9, 16(rp)
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addi up, up, 16
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addi rp, rp, 16
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ld r26, 8(up)
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ld r27, 16(up)
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bdz L(end_m_1)
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ALIGN(16)
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L(lo_m_1):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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ld r26, 24(up)
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nop
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r27, 32(up)
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nop
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adde r0, r0, r12
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adde r24, r24, r31
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mulld r9, r26, v0
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mulhdu r10, r26, v0
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ld r26, 40(up)
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nop
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mulld r11, r27, v0
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mulhdu r12, r27, v0
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ld r27, 48(up)
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std r0, 8(rp)
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adde r9, r9, r8
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std r24, 16(rp)
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adde r11, r11, r10
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std r9, 24(rp)
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addi up, up, 32
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std r11, 32(rp)
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addi rp, rp, 32
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bdnz L(lo_m_1)
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ALIGN(16)
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L(end_m_1):
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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adde r0, r0, r12
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adde r24, r24, r31
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std r0, 8(rp)
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addze r8, r8
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std r24, 16(rp)
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addic. vn, vn, -1
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std r8, 24(rp)
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nop
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beq L(ret)
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ALIGN(16)
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L(outer_lo_1):
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mtctr un C copy inner loop count into ctr
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addi rp, outer_rp, 24
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addi up, outer_up, 16
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addi outer_rp, outer_rp, 8
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ld v0, 0(vp) C new v limb
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addi vp, vp, 8
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ld r26, -16(up)
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ld r27, -8(up)
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mulld r0, r26, v0
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mulhdu r31, r26, v0
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ld r26, 0(up)
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ld r28, -16(rp)
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mulld r24, r27, v0
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mulhdu r8, r27, v0
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ld r29, -8(rp)
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ld r30, 0(rp)
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mulld r9, r26, v0
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mulhdu r10, r26, v0
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addc r24, r24, r31
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adde r9, r9, r8
|
|
addze r12, r10
|
|
addc r0, r0, r28
|
|
std r0, -16(rp)
|
|
adde r24, r24, r29
|
|
std r24, -8(rp)
|
|
adde r9, r9, r30
|
|
std r9, 0(rp)
|
|
ld r26, 8(up)
|
|
ld r27, 16(up)
|
|
bdz L(end_1)
|
|
|
|
ALIGN(16) C registers dying
|
|
L(lo_1):
|
|
mulld r0, r26, v0 C
|
|
mulhdu r10, r26, v0 C 26
|
|
ld r26, 24(up) C
|
|
ld r28, 8(rp) C
|
|
mulld r24, r27, v0 C
|
|
mulhdu r8, r27, v0 C 27
|
|
ld r27, 32(up) C
|
|
ld r29, 16(rp) C
|
|
adde r0, r0, r12 C 0 12
|
|
adde r24, r24, r10 C 24 10
|
|
mulld r9, r26, v0 C
|
|
mulhdu r10, r26, v0 C 26
|
|
ld r26, 40(up) C
|
|
ld r30, 24(rp) C
|
|
mulld r11, r27, v0 C
|
|
mulhdu r12, r27, v0 C 27
|
|
ld r27, 48(up) C
|
|
ld r31, 32(rp) C
|
|
adde r9, r9, r8 C 8 9
|
|
adde r11, r11, r10 C 10 11
|
|
addze r12, r12 C 12
|
|
addc r0, r0, r28 C 0 28
|
|
std r0, 8(rp) C 0
|
|
adde r24, r24, r29 C 7 29
|
|
std r24, 16(rp) C 7
|
|
adde r9, r9, r30 C 9 30
|
|
std r9, 24(rp) C 9
|
|
adde r11, r11, r31 C 11 31
|
|
std r11, 32(rp) C 11
|
|
addi up, up, 32 C
|
|
addi rp, rp, 32 C
|
|
bdnz L(lo_1) C
|
|
|
|
ALIGN(16)
|
|
L(end_1):
|
|
mulld r0, r26, v0
|
|
mulhdu r10, r26, v0
|
|
ld r28, 8(rp)
|
|
nop
|
|
mulld r24, r27, v0
|
|
mulhdu r8, r27, v0
|
|
ld r29, 16(rp)
|
|
nop
|
|
adde r0, r0, r12
|
|
adde r24, r24, r10
|
|
addze r8, r8
|
|
addic. vn, vn, -1
|
|
addc r0, r0, r28
|
|
std r0, 8(rp)
|
|
adde r24, r24, r29
|
|
std r24, 16(rp)
|
|
addze r8, r8
|
|
std r8, 24(rp)
|
|
bne L(outer_lo_1)
|
|
b L(ret)
|
|
|
|
|
|
ALIGN(16)
|
|
L(b2): ld r27, 8(up)
|
|
addi up, up, -8
|
|
addi rp, rp, -8
|
|
li r12, 0
|
|
addic r12, r12, 0
|
|
|
|
ALIGN(16)
|
|
L(lo_m_2):
|
|
mulld r0, r26, v0
|
|
mulhdu r31, r26, v0
|
|
ld r26, 24(up)
|
|
nop
|
|
mulld r24, r27, v0
|
|
mulhdu r8, r27, v0
|
|
ld r27, 32(up)
|
|
nop
|
|
adde r0, r0, r12
|
|
adde r24, r24, r31
|
|
mulld r9, r26, v0
|
|
mulhdu r10, r26, v0
|
|
ld r26, 40(up)
|
|
nop
|
|
mulld r11, r27, v0
|
|
mulhdu r12, r27, v0
|
|
ld r27, 48(up)
|
|
std r0, 8(rp)
|
|
adde r9, r9, r8
|
|
std r24, 16(rp)
|
|
adde r11, r11, r10
|
|
std r9, 24(rp)
|
|
addi up, up, 32
|
|
std r11, 32(rp)
|
|
|
|
addi rp, rp, 32
|
|
bdnz L(lo_m_2)
|
|
|
|
ALIGN(16)
|
|
L(end_m_2):
|
|
mulld r0, r26, v0
|
|
mulhdu r31, r26, v0
|
|
|
|
mulld r24, r27, v0
|
|
mulhdu r8, r27, v0
|
|
|
|
adde r0, r0, r12
|
|
adde r24, r24, r31
|
|
|
|
std r0, 8(rp)
|
|
addze r8, r8
|
|
std r24, 16(rp)
|
|
addic. vn, vn, -1
|
|
std r8, 24(rp)
|
|
nop
|
|
beq L(ret)
|
|
|
|
ALIGN(16)
|
|
L(outer_lo_2):
|
|
mtctr un C copy inner loop count into ctr
|
|
addi rp, outer_rp, 0
|
|
addi up, outer_up, -8
|
|
addi outer_rp, outer_rp, 8
|
|
ld v0, 0(vp) C new v limb
|
|
addi vp, vp, 8
|
|
ld r26, 8(up)
|
|
ld r27, 16(up)
|
|
li r12, 0
|
|
addic r12, r12, 0
|
|
|
|
ALIGN(16) C registers dying
|
|
L(lo_2):
|
|
mulld r0, r26, v0 C
|
|
mulhdu r10, r26, v0 C 26
|
|
ld r26, 24(up) C
|
|
ld r28, 8(rp) C
|
|
mulld r24, r27, v0 C
|
|
mulhdu r8, r27, v0 C 27
|
|
ld r27, 32(up) C
|
|
ld r29, 16(rp) C
|
|
adde r0, r0, r12 C 0 12
|
|
adde r24, r24, r10 C 24 10
|
|
mulld r9, r26, v0 C
|
|
mulhdu r10, r26, v0 C 26
|
|
ld r26, 40(up) C
|
|
ld r30, 24(rp) C
|
|
mulld r11, r27, v0 C
|
|
mulhdu r12, r27, v0 C 27
|
|
ld r27, 48(up) C
|
|
ld r31, 32(rp) C
|
|
adde r9, r9, r8 C 8 9
|
|
adde r11, r11, r10 C 10 11
|
|
addze r12, r12 C 12
|
|
addc r0, r0, r28 C 0 28
|
|
std r0, 8(rp) C 0
|
|
adde r24, r24, r29 C 7 29
|
|
std r24, 16(rp) C 7
|
|
adde r9, r9, r30 C 9 30
|
|
std r9, 24(rp) C 9
|
|
adde r11, r11, r31 C 11 31
|
|
std r11, 32(rp) C 11
|
|
addi up, up, 32 C
|
|
addi rp, rp, 32 C
|
|
bdnz L(lo_2) C
|
|
|
|
ALIGN(16)
|
|
L(end_2):
|
|
mulld r0, r26, v0
|
|
mulhdu r10, r26, v0
|
|
ld r28, 8(rp)
|
|
nop
|
|
mulld r24, r27, v0
|
|
mulhdu r8, r27, v0
|
|
ld r29, 16(rp)
|
|
nop
|
|
adde r0, r0, r12
|
|
adde r24, r24, r10
|
|
addze r8, r8
|
|
addic. vn, vn, -1
|
|
addc r0, r0, r28
|
|
std r0, 8(rp)
|
|
adde r24, r24, r29
|
|
std r24, 16(rp)
|
|
addze r8, r8
|
|
std r8, 24(rp)
|
|
bne L(outer_lo_2)
|
|
b L(ret)
|
|
|
|
|
|
L(ret): ld r31, -8(r1)
|
|
ld r30, -16(r1)
|
|
ld r29, -24(r1)
|
|
ld r28, -32(r1)
|
|
ld r27, -40(r1)
|
|
ld r26, -48(r1)
|
|
ld r25, -56(r1)
|
|
ld r24, -64(r1)
|
|
ld r23, -72(r1)
|
|
ld r22, -80(r1)
|
|
blr
|
|
EPILOGUE()
|