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280 lines
6.6 KiB
NASM
280 lines
6.6 KiB
NASM
dnl ARM Neon mpn_lshift and mpn_rshift.
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dnl Contributed to the GNU project by Torbjörn Granlund.
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dnl Copyright 2013 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb cycles/limb cycles/limb good
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C aligned unaligned best seen for cpu?
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C StrongARM - -
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C XScale - -
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C Cortex-A7 ? ?
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C Cortex-A8 ? ?
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C Cortex-A9 3 3 Y
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C Cortex-A15 1.5 1.5 Y
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C We read 64 bits at a time at 32-bit aligned addresses, and except for the
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C first and last store, we write using 64-bit aligned addresses. All shifting
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C is done on 64-bit words in 'extension' registers.
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C
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C It should be possible to read also using 64-bit alignment, by manipulating
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C the shift count for unaligned operands. Not done, since it does not seem to
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C matter for A9 or A15.
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C
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C This will not work in big-endian mode.
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C TODO
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C * Try using 128-bit operations. Note that Neon lacks pure 128-bit shifts,
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C which might make it tricky.
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C * Clean up and simplify.
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C * Consider sharing most of the code for lshift and rshift, since the feed-in
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C code, the loop, and most of the wind-down code are identical.
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C * Replace the basecase code with code using 'extension' registers.
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C * Optimise. It is not clear that this loop insn permutation is optimal for
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C either A9 or A15.
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C INPUT PARAMETERS
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define(`rp', `r0')
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define(`ap', `r1')
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define(`n', `r2')
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define(`cnt', `r3')
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ifdef(`OPERATION_lshift',`
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define(`IFLSH', `$1')
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define(`IFRSH', `')
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define(`X',`0')
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define(`Y',`1')
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define(`func',`mpn_lshift')
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')
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ifdef(`OPERATION_rshift',`
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define(`IFLSH', `')
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define(`IFRSH', `$1')
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define(`X',`1')
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define(`Y',`0')
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define(`func',`mpn_rshift')
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')
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MULFUNC_PROLOGUE(mpn_lshift mpn_rshift)
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ASM_START(neon)
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TEXT
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ALIGN(64)
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PROLOGUE(func)
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IFLSH(` mov r12, n, lsl #2 ')
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IFLSH(` add rp, rp, r12 ')
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IFLSH(` add ap, ap, r12 ')
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cmp n, #4 C SIMD code n limit
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ble L(base)
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ifdef(`OPERATION_lshift',`
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vdup.32 d6, r3 C left shift count is positive
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sub r3, r3, #64 C right shift count is negative
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vdup.32 d7, r3
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mov r12, #-8') C lshift pointer update offset
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ifdef(`OPERATION_rshift',`
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rsb r3, r3, #0 C right shift count is negative
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vdup.32 d6, r3
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add r3, r3, #64 C left shift count is positive
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vdup.32 d7, r3
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mov r12, #8') C rshift pointer update offset
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IFLSH(` sub ap, ap, #8 ')
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vld1.32 {d19}, [ap], r12 C load initial 2 limbs
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vshl.u64 d18, d19, d7 C retval
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tst rp, #4 C is rp 64-bit aligned already?
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beq L(rp_aligned) C yes, skip
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IFLSH(` add ap, ap, #4 ') C move back ap pointer
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IFRSH(` sub ap, ap, #4 ') C move back ap pointer
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vshl.u64 d4, d19, d6
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sub n, n, #1 C first limb handled
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IFLSH(` sub rp, rp, #4 ')
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vst1.32 {d4[Y]}, [rp]IFRSH(!) C store first limb, rp gets aligned
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vld1.32 {d19}, [ap], r12 C load ap[1] and ap[2]
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L(rp_aligned):
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IFLSH(` sub rp, rp, #8 ')
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subs n, n, #6
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blt L(two_or_three_more)
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tst n, #2
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beq L(2)
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L(1): vld1.32 {d17}, [ap], r12
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vshl.u64 d5, d19, d6
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vld1.32 {d16}, [ap], r12
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vshl.u64 d0, d17, d7
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vshl.u64 d4, d17, d6
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sub n, n, #2
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b L(mid)
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L(2): vld1.32 {d16}, [ap], r12
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vshl.u64 d4, d19, d6
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vld1.32 {d17}, [ap], r12
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vshl.u64 d1, d16, d7
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vshl.u64 d5, d16, d6
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subs n, n, #4
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blt L(end)
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L(top): vld1.32 {d16}, [ap], r12
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vorr d2, d4, d1
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vshl.u64 d0, d17, d7
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vshl.u64 d4, d17, d6
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vst1.32 {d2}, [rp:64], r12
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L(mid): vld1.32 {d17}, [ap], r12
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vorr d3, d5, d0
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vshl.u64 d1, d16, d7
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vshl.u64 d5, d16, d6
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vst1.32 {d3}, [rp:64], r12
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subs n, n, #4
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bge L(top)
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L(end): tst n, #1
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beq L(evn)
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vorr d2, d4, d1
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vst1.32 {d2}, [rp:64], r12
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b L(cj1)
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L(evn): vorr d2, d4, d1
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vshl.u64 d0, d17, d7
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vshl.u64 d16, d17, d6
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vst1.32 {d2}, [rp:64], r12
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vorr d2, d5, d0
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b L(cj2)
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C Load last 2 - 3 limbs, store last 4 - 5 limbs
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L(two_or_three_more):
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tst n, #1
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beq L(l2)
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L(l3): vshl.u64 d5, d19, d6
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vld1.32 {d17}, [ap], r12
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L(cj1): veor d16, d16, d16
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IFLSH(` add ap, ap, #4 ')
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vld1.32 {d16[Y]}, [ap], r12
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vshl.u64 d0, d17, d7
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vshl.u64 d4, d17, d6
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vorr d3, d5, d0
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vshl.u64 d1, d16, d7
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vshl.u64 d5, d16, d6
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vst1.32 {d3}, [rp:64], r12
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vorr d2, d4, d1
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vst1.32 {d2}, [rp:64], r12
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IFLSH(` add rp, rp, #4 ')
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vst1.32 {d5[Y]}, [rp]
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vmov.32 r0, d18[X]
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bx lr
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L(l2): vld1.32 {d16}, [ap], r12
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vshl.u64 d4, d19, d6
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vshl.u64 d1, d16, d7
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vshl.u64 d16, d16, d6
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vorr d2, d4, d1
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L(cj2): vst1.32 {d2}, [rp:64], r12
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vst1.32 {d16}, [rp]
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vmov.32 r0, d18[X]
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bx lr
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define(`tnc', `r12')
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L(base):
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push {r4, r6, r7, r8}
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ifdef(`OPERATION_lshift',`
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ldr r4, [ap, #-4]!
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rsb tnc, cnt, #32
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mov r7, r4, lsl cnt
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tst n, #1
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beq L(ev) C n even
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L(od): subs n, n, #2
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bcc L(ed1) C n = 1
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ldr r8, [ap, #-4]!
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b L(md) C n = 3
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L(ev): ldr r6, [ap, #-4]!
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subs n, n, #2
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beq L(ed) C n = 3
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C n = 4
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L(tp): ldr r8, [ap, #-4]!
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orr r7, r7, r6, lsr tnc
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str r7, [rp, #-4]!
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mov r7, r6, lsl cnt
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L(md): ldr r6, [ap, #-4]!
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orr r7, r7, r8, lsr tnc
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str r7, [rp, #-4]!
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mov r7, r8, lsl cnt
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L(ed): orr r7, r7, r6, lsr tnc
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str r7, [rp, #-4]!
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mov r7, r6, lsl cnt
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L(ed1): str r7, [rp, #-4]
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mov r0, r4, lsr tnc
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')
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ifdef(`OPERATION_rshift',`
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ldr r4, [ap]
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rsb tnc, cnt, #32
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mov r7, r4, lsr cnt
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tst n, #1
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beq L(ev) C n even
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L(od): subs n, n, #2
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bcc L(ed1) C n = 1
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ldr r8, [ap, #4]!
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b L(md) C n = 3
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L(ev): ldr r6, [ap, #4]!
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subs n, n, #2
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beq L(ed) C n = 2
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C n = 4
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L(tp): ldr r8, [ap, #4]!
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orr r7, r7, r6, lsl tnc
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str r7, [rp], #4
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mov r7, r6, lsr cnt
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L(md): ldr r6, [ap, #4]!
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orr r7, r7, r8, lsl tnc
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str r7, [rp], #4
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mov r7, r8, lsr cnt
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L(ed): orr r7, r7, r6, lsl tnc
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str r7, [rp], #4
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mov r7, r6, lsr cnt
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L(ed1): str r7, [rp], #4
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mov r0, r4, lsl tnc
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')
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pop {r4, r6, r7, r8}
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bx r14
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EPILOGUE()
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