#ifndef _VIRTGPU_DRM_H_
#define _VIRTGPU_DRM_H_

#include <stdint.h>

#define DRM_VIRTGPU_MAP                  0x41
#define DRM_VIRTGPU_EXECBUFFER           0x42
#define DRM_VIRTGPU_GETPARAM             0x43
#define DRM_VIRTGPU_RESOURCE_CREATE      0x44
#define DRM_VIRTGPU_RESOURCE_INFO        0x45
#define DRM_VIRTGPU_TRANSFER_FROM_HOST   0x46
#define DRM_VIRTGPU_TRANSFER_TO_HOST     0x47
#define DRM_VIRTGPU_WAIT                 0x48
#define DRM_VIRTGPU_GET_CAPS             0x49
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x4A
#define DRM_VIRTGPU_CONTEXT_INIT         0x4B

#define drm_virtgpu_resource_create drm_virtgpu_resource_create_3d
#define drm_virtgpu_3d_transfer_to_host drm_virtgpu_transfer_to_host
#define drm_virtgpu_3d_transfer_from_host drm_virtgpu_transfer_from_host
#define drm_virtgpu_3d_wait drm_virtgpu_wait_3d
#define ctx_set_params_ptr ctx_set_params
#define resource_id res_handle

struct drm_virtgpu_3d_box {
	uint32_t x;
	uint32_t y;
	uint32_t z;
	uint32_t w;
	uint32_t h;
	uint32_t d;
};

struct drm_virtgpu_execbuffer {
	uint32_t flags;
	uint32_t size;
	uint64_t command;
	uint64_t bo_handles;
	uint32_t num_bo_handles;
	int32_t fence_fd;
	uint32_t ring_idx;
	uint32_t syncobj_stride;
	uint32_t num_in_syncobjs;
	uint32_t num_out_syncobjs;
	uint64_t in_syncobjs;
	uint64_t out_syncobjs;
};

struct drm_virtgpu_getparam {
	uint64_t param;
	uint64_t value;
};

struct drm_virtgpu_resource_create_3d {
	uint32_t target;
	uint32_t format;
	uint32_t bind;
	uint32_t width;
	uint32_t height;
	uint32_t depth;
	uint32_t array_size;
	uint32_t last_level;
	uint32_t nr_samples;
	uint32_t flags;
	uint32_t bo_handle;
	uint32_t res_handle;
	uint32_t size;
	uint32_t stride;
};

struct drm_virtgpu_resource_info {
	uint32_t bo_handle;
	uint32_t res_handle;
	uint32_t size;
	uint32_t blob_mem;
};

struct drm_virtgpu_transfer_to_host {
	uint32_t bo_handle;
	struct drm_virtgpu_3d_box box;
	uint32_t level;
	uint32_t offset;
	uint32_t stride;
	uint32_t layer_stride;
};

struct drm_virtgpu_transfer_from_host {
	uint32_t bo_handle;
	struct drm_virtgpu_3d_box box;
	uint32_t level;
	uint32_t offset;
	uint32_t stride;
	uint32_t layer_stride;
};

struct drm_virtgpu_wait_3d {
	uint32_t handle;
	uint32_t flags;
};

struct drm_virtgpu_get_caps {
	uint32_t cap_set_id;
	uint32_t cap_set_ver;
	uint64_t addr;
	uint32_t size;
	uint32_t pad;
};

struct drm_virtgpu_resource_create_blob {
	uint32_t blob_mem;
	uint32_t blob_flags;
	uint32_t bo_handle;
	uint32_t res_handle;
	uint64_t size;
	uint32_t pad;
	uint32_t cmd_size;
	uint64_t cmd;
	uint64_t blob_id;
};

struct drm_virtgpu_context_set_param {
	uint64_t param;
	uint64_t value;
};

struct drm_virtgpu_context_init {
	uint32_t num_params;
	uint32_t pad;
	uint64_t ctx_set_params;
};

#endif