af36ae12b0
fix(mremap): fix referencing
...
Before it was first add_ref'ed by `borrow_frame_enforce_rw_allocated`,
manually and then by `allocated_shared_one_page`.
Now it is only done by `borrow_frame_enforce_rw_allocated` and does not
get unref-ed as take() is called on the returned `RaiiFrame`.
Now the page is manually mapped and an `Allocated` type grant is
constructed (synonymous to `MAP_PRIVATE`). Before by using `allocated_shared_one_page`
an `AllocatedShared` provided grant was constructed (synonymous to
`MAP_SHARED`), which was wrong as the TCB would've not got CoW-ed
after fork(), making the Tcb malformed.
Signed-off-by: Anhad Singh <andypython@protonmail.com >
2024-12-11 16:37:01 +11:00
08231eb4df
feat(mremap): KEEP_OLD
...
Signed-off-by: Anhad Singh <andypython@protonmail.com >
Co-authored-by: @4lDO2
2024-12-11 16:08:08 +11:00
7af6dd1f88
Restore riscv,plic0 compatible check
2024-11-07 05:09:24 +03:00
9fe8f759af
Fix formatting and a warning
2024-11-06 12:13:13 +03:00
ee89d02282
Change PLIC compatible string from riscv,plic0 to sifive,plic-1.0.0
...
Former one is deprecated and apparently only used by QEMU. Latter is used by QEMU as well as others.
2024-11-06 12:09:36 +03:00
99fbdf426c
Fix assumption that CPU ID must equal APIC ID
2024-11-04 14:46:46 -07:00
7b1d135057
Use redoxer for CI jobs
2024-11-01 06:51:13 +03:00
4db9673e2a
Support SPCR and clean up device memory allocation
2024-10-31 10:53:58 -06:00
e19c1404f7
chore: enrich context/switch
...
* Add documentation and more code comments to `src/context/switch.rs`
* Eliminate a `context.wake.expect(...)` where `context.wake.is_some()`
* Eliminate a TODO item about updating contexts' timestamps in `switch_to`
* Eliminate a dangling `else { continue }` at the end of the loop that iterates
on contexts
2024-10-31 10:22:21 +00:00
df9db9291a
Fix AP CPU ID on newer Intel CPUs
2024-10-30 21:09:06 -06:00
9b6d1549b5
Support GTDT for aarch64
2024-10-30 18:17:11 -06:00
34a6a441f1
Initial aarch64 ACPI support
2024-10-30 16:16:24 -06:00
b221bb6c51
Make it possible to boot aarch64 with invalid DTB
2024-10-30 12:34:50 -06:00
4dd6a26742
Make it possible to compile acpi system on any arch
2024-10-30 11:43:21 -06:00
939c9567ee
Support 16550 uarts for aarch64 debug output
2024-10-29 14:06:00 -06:00
161e578f29
Use null driver for unknown IRQ controllers on aarch64
2024-10-29 08:01:38 -06:00
380532aea5
Improve reliability of aarch64 startup code
2024-10-29 08:00:57 -06:00
15b0133b7b
Add arm,gic-400 support to GIC driver
2024-10-29 08:00:17 -06:00
e4e55103ad
Remove old aarch64 asm code
2024-10-29 07:59:12 -06:00
ea0356b26a
Address minor warts
...
* Mention the need to have `nasm` available on the PATH in the README
* Replace the deprecated `hide_parse_errors` by `show_parse_errors` in `rustfmt.toml`
* Mark unused variables in `src/scheme/proc.rs`
2024-10-27 18:14:12 -03:00
505425bec9
Expose riscv64/aarch64 legacy irqs (requiring remapping) to the irq scheme
2024-10-22 20:26:40 +03:00
cba02a26fa
Rework irqchip to support risc-v irqs, and add risc-v irq chips handling
2024-10-22 19:16:21 +03:00
906259c024
Pull irqchip from aarch64 code into more generic place
2024-10-21 19:56:32 +03:00
1921c6814b
Initial RISC-V implementation
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Has no IRQ handling yet
2024-10-20 16:24:21 +03:00
db32f5f7a3
Move some conditionally compiled code from common files into arch-gated files
2024-10-19 21:59:14 +03:00
55041e2eeb
Use a custom config flag to conditionally compile DTB-specific areas
...
Would be great if we could use a feature instead, but Cargo can't do target-specific defaults features
2024-10-19 21:03:43 +03:00
0a6a90415a
Refactor initial memory paging
2024-10-19 08:44:46 +03:00
3fbd52a212
Made a change in context to the way arrays are resized. Slight change to the logic but resize_with should be slightly more efficient
2024-10-15 21:24:32 +11:00
865122e92f
Fix serial console login
2024-10-10 18:45:14 +00:00
8d4ee26ff1
Fix profiling && + toggle support via debug scheme.
2024-10-07 10:20:51 +02:00
ad16b747ea
Restrict auto-fcntl to non-v2 schemes.
2024-09-27 21:36:22 +02:00
fc5d246b30
remove wrapper functions
2024-09-26 22:34:55 +00:00
14eb140f7a
Refactor panic stack walking
2024-09-26 19:22:21 +03:00
755694494b
Factor KernelMapper out of arch
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Same implementation on all the platforms. Also remove mutable Deref as it allowed circumventing RO check
2024-09-25 21:51:39 +03:00
539dc5a24e
Remove SYS_UMASK.
2024-09-25 19:55:39 +02:00
d08861e586
Upgrade fdt library to the very latest
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The new helpers remove a lot of boilerplace. Unfortunately some rough edges still remain (in particular issue gh#12 which renders interrupts() helper useless)
2024-09-25 06:51:02 +03:00
71538efc06
Allow thread exit to optionally deallocate stack.
2024-09-24 19:18:23 +02:00
9a0192fc94
Prevent duplicate idempotent signals.
2024-09-24 19:18:23 +02:00
fcb2e2be3a
Pass si_uid and si_pid to kill signals.
2024-09-24 19:18:23 +02:00
7def7ce6e3
Extend size of sig{en,de}queue payload.
2024-09-24 19:18:22 +02:00
54b1fbe453
Implement queued signals.
...
This currently needs to be done in the kernel for synchronization
reasons, but it's possible all delivery parts can later be moved to
userspace.
2024-09-24 19:18:22 +02:00
6d9cf30445
WIP: realtime signals
2024-09-24 19:18:20 +02:00
dbbbfcf48a
Update RMM
2024-09-24 19:23:08 +03:00
960e79b107
Treat broken pipes as IO-capable in fevent.
2024-09-19 10:41:40 +02:00
ef499f81fc
Support compiling for host, allowing unit tests.
2024-09-17 19:24:23 +02:00
a0d0eac8aa
Optimally divide responsibility for borrow free.
...
This appears to slightly improve performance.
2024-09-14 10:49:40 +02:00
031fdea089
Discard empty names in root scheme getdents.
2024-09-13 15:26:24 +02:00
e3e05ebca8
Fix root scheme order by using indexmap (tmp).
2024-09-11 22:09:29 +02:00
97f60de4ef
WIP: Add getdents opaque_id
2024-09-11 22:09:29 +02:00
339271b4d7
Add getdents syscall, and switch schemes to it.
2024-09-11 22:09:26 +02:00
Anhad Singh