ee1260363c
Fix many clippy lints
2026-04-08 19:40:41 +01:00
b7456d5bcc
Avoid PHYS_OFFSET in dtb/serial.rs
2026-04-04 21:53:34 +02:00
d029ccfe20
Deduplicate a bunch of serial port initialization between arm64 and riscv
2026-04-04 16:36:30 +02:00
bbb9d98570
Unconditionally compile part of the DTB code
2026-04-04 14:01:19 +02:00
3b1fd27431
Remove byteorder dependency
2025-10-26 12:43:08 -06:00
6ce2101cf4
Do not mark soc ranges as device memory
2025-09-23 10:31:34 -06:00
5dc6f7c3ba
lock ordering
2025-09-22 07:48:48 -06:00
eb69d37323
Apply 1 suggestion(s) to 1 file(s)
...
Co-authored-by: bjorn3 <4397-bjorn3@users.noreply.gitlab.redox-os.org >
2025-09-19 06:43:19 -06:00
0022bd448c
dtb: remove allocation for in-memory DTB
...
Replaces the `Once<Vec<u8>>` with `Once<&'static [u8]>` to avoid an
unnecessary allocation.
Adds some basic documentation.
Signed-off-by: Elle Rhumsaa <elle@weathered-steel.dev >
2025-09-19 06:43:19 -06:00
5a6117b5ae
Replace the log crate with a custom logging system
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This avoids the need to explicitly set a logger early during boot, which
reduces the amount of moving parts that could go wrong slightly. And it
cuts the kernel image size by 13kb.
2025-09-13 18:55:16 +02:00
35a0f2d440
Remove usage of array_chunks
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It has been removed in newer rustc versions
2025-09-10 18:00:02 +02:00
cea93f7647
cargo fix --edition & rustfmt
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Or to be precise:
RUST_TARGET_PATH=$(pwd)/targets cargo fix --edition \
--target targets/x86_64-unknown-kernel.json \
--target targets/i686-unknown-kernel.json \
--target targets/aarch64-unknown-kernel.json \
--target targets/riscv64-unknown-kernel.json \
-Zbuild-std=core,alloc --allow-dirty --bin kernel
cargo fmt
2025-09-10 16:44:36 +02:00
172a0ffd02
remove dtb unwraps
2025-09-07 22:53:39 -07:00
7db6667e6b
Better parsing of IRQ specifications in DTB
...
Fixes Raspberry 3B+ DTB parsing (as generated by Qemu)
2024-12-18 21:11:46 +03:00
7f38f51b20
dtb: Apply bus mappings
2024-12-18 21:11:46 +03:00
34a6a441f1
Initial aarch64 ACPI support
2024-10-30 16:16:24 -06:00
939c9567ee
Support 16550 uarts for aarch64 debug output
2024-10-29 14:06:00 -06:00
380532aea5
Improve reliability of aarch64 startup code
2024-10-29 08:00:57 -06:00
505425bec9
Expose riscv64/aarch64 legacy irqs (requiring remapping) to the irq scheme
2024-10-22 20:26:40 +03:00
cba02a26fa
Rework irqchip to support risc-v irqs, and add risc-v irq chips handling
2024-10-22 19:16:21 +03:00
906259c024
Pull irqchip from aarch64 code into more generic place
2024-10-21 19:56:32 +03:00
1921c6814b
Initial RISC-V implementation
...
Has no IRQ handling yet
2024-10-20 16:24:21 +03:00
0a6a90415a
Refactor initial memory paging
2024-10-19 08:44:46 +03:00
eb0d48ac81
aarch64: add dtb scheme
2023-09-18 20:45:23 +00:00
Speedy_Lex