From f00a049439483e6b87189ec500587646a70c032b Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Sat, 22 Feb 2020 20:10:43 -0700
Subject: [PATCH] Enable ahcid interrupts

---
 ahcid/src/ahci/disk_ata.rs | 2 +-
 ahcid/src/ahci/hba.rs      | 2 +-
 ahcid/src/scheme.rs        | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/ahcid/src/ahci/disk_ata.rs b/ahcid/src/ahci/disk_ata.rs
index 03d51d838f..30c4de7e9d 100644
--- a/ahcid/src/ahci/disk_ata.rs
+++ b/ahcid/src/ahci/disk_ata.rs
@@ -68,7 +68,7 @@ impl DiskATA {
         };
 
         //TODO: Go back to interrupt magic
-        let use_interrupts = false;
+        let use_interrupts = true;
         loop {
             let mut request = match self.request_opt.take() {
                 Some(request) => if address == request.address && total_sectors == request.total_sectors {
diff --git a/ahcid/src/ahci/hba.rs b/ahcid/src/ahci/hba.rs
index 86764ec767..d0318e54cc 100644
--- a/ahcid/src/ahci/hba.rs
+++ b/ahcid/src/ahci/hba.rs
@@ -116,7 +116,7 @@ impl HbaPort {
         self.fb[1].write((fb.physical() >> 32) as u32);
         let is = self.is.read();
         self.is.write(is);
-        self.ie.write(0 /*TODO: Enable interrupts: 0b10111*/);
+        self.ie.write(0b10111);
         let serr = self.serr.read();
         self.serr.write(serr);
 
diff --git a/ahcid/src/scheme.rs b/ahcid/src/scheme.rs
index 48d0721d61..0d1f3d9e00 100644
--- a/ahcid/src/scheme.rs
+++ b/ahcid/src/scheme.rs
@@ -136,6 +136,7 @@ impl DiskScheme {
                 if pi_is & 1 << i > 0 {
                     let port = &mut self.hba_mem.ports[i];
                     let is = port.is.read();
+                    //TODO: Handle requests for only this port here
                     port.is.write(is);
                 }
             }