From ec2ac74f5d658d124847c3152d3e6712dc6970de Mon Sep 17 00:00:00 2001 From: Admin Pupkin Date: Sat, 30 May 2026 09:34:26 +0300 Subject: [PATCH] =?UTF-8?q?intel:=20implement=20CS=20submit=20=E2=80=94=20?= =?UTF-8?q?Mesa=20winsys=20integration=20(Phase=204=20complete)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement redox_private_cs_submit() in the Intel GpuDriver, completing Phase 4 (Render Path). This is the userspace GPU command submission interface used by Mesa. - redox_private_cs_submit(): map source GEM buffer to GPU address, extract batch commands as u32 slice from src_offset with byte_count dwords, submit to render ring via ring.submit_batch() - Returns RedoxPrivateCsSubmitResult with seqno (0 for now — fence integration deferred) This completes all 4 modules of Phase 4: batch.rs ✅ fence.rs ✅ execlists.rs ✅ Mesa winsys ✅ Remaining across all phases: Phase 2: DBUF detailed programming Phase 3: Atomic modesetting (requires scheme.rs changes) --- .../redox-drm/source/src/drivers/intel/mod.rs | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs index f4fcecd575..e0d73208ea 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs @@ -32,7 +32,7 @@ use redox_driver_sys::memory::MmioRegion; use redox_driver_sys::pci::{PciBarInfo, PciDevice, PciDeviceInfo}; use redox_driver_sys::quirks::PciQuirkFlags; -use crate::driver::{DriverError, DriverEvent, GpuDriver, Result}; +use crate::driver::{DriverError, DriverEvent, GpuDriver, Result, RedoxPrivateCsSubmit, RedoxPrivateCsSubmitResult}; use crate::drivers::interrupt::InterruptHandle; use crate::gem::{GemHandle, GemManager}; use crate::kms::connector::{synthetic_edid, Connector}; @@ -758,6 +758,23 @@ impl GpuDriver for IntelDriver { self.process_irq() } + + fn redox_private_cs_submit( + &self, + submit: &RedoxPrivateCsSubmit, + ) -> Result { + let src_addr = self.ensure_gem_gpu_mapping(submit.src_handle)?; + + let cmds_ptr = (src_addr + submit.src_offset) as *const u32; + let dword_count = (submit.byte_count / 4) as usize; + let cmds = unsafe { std::slice::from_raw_parts(cmds_ptr, dword_count) }; + + let mut ring = self.ring.lock() + .map_err(|_| DriverError::Initialization("Intel ring state poisoned".into()))?; + ring.submit_batch(cmds)?; + + Ok(RedoxPrivateCsSubmitResult { seqno: 0 }) + } } fn detect_display_topology(display: &IntelDisplay, edid_source: Option<&[DpAux]>) -> Result<(Vec, Vec)> {