diff --git a/src/acpi/spcr.rs b/src/acpi/spcr.rs index a611480002..647e1ec00c 100644 --- a/src/acpi/spcr.rs +++ b/src/acpi/spcr.rs @@ -2,8 +2,8 @@ use core::mem; use super::{find_sdt, sdt::Sdt, GenericAddressStructure}; use crate::{ - device::serial::{SerialKind, COM1}, - devices::uart_pl011, + device::serial::COM1, + devices::{serial::SerialKind, uart_pl011}, log::LOG, memory::{map_device_memory, PhysicalAddress, PAGE_SIZE}, }; diff --git a/src/arch/aarch64/debug.rs b/src/arch/aarch64/debug.rs index fc2f16dae5..ad591311b9 100644 --- a/src/arch/aarch64/debug.rs +++ b/src/arch/aarch64/debug.rs @@ -7,7 +7,9 @@ use crate::{ }; #[cfg(feature = "serial_debug")] -use super::device::serial::{SerialKind, COM1}; +use super::device::serial::COM1; +#[cfg(feature = "serial_debug")] +use crate::devices::serial::SerialKind; pub struct Writer<'a> { log: MutexGuard<'a, Option>, diff --git a/src/arch/aarch64/device/serial.rs b/src/arch/aarch64/device/serial.rs index 71d683c2a8..5e4121d687 100644 --- a/src/arch/aarch64/device/serial.rs +++ b/src/arch/aarch64/device/serial.rs @@ -3,62 +3,17 @@ use spin::Mutex; use crate::{ arch::device::irqchip::ic_for_chip, - devices::{uart_16550, uart_pl011}, + devices::{serial::SerialKind, uart_16550, uart_pl011}, dtb::{ diag_uart_range, get_interrupt, irqchip::{register_irq, InterruptHandler, IRQ_CHIP}, }, interrupt::irq::trigger, - scheme::debug::{debug_input, debug_notify}, }; use fdt::Fdt; use log::{error, info}; use syscall::Mmio; -pub enum SerialKind { - Ns16550u8(&'static mut uart_16550::SerialPort>), - Ns16550u32(&'static mut uart_16550::SerialPort>), - Pl011(uart_pl011::SerialPort), -} - -impl SerialKind { - pub fn enable_irq(&mut self) { - //TODO: implement for NS16550 - match self { - Self::Ns16550u8(_) => {} - Self::Ns16550u32(_) => {} - Self::Pl011(inner) => inner.enable_irq(), - } - } - - pub fn receive(&mut self) { - //TODO: make PL011 receive work the same way as NS16550 - match self { - Self::Ns16550u8(inner) => { - while let Some(c) = inner.receive() { - debug_input(c); - } - debug_notify(); - } - Self::Ns16550u32(inner) => { - while let Some(c) = inner.receive() { - debug_input(c); - } - debug_notify(); - } - Self::Pl011(inner) => inner.receive(), - } - } - - pub fn write(&mut self, buf: &[u8]) { - match self { - Self::Ns16550u8(inner) => inner.write(buf), - Self::Ns16550u32(inner) => inner.write(buf), - Self::Pl011(inner) => inner.write(buf), - } - } -} - pub static COM1: Mutex> = Mutex::new(None); pub struct Com1Irq {} diff --git a/src/arch/riscv64/debug.rs b/src/arch/riscv64/debug.rs index 6c0bd983f0..3a89bfd70b 100644 --- a/src/arch/riscv64/debug.rs +++ b/src/arch/riscv64/debug.rs @@ -2,7 +2,9 @@ use core::fmt; use spin::MutexGuard; #[cfg(feature = "serial_debug")] -use super::device::serial::{SerialPort, COM1}; +use super::device::serial::COM1; +#[cfg(feature = "serial_debug")] +use crate::devices::serial::SerialKind; use crate::{ devices::graphical_debug::{DebugDisplay, DEBUG_DISPLAY}, log::{Log, LOG}, @@ -11,7 +13,7 @@ use crate::{ pub struct Writer<'a> { log: MutexGuard<'a, Option>, #[cfg(feature = "serial_debug")] - serial: MutexGuard<'a, Option>, + serial: MutexGuard<'a, Option>, display: MutexGuard<'a, Option>, } diff --git a/src/arch/riscv64/device/serial.rs b/src/arch/riscv64/device/serial.rs index 53aef975af..2528466567 100644 --- a/src/arch/riscv64/device/serial.rs +++ b/src/arch/riscv64/device/serial.rs @@ -5,50 +5,15 @@ use spin::Mutex; use syscall::Mmio; use crate::{ - devices::uart_16550, + devices::{serial::SerialKind, uart_16550}, dtb::{ diag_uart_range, get_interrupt, interrupt_parent, irqchip::{register_irq, InterruptHandler, IRQ_CHIP}, }, - scheme::{ - debug::{debug_input, debug_notify}, - irq::irq_trigger, - }, + scheme::irq::irq_trigger, }; -pub enum SerialPort { - Ns16550u8(&'static mut uart_16550::SerialPort>), - Ns16550u32(&'static mut uart_16550::SerialPort>), -} - -impl SerialPort { - pub fn receive(&mut self) { - //TODO: make PL011 receive work the same way as NS16550 - match self { - Self::Ns16550u8(inner) => { - while let Some(c) = inner.receive() { - debug_input(c); - } - debug_notify(); - } - Self::Ns16550u32(inner) => { - while let Some(c) = inner.receive() { - debug_input(c); - } - debug_notify(); - } - } - } - - pub fn write(&mut self, buf: &[u8]) { - match self { - Self::Ns16550u8(inner) => inner.write(buf), - Self::Ns16550u32(inner) => inner.write(buf), - } - } -} - -pub static COM1: Mutex> = Mutex::new(None); +pub static COM1: Mutex> = Mutex::new(None); pub struct Com1Irq {} @@ -79,14 +44,14 @@ pub unsafe fn init_early(dtb: &Fdt) { if !skip_init { serial_port.init(); } - Some(SerialPort::Ns16550u8(serial_port)) + Some(SerialKind::Ns16550u8(serial_port)) } else if compatible.contains("snps,dw-apb-uart") { //TODO: get actual register size from device tree let serial_port = uart_16550::SerialPort::>::new(virt); if !skip_init { serial_port.init(); } - Some(SerialPort::Ns16550u32(serial_port)) + Some(SerialKind::Ns16550u32(serial_port)) } else { None }; diff --git a/src/devices/mod.rs b/src/devices/mod.rs index 5b12fbed5f..44430d9df6 100644 --- a/src/devices/mod.rs +++ b/src/devices/mod.rs @@ -1,3 +1,4 @@ pub mod graphical_debug; +pub mod serial; pub mod uart_16550; pub mod uart_pl011; diff --git a/src/devices/serial.rs b/src/devices/serial.rs new file mode 100644 index 0000000000..8f14adf083 --- /dev/null +++ b/src/devices/serial.rs @@ -0,0 +1,66 @@ +use syscall::Mmio; +#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] +use syscall::Pio; + +use crate::{ + devices::{uart_16550, uart_pl011}, + scheme::debug::{debug_input, debug_notify}, +}; + +#[allow(dead_code)] +pub enum SerialKind { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + Ns16550Pio(uart_16550::SerialPort>), + Ns16550u8(&'static mut uart_16550::SerialPort>), + Ns16550u32(&'static mut uart_16550::SerialPort>), + Pl011(uart_pl011::SerialPort), +} + +impl SerialKind { + pub fn enable_irq(&mut self) { + //TODO: implement for NS16550 + match self { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + Self::Ns16550Pio(_) => {} + Self::Ns16550u8(_) => {} + Self::Ns16550u32(_) => {} + Self::Pl011(inner) => inner.enable_irq(), + } + } + + pub fn receive(&mut self) { + //TODO: make PL011 receive work the same way as NS16550 + match self { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + Self::Ns16550Pio(inner) => { + while let Some(c) = inner.receive() { + debug_input(c); + } + debug_notify(); + } + Self::Ns16550u8(inner) => { + while let Some(c) = inner.receive() { + debug_input(c); + } + debug_notify(); + } + Self::Ns16550u32(inner) => { + while let Some(c) = inner.receive() { + debug_input(c); + } + debug_notify(); + } + Self::Pl011(inner) => inner.receive(), + } + } + + pub fn write(&mut self, buf: &[u8]) { + match self { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + Self::Ns16550Pio(inner) => inner.write(buf), + Self::Ns16550u8(inner) => inner.write(buf), + Self::Ns16550u32(inner) => inner.write(buf), + Self::Pl011(inner) => inner.write(buf), + } + } +}