From ea1c855cdcde3b44ff9f2bfefde5726f64a3b658 Mon Sep 17 00:00:00 2001
From: Anhad Singh <andypython@protonmail.com>
Date: Mon, 26 Jun 2023 09:37:57 +1000
Subject: [PATCH] virtiod: make use of the `int_roundings` feature

* Removes the need to define `round_up` and `div_round_up`

Signed-off-by: Anhad Singh <andypython@protonmail.com>
---
 virtiod/src/lib.rs       |  2 ++
 virtiod/src/main.rs      | 15 ++-------------
 virtiod/src/transport.rs |  6 +++---
 virtiod/src/utils.rs     |  7 -------
 4 files changed, 7 insertions(+), 23 deletions(-)

diff --git a/virtiod/src/lib.rs b/virtiod/src/lib.rs
index 64fff84bb7..04f8e74492 100644
--- a/virtiod/src/lib.rs
+++ b/virtiod/src/lib.rs
@@ -1,5 +1,7 @@
 //! https://docs.oasis-open.org/virtio/virtio/v1.1/virtio-v1.1.html
 
+#![feature(int_roundings)]
+
 use static_assertions::const_assert_eq;
 
 pub mod transport;
diff --git a/virtiod/src/main.rs b/virtiod/src/main.rs
index c965301fc1..11e1c38543 100644
--- a/virtiod/src/main.rs
+++ b/virtiod/src/main.rs
@@ -1,11 +1,11 @@
 #![deny(trivial_numeric_casts, unused_allocation)]
+#![feature(int_roundings)]
 
 use core::ptr::NonNull;
 
 use std::fs::File;
 use std::io;
 use std::io::{Read, Write};
-use std::ops::{Add, Div, Rem};
 use std::os::fd::{AsRawFd, FromRawFd, RawFd};
 
 use static_assertions::const_assert_eq;
@@ -26,17 +26,6 @@ use virtiod::utils::VolatileCell;
 
 mod scheme;
 
-fn div_round_up<T>(a: T, b: T) -> T
-where
-    T: Add<Output = T> + Div<Output = T> + Rem<Output = T> + PartialEq + From<u8> + Copy,
-{
-    if a % b != T::from(0u8) {
-        a / b + T::from(1u8)
-    } else {
-        a / b
-    }
-}
-
 pub fn main() -> anyhow::Result<()> {
     #[cfg(target_os = "redox")]
     setup_logging();
@@ -118,7 +107,7 @@ fn enable_msix(pcid_handle: &mut PcidServerHandle) -> anyhow::Result<File> {
     let table_size = capability.table_size();
     let table_base = capability.table_base_pointer(pci_config.func.bars);
     let table_min_length = table_size * 16;
-    let pba_min_length = div_round_up(table_size, 8);
+    let pba_min_length = table_size.div_ceil(8);
 
     let pba_base = capability.pba_base_pointer(pci_config.func.bars);
 
diff --git a/virtiod/src/transport.rs b/virtiod/src/transport.rs
index 21302b9d53..4ee9753f26 100644
--- a/virtiod/src/transport.rs
+++ b/virtiod/src/transport.rs
@@ -1,4 +1,4 @@
-use crate::utils::{align, round_up};
+use crate::utils::align;
 use crate::*;
 
 use pcid_interface::PciHeader;
@@ -169,8 +169,8 @@ pub struct Available<'a> {
 impl<'a> Available<'a> {
     pub fn new(queue_size: usize) -> anyhow::Result<Self> {
         let (_, size, _) = queue_part_sizes(queue_size);
+        let size = size.next_multiple_of(syscall::PAGE_SIZE); // align to page size
 
-        let size = round_up(size);
         let addr = unsafe { syscall::physalloc(size) }.map_err(Error::SyscallError)?;
         let virt =
             unsafe { syscall::physmap(addr, size, PHYSMAP_WRITE) }.map_err(Error::SyscallError)?;
@@ -231,8 +231,8 @@ pub struct Used<'a> {
 impl<'a> Used<'a> {
     pub fn new(queue_size: usize) -> anyhow::Result<Self> {
         let (_, _, size) = queue_part_sizes(queue_size);
+        let size = size.next_multiple_of(syscall::PAGE_SIZE); // align to page size
 
-        let size = round_up(size);
         let addr = unsafe { syscall::physalloc(size) }.map_err(Error::SyscallError)?;
         let virt =
             unsafe { syscall::physmap(addr, size, PHYSMAP_WRITE) }.map_err(Error::SyscallError)?;
diff --git a/virtiod/src/utils.rs b/virtiod/src/utils.rs
index 99efef87d6..be9ccbe876 100644
--- a/virtiod/src/utils.rs
+++ b/virtiod/src/utils.rs
@@ -63,10 +63,3 @@ impl<T> IncompleteArrayField<T> {
 pub const fn align(val: usize, align: usize) -> usize {
     (val + align) & !align
 }
-
-// From the syscall crate; the function is private.
-//
-// TODO(andypython): make it public
-pub const fn round_up(x: usize) -> usize {
-    (x + syscall::PAGE_SIZE - 1) / syscall::PAGE_SIZE * syscall::PAGE_SIZE
-}