Red Bear OS base baseline from 0.1.0 pre-patched archive
This commit is contained in:
Red Bear OS
@@ -0,0 +1,20 @@
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[package]
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name = "rtl8168d"
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description = "Realtek 8168 ethernet driver"
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version = "0.1.0"
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edition = "2018"
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[dependencies]
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bitflags.workspace = true
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libredox.workspace = true
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log.workspace = true
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redox_event.workspace = true
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redox_syscall.workspace = true
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common = { path = "../../common" }
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daemon = { path = "../../../daemon" }
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driver-network = { path = "../driver-network" }
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pcid = { path = "../../pcid" }
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[lints]
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workspace = true
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@@ -0,0 +1,5 @@
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[[drivers]]
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name = "RTL8168 NIC"
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class = 0x02
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ids = { 0x10ec = [0x8168, 0x8169] }
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command = ["rtl8168d"]
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@@ -0,0 +1,345 @@
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use std::convert::TryInto;
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use std::mem;
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use common::dma::Dma;
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use common::io::{Io, Mmio, ReadOnly};
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use common::timeout::Timeout;
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use driver_network::NetworkAdapter;
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use syscall::error::{Error, Result, EIO, EMSGSIZE};
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#[repr(C, packed)]
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struct Regs {
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mac: [Mmio<u32>; 2],
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_mar: [Mmio<u32>; 2],
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_dtccr: [Mmio<u32>; 2],
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_rsv0: [Mmio<u32>; 2],
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tnpds: [Mmio<u32>; 2],
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thpds: [Mmio<u32>; 2],
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_rsv1: [Mmio<u8>; 7],
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cmd: Mmio<u8>,
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tppoll: Mmio<u8>,
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_rsv2: [Mmio<u8>; 3],
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imr: Mmio<u16>,
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isr: Mmio<u16>,
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tcr: Mmio<u32>,
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rcr: Mmio<u32>,
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_tctr: Mmio<u32>,
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_rsv3: Mmio<u32>,
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cmd_9346: Mmio<u8>,
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_config: [Mmio<u8>; 6],
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_rsv4: Mmio<u8>,
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timer_int: Mmio<u32>,
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_rsv5: Mmio<u32>,
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_phys_ar: Mmio<u32>,
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_rsv6: [Mmio<u32>; 2],
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phys_sts: ReadOnly<Mmio<u8>>,
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_rsv7: [Mmio<u8>; 23],
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_wakeup: [Mmio<u32>; 16],
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_crc: [Mmio<u16>; 5],
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_rsv8: [Mmio<u8>; 12],
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rms: Mmio<u16>,
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_rsv9: Mmio<u32>,
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_c_plus_cr: Mmio<u16>,
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_rsv10: Mmio<u16>,
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rdsar: [Mmio<u32>; 2],
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mtps: Mmio<u8>,
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_rsv11: [Mmio<u8>; 19],
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}
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const OWN: u32 = 1 << 31;
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const EOR: u32 = 1 << 30;
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const FS: u32 = 1 << 29;
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const LS: u32 = 1 << 28;
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#[repr(C, packed)]
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struct Rd {
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ctrl: Mmio<u32>,
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_vlan: Mmio<u32>,
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buffer_low: Mmio<u32>,
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buffer_high: Mmio<u32>,
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}
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#[repr(C, packed)]
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struct Td {
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ctrl: Mmio<u32>,
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_vlan: Mmio<u32>,
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buffer_low: Mmio<u32>,
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buffer_high: Mmio<u32>,
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}
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pub struct Rtl8168 {
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regs: &'static mut Regs,
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receive_buffer: [Dma<[Mmio<u8>; 0x1FF8]>; 64],
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receive_ring: Dma<[Rd; 64]>,
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receive_i: usize,
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transmit_buffer: [Dma<[Mmio<u8>; 7552]>; 16],
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transmit_ring: Dma<[Td; 16]>,
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transmit_i: usize,
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transmit_buffer_h: [Dma<[Mmio<u8>; 7552]>; 1],
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transmit_ring_h: Dma<[Td; 1]>,
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mac_address: [u8; 6],
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}
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impl NetworkAdapter for Rtl8168 {
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fn mac_address(&mut self) -> [u8; 6] {
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self.mac_address
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}
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fn available_for_read(&mut self) -> usize {
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self.next_read()
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}
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fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
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if self.receive_i >= self.receive_ring.len() {
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self.receive_i = 0;
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}
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let rd = &mut self.receive_ring[self.receive_i];
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if !rd.ctrl.readf(OWN) {
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let rd_len = rd.ctrl.read() & 0x3FFF;
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let data = &self.receive_buffer[self.receive_i];
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let mut i = 0;
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while i < buf.len() && i < rd_len as usize {
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buf[i] = data[i].read();
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i += 1;
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}
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let eor = rd.ctrl.read() & EOR;
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rd.ctrl.write(OWN | eor | data.len() as u32);
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self.receive_i += 1;
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Ok(Some(i))
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} else {
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Ok(None)
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}
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}
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fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
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loop {
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if self.transmit_i >= self.transmit_ring.len() {
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self.transmit_i = 0;
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}
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let td = &mut self.transmit_ring[self.transmit_i];
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if !td.ctrl.readf(OWN) {
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let data = &mut self.transmit_buffer[self.transmit_i];
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if buf.len() > data.len() {
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return Err(Error::new(EMSGSIZE));
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}
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let mut i = 0;
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while i < buf.len() && i < data.len() {
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data[i].write(buf[i]);
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i += 1;
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}
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let eor = td.ctrl.read() & EOR;
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td.ctrl.write(OWN | eor | FS | LS | i as u32);
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self.regs.tppoll.writef(1 << 6, true); //Notify of normal priority packet
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while self.regs.tppoll.readf(1 << 6) {
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std::hint::spin_loop();
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}
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self.transmit_i += 1;
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return Ok(i);
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}
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std::hint::spin_loop();
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}
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}
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}
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impl Rtl8168 {
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pub unsafe fn new(base: usize) -> Result<Self> {
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assert_eq!(mem::size_of::<Regs>(), 256);
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let regs = &mut *(base as *mut Regs);
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assert_eq!(®s.tnpds as *const _ as usize - base, 0x20);
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assert_eq!(®s.cmd as *const _ as usize - base, 0x37);
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assert_eq!(®s.tcr as *const _ as usize - base, 0x40);
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assert_eq!(®s.rcr as *const _ as usize - base, 0x44);
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assert_eq!(®s.cmd_9346 as *const _ as usize - base, 0x50);
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assert_eq!(®s.phys_sts as *const _ as usize - base, 0x6C);
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assert_eq!(®s.rms as *const _ as usize - base, 0xDA);
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assert_eq!(®s.rdsar as *const _ as usize - base, 0xE4);
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assert_eq!(®s.mtps as *const _ as usize - base, 0xEC);
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let mut module = Rtl8168 {
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regs,
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receive_buffer: (0..64)
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.map(|_| Ok(Dma::zeroed()?.assume_init()))
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.collect::<Result<Vec<_>>>()?
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.try_into()
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.unwrap_or_else(|_| unreachable!()),
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receive_ring: Dma::zeroed()?.assume_init(),
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receive_i: 0,
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transmit_buffer: (0..16)
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.map(|_| Ok(Dma::zeroed()?.assume_init()))
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.collect::<Result<Vec<_>>>()?
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.try_into()
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.unwrap_or_else(|_| unreachable!()),
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transmit_ring: Dma::zeroed()?.assume_init(),
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transmit_i: 0,
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transmit_buffer_h: [Dma::zeroed()?.assume_init()],
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transmit_ring_h: Dma::zeroed()?.assume_init(),
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mac_address: [0; 6],
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};
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module.init()?;
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Ok(module)
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}
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pub unsafe fn irq(&mut self) -> bool {
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// Read and then clear the ISR
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let isr = self.regs.isr.read();
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self.regs.isr.write(isr);
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let imr = self.regs.imr.read();
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(isr & imr) != 0
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}
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pub fn next_read(&self) -> usize {
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let mut receive_i = self.receive_i;
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if receive_i >= self.receive_ring.len() {
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receive_i = 0;
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}
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let rd = &self.receive_ring[receive_i];
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if !rd.ctrl.readf(OWN) {
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(rd.ctrl.read() & 0x3FFF) as usize
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} else {
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0
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}
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}
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pub unsafe fn init(&mut self) -> Result<()> {
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let mac_low = self.regs.mac[0].read();
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let mac_high = self.regs.mac[1].read();
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let mac = [
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mac_low as u8,
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(mac_low >> 8) as u8,
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(mac_low >> 16) as u8,
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(mac_low >> 24) as u8,
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mac_high as u8,
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(mac_high >> 8) as u8,
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];
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log::debug!(
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"MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
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mac[0],
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mac[1],
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mac[2],
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mac[3],
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mac[4],
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mac[5]
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);
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self.mac_address = mac;
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// Reset - this will disable tx and rx, reinitialize FIFOs, and set the system buffer pointer to the initial value
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{
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log::debug!("Reset");
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let timeout = Timeout::from_secs(1);
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self.regs.cmd.writef(1 << 4, true);
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while self.regs.cmd.readf(1 << 4) {
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timeout.run().map_err(|()| Error::new(EIO))?;
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}
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}
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// Set up rx buffers
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log::debug!("Receive buffers");
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for i in 0..self.receive_ring.len() {
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let rd = &mut self.receive_ring[i];
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let data = &mut self.receive_buffer[i];
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rd.buffer_low.write(data.physical() as u32);
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rd.buffer_high.write((data.physical() as u64 >> 32) as u32);
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rd.ctrl.write(OWN | data.len() as u32);
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}
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if let Some(rd) = self.receive_ring.last_mut() {
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rd.ctrl.writef(EOR, true);
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}
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// Set up normal priority tx buffers
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log::debug!("Transmit buffers (normal priority)");
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for i in 0..self.transmit_ring.len() {
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self.transmit_ring[i]
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.buffer_low
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.write(self.transmit_buffer[i].physical() as u32);
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self.transmit_ring[i]
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.buffer_high
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.write((self.transmit_buffer[i].physical() as u64 >> 32) as u32);
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}
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if let Some(td) = self.transmit_ring.last_mut() {
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td.ctrl.writef(EOR, true);
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}
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// Set up high priority tx buffers
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log::debug!("Transmit buffers (high priority)");
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for i in 0..self.transmit_ring_h.len() {
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self.transmit_ring_h[i]
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.buffer_low
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.write(self.transmit_buffer_h[i].physical() as u32);
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self.transmit_ring_h[i]
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.buffer_high
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.write((self.transmit_buffer_h[i].physical() as u64 >> 32) as u32);
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}
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if let Some(td) = self.transmit_ring_h.last_mut() {
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td.ctrl.writef(EOR, true);
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}
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log::debug!("Set config");
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// Unlock config
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self.regs.cmd_9346.write(1 << 7 | 1 << 6);
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// Enable rx (bit 3) and tx (bit 2)
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self.regs.cmd.writef(1 << 3 | 1 << 2, true);
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// Max RX packet size
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self.regs.rms.write(0x1FF8);
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// Max TX packet size
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self.regs.mtps.write(0x3B);
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// Set tx low priority buffer address
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self.regs.tnpds[0].write(self.transmit_ring.physical() as u32);
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self.regs.tnpds[1].write(((self.transmit_ring.physical() as u64) >> 32) as u32);
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// Set tx high priority buffer address
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self.regs.thpds[0].write(self.transmit_ring_h.physical() as u32);
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self.regs.thpds[1].write(((self.transmit_ring_h.physical() as u64) >> 32) as u32);
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// Set rx buffer address
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self.regs.rdsar[0].write(self.receive_ring.physical() as u32);
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self.regs.rdsar[1].write(((self.receive_ring.physical() as u64) >> 32) as u32);
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// Disable timer interrupt
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self.regs.timer_int.write(0);
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//Clear ISR
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let isr = self.regs.isr.read();
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self.regs.isr.write(isr);
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// Interrupt on tx error (bit 3), tx ok (bit 2), rx error(bit 1), and rx ok (bit 0)
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self.regs.imr.write(
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1 << 15 | 1 << 14 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1,
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);
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// Set TX config
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self.regs.tcr.write(0b11 << 24 | 0b111 << 8);
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// Set RX config - Accept broadcast (bit 3), multicast (bit 2), and unicast (bit 1)
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self.regs.rcr.write(0xE70E);
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// Lock config
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self.regs.cmd_9346.write(0);
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log::debug!("Complete!");
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Ok(())
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}
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}
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@@ -0,0 +1,115 @@
|
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use std::io::{Read, Write};
|
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use std::os::unix::io::AsRawFd;
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|
||||
use driver_network::NetworkScheme;
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use event::{user_data, EventQueue};
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use pcid_interface::irq_helpers::pci_allocate_interrupt_vector;
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use pcid_interface::PciFunctionHandle;
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pub mod device;
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use std::ops::{Add, Div, Rem};
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pub fn div_round_up<T>(a: T, b: T) -> T
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where
|
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T: Add<Output = T> + Div<Output = T> + Rem<Output = T> + PartialEq + From<u8> + Copy,
|
||||
{
|
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if a % b != T::from(0u8) {
|
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a / b + T::from(1u8)
|
||||
} else {
|
||||
a / b
|
||||
}
|
||||
}
|
||||
|
||||
fn map_bar(pcid_handle: &mut PciFunctionHandle) -> *mut u8 {
|
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let config = pcid_handle.config();
|
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|
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// RTL8168 uses BAR2, RTL8169 uses BAR1, search in that order
|
||||
for &barnum in &[2, 1] {
|
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match config.func.bars[usize::from(barnum)] {
|
||||
pcid_interface::PciBar::Memory32 { .. } | pcid_interface::PciBar::Memory64 { .. } => unsafe {
|
||||
return pcid_handle.map_bar(barnum).ptr.as_ptr();
|
||||
},
|
||||
other => log::warn!("BAR {} is {:?} instead of memory BAR", barnum, other),
|
||||
}
|
||||
}
|
||||
panic!("rtl8168d: failed to find BAR");
|
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}
|
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|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon);
|
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}
|
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|
||||
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
|
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let pci_config = pcid_handle.config();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_rtl8168");
|
||||
|
||||
common::setup_logging(
|
||||
"net",
|
||||
"pci",
|
||||
&name,
|
||||
common::output_level(),
|
||||
common::file_level(),
|
||||
);
|
||||
|
||||
log::info!("RTL8168 {}", pci_config.func.display());
|
||||
|
||||
let bar = map_bar(&mut pcid_handle);
|
||||
|
||||
let irq_file = pci_allocate_interrupt_vector(&mut pcid_handle, "rtl8168d");
|
||||
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || unsafe {
|
||||
device::Rtl8168::new(bar as usize).expect("rtl8168d: failed to allocate device")
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
user_data! {
|
||||
enum Source {
|
||||
Irq,
|
||||
Scheme,
|
||||
}
|
||||
}
|
||||
|
||||
let event_queue = EventQueue::<Source>::new().expect("rtl8168d: Could not create event queue.");
|
||||
event_queue
|
||||
.subscribe(
|
||||
irq_file.irq_handle().as_raw_fd() as usize,
|
||||
Source::Irq,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
event_queue
|
||||
.subscribe(
|
||||
scheme.event_handle().raw(),
|
||||
Source::Scheme,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
libredox::call::setrens(0, 0).expect("rtl8168d: failed to enter null namespace");
|
||||
|
||||
scheme.tick().unwrap();
|
||||
|
||||
for event in event_queue.map(|e| e.expect("rtl8168d: failed to get next event")) {
|
||||
match event.user_data {
|
||||
Source::Irq => {
|
||||
let mut irq = [0; 8];
|
||||
irq_file.irq_handle().read(&mut irq).unwrap();
|
||||
//TODO: This may be causing spurious interrupts
|
||||
if unsafe { scheme.adapter_mut().irq() } {
|
||||
irq_file.irq_handle().write(&mut irq).unwrap();
|
||||
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
Source::Scheme => {
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
unreachable!()
|
||||
}
|
||||
Reference in New Issue
Block a user