restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
@@ -0,0 +1,25 @@
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||||
/* SPDX-License-Identifier: GPL-2.0 */
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/* linux/spi/ad7877.h */
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/* Touchscreen characteristics vary between boards and models. The
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* platform_data for the device's "struct device" holds this information.
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*
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* It's OK if the min/max values are zero.
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*/
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struct ad7877_platform_data {
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u16 model; /* 7877 */
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u16 vref_delay_usecs; /* 0 for external vref; etc */
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u16 x_plate_ohms;
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u16 y_plate_ohms;
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u16 x_min, x_max;
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u16 y_min, y_max;
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u16 pressure_min, pressure_max;
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u8 stopacq_polarity; /* 1 = Active HIGH, 0 = Active LOW */
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u8 first_conversion_delay; /* 0 = 0.5us, 1 = 128us, 2 = 1ms, 3 = 8ms */
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u8 acquisition_time; /* 0 = 2us, 1 = 4us, 2 = 8us, 3 = 16us */
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u8 averaging; /* 0 = 1, 1 = 4, 2 = 8, 3 = 16 */
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u8 pen_down_acc_interval; /* 0 = covert once, 1 = every 0.5 ms,
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2 = ever 1 ms, 3 = every 8 ms,*/
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};
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@@ -0,0 +1,45 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* linux/spi/ads7846.h */
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struct ads7846_platform_data {
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u16 model; /* 7843, 7845, 7846, 7873. */
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u16 vref_delay_usecs; /* 0 for external vref; etc */
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u16 vref_mv; /* external vref value, milliVolts
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* ads7846: if 0, use internal vref */
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bool keep_vref_on; /* set to keep vref on for differential
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* measurements as well */
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bool swap_xy; /* swap x and y axes */
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/* Settling time of the analog signals; a function of Vcc and the
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* capacitance on the X/Y drivers. If set to non-zero, two samples
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* are taken with settle_delay us apart, and the second one is used.
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* ~150 uSec with 0.01uF caps.
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*/
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u16 settle_delay_usecs;
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/* If set to non-zero, after samples are taken this delay is applied
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* and penirq is rechecked, to help avoid false events. This value
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* is affected by the material used to build the touch layer.
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*/
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u16 penirq_recheck_delay_usecs;
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u16 x_plate_ohms;
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u16 y_plate_ohms;
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u16 x_min, x_max;
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u16 y_min, y_max;
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u16 pressure_min, pressure_max;
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u16 debounce_max; /* max number of additional readings
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* per sample */
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u16 debounce_tol; /* tolerance used for filtering */
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u16 debounce_rep; /* additional consecutive good readings
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* required after the first two */
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int gpio_pendown_debounce; /* platform specific debounce time for
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* the gpio_pendown */
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int (*get_pendown_state)(void);
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void (*wait_for_sync)(void);
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bool wakeup;
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unsigned long irq_flags;
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};
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@@ -0,0 +1,50 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header File for Altera SPI Driver.
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*/
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#ifndef __LINUX_SPI_ALTERA_H
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#define __LINUX_SPI_ALTERA_H
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#define ALTERA_SPI_MAX_CS 32
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/**
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* struct altera_spi_platform_data - Platform data of the Altera SPI driver
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* @mode_bits: Mode bits of SPI host.
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* @num_chipselect: Number of chipselects.
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* @bits_per_word_mask: bitmask of supported bits_per_word for transfers.
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* @num_devices: Number of devices that shall be added when the driver
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* is probed.
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* @devices: The devices to add.
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*/
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struct altera_spi_platform_data {
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u16 mode_bits;
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u16 num_chipselect;
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u32 bits_per_word_mask;
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u16 num_devices;
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struct spi_board_info *devices;
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};
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struct altera_spi {
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int irq;
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int len;
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int count;
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int bytes_per_word;
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u32 imr;
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/* data buffers */
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const unsigned char *tx;
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unsigned char *rx;
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struct regmap *regmap;
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u32 regoff;
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struct device *dev;
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};
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extern irqreturn_t altera_spi_irq(int irq, void *dev);
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extern void altera_spi_init_host(struct spi_controller *host);
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#endif /* __LINUX_SPI_ALTERA_H */
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@@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Board-specific data used to set up AT73c213 audio DAC driver.
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*/
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#ifndef __LINUX_SPI_AT73C213_H
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#define __LINUX_SPI_AT73C213_H
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/**
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* at73c213_board_info - how the external DAC is wired to the device.
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*
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* @ssc_id: SSC platform_driver id the DAC shall use to stream the audio.
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* @dac_clk: the external clock used to provide master clock to the DAC.
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* @shortname: a short discription for the DAC, seen by userspace tools.
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*
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* This struct contains the configuration of the hardware connection to the
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* external DAC. The DAC needs a master clock and a I2S audio stream. It also
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* provides a name which is used to identify it in userspace tools.
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*/
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struct at73c213_board_info {
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int ssc_id;
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struct clk *dac_clk;
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char shortname[32];
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};
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#endif /* __LINUX_SPI_AT73C213_H */
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@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SPI_CORGI_LCD_H
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#define __LINUX_SPI_CORGI_LCD_H
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#define CORGI_LCD_MODE_QVGA 1
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#define CORGI_LCD_MODE_VGA 2
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struct corgi_lcd_platform_data {
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int init_mode;
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int max_intensity;
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int default_intensity;
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int limit_mask;
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void (*notify)(int intensity);
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void (*kick_battery)(void);
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};
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void corgi_lcd_limit_intensity(int limit);
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#endif /* __LINUX_SPI_CORGI_LCD_H */
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@@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SPI_DS1305_H
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#define __LINUX_SPI_DS1305_H
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/*
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* One-time configuration for ds1305 and ds1306 RTC chips.
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*
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* Put a pointer to this in spi_board_info.platform_data if you want to
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* be sure that Linux (re)initializes this as needed ... after losing
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* backup power, and potentially on the first boot.
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*/
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struct ds1305_platform_data {
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/* Trickle charge configuration: it's OK to leave out the MAGIC
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* bitmask; mask in either DS1 or DS2, and then one of 2K/4k/8K.
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*/
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#define DS1305_TRICKLE_MAGIC 0xa0
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#define DS1305_TRICKLE_DS2 0x08 /* two diodes */
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#define DS1305_TRICKLE_DS1 0x04 /* one diode */
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#define DS1305_TRICKLE_2K 0x01 /* 2 KOhm resistance */
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#define DS1305_TRICKLE_4K 0x02 /* 4 KOhm resistance */
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#define DS1305_TRICKLE_8K 0x03 /* 8 KOhm resistance */
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u8 trickle;
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/* set only on ds1306 parts */
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bool is_ds1306;
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/* ds1306 only: enable 1 Hz output */
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bool en_1hz;
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/* REVISIT: the driver currently expects nINT0 to be wired
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* as the alarm IRQ. ALM1 may also need to be set up ...
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*/
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};
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#endif /* __LINUX_SPI_DS1305_H */
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@@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SPI_EEPROM_H
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#define __LINUX_SPI_EEPROM_H
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#include <linux/memory.h>
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/*
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* Put one of these structures in platform_data for SPI EEPROMS handled
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* by the "at25" driver. On SPI, most EEPROMS understand the same core
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* command set. If you need to support EEPROMs that don't yet fit, add
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* flags to support those protocol options. These values all come from
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* the chip datasheets.
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*/
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struct spi_eeprom {
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u32 byte_len;
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char name[10];
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u32 page_size; /* for writes */
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u16 flags;
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#define EE_ADDR1 0x0001 /* 8 bit addrs */
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#define EE_ADDR2 0x0002 /* 16 bit addrs */
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#define EE_ADDR3 0x0004 /* 24 bit addrs */
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#define EE_READONLY 0x0008 /* disallow writes */
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/*
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* Certain EEPROMS have a size that is larger than the number of address
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* bytes would allow (e.g. like M95040 from ST that has 512 Byte size
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* but uses only one address byte (A0 to A7) for addressing.) For
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* the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
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* is used. This instruction bit is normally defined as don't care for
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* other AT25 like chips.
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*/
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#define EE_INSTR_BIT3_IS_ADDR 0x0010
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void *context;
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};
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#endif /* __LINUX_SPI_EEPROM_H */
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@@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef LINUX_SPI_FLASH_H
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#define LINUX_SPI_FLASH_H
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struct mtd_partition;
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/**
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* struct flash_platform_data: board-specific flash data
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* @name: optional flash device name (eg, as used with mtdparts=)
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* @parts: optional array of mtd_partitions for static partitioning
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* @nr_parts: number of mtd_partitions for static partitioning
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* @type: optional flash device type (e.g. m25p80 vs m25p64), for use
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* with chips that can't be queried for JEDEC or other IDs
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*
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* Board init code (in arch/.../mach-xxx/board-yyy.c files) can
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* provide information about SPI flash parts (such as DataFlash) to
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* help set up the device and its appropriate default partitioning.
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*
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* Note that for DataFlash, sizes for pages, blocks, and sectors are
|
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* rarely powers of two; and partitions should be sector-aligned.
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*/
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struct flash_platform_data {
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char *name;
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struct mtd_partition *parts;
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unsigned int nr_parts;
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char *type;
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/* we'll likely add more ... use JEDEC IDs, etc */
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};
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#endif
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@@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* board-specific data for the libertas_spi driver.
|
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*
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* Copyright 2008 Analog Devices Inc.
|
||||
*/
|
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#ifndef _LIBERTAS_SPI_H_
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#define _LIBERTAS_SPI_H_
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struct spi_device;
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|
||||
struct libertas_spi_platform_data {
|
||||
/* There are two ways to read data from the WLAN module's SPI
|
||||
* interface. Setting 0 or 1 here controls which one is used.
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||||
*
|
||||
* Usually you want to set use_dummy_writes = 1.
|
||||
* However, if that doesn't work or if you are using a slow SPI clock
|
||||
* speed, you may want to use 0 here. */
|
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u16 use_dummy_writes;
|
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|
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/* Board specific setup/teardown */
|
||||
int (*setup)(struct spi_device *spi);
|
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int (*teardown)(struct spi_device *spi);
|
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};
|
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#endif
|
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@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef LINUX_SPI_MAX7301_H
|
||||
#define LINUX_SPI_MAX7301_H
|
||||
|
||||
#include <linux/gpio/driver.h>
|
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|
||||
/*
|
||||
* Some registers must be read back to modify.
|
||||
* To save time we cache them here in memory
|
||||
*/
|
||||
struct max7301 {
|
||||
struct mutex lock;
|
||||
u8 port_config[8]; /* field 0 is unused */
|
||||
u32 out_level; /* cached output levels */
|
||||
u32 input_pullup_active;
|
||||
struct gpio_chip chip;
|
||||
struct device *dev;
|
||||
int (*write)(struct device *dev, unsigned int reg, unsigned int val);
|
||||
int (*read)(struct device *dev, unsigned int reg);
|
||||
};
|
||||
|
||||
struct max7301_platform_data {
|
||||
/* number assigned to the first GPIO */
|
||||
unsigned base;
|
||||
/*
|
||||
* bitmask controlling the pullup configuration,
|
||||
*
|
||||
* _note_ the 4 lowest bits are unused, because the first 4
|
||||
* ports of the controller are not used, too.
|
||||
*/
|
||||
u32 input_pullup_active;
|
||||
};
|
||||
|
||||
extern void __max730x_remove(struct device *dev);
|
||||
extern int __max730x_probe(struct max7301 *ts);
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef LINUX_SPI_MC33880_H
|
||||
#define LINUX_SPI_MC33880_H
|
||||
|
||||
struct mc33880_platform_data {
|
||||
/* number assigned to the first GPIO */
|
||||
unsigned base;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SPI_MMC_SPI_H
|
||||
#define __LINUX_SPI_MMC_SPI_H
|
||||
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
struct device;
|
||||
struct mmc_host;
|
||||
|
||||
/* Put this in platform_data of a device being used to manage an MMC/SD
|
||||
* card slot. (Modeled after PXA mmc glue; see that for usage examples.)
|
||||
*
|
||||
* REVISIT This is not a spi-specific notion. Any card slot should be
|
||||
* able to handle it. If the MMC core doesn't adopt this kind of notion,
|
||||
* switch the "struct device *" parameters over to "struct spi_device *".
|
||||
*/
|
||||
struct mmc_spi_platform_data {
|
||||
/* driver activation and (optional) card detect irq hookup */
|
||||
int (*init)(struct device *,
|
||||
irqreturn_t (*)(int, void *),
|
||||
void *);
|
||||
void (*exit)(struct device *, void *);
|
||||
|
||||
/* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */
|
||||
unsigned long caps;
|
||||
unsigned long caps2;
|
||||
|
||||
/* how long to debounce card detect, in msecs */
|
||||
u16 detect_delay;
|
||||
|
||||
/* power management */
|
||||
u16 powerup_msecs; /* delay of up to 250 msec */
|
||||
u32 ocr_mask; /* available voltages */
|
||||
void (*setpower)(struct device *, unsigned int maskval);
|
||||
};
|
||||
|
||||
extern struct mmc_spi_platform_data *mmc_spi_get_pdata(struct spi_device *spi);
|
||||
extern void mmc_spi_put_pdata(struct spi_device *spi);
|
||||
|
||||
#endif /* __LINUX_SPI_MMC_SPI_H */
|
||||
@@ -0,0 +1,135 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* include/linux/spi/mxs-spi.h
|
||||
*
|
||||
* Freescale i.MX233/i.MX28 SPI controller register definition
|
||||
*
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc.
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SPI_MXS_SPI_H__
|
||||
#define __LINUX_SPI_MXS_SPI_H__
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define ssp_is_old(host) ((host)->devid == IMX23_SSP)
|
||||
|
||||
/* SSP registers */
|
||||
#define HW_SSP_CTRL0 0x000
|
||||
#define BM_SSP_CTRL0_RUN (1 << 29)
|
||||
#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
|
||||
#define BM_SSP_CTRL0_LOCK_CS (1 << 27)
|
||||
#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
|
||||
#define BM_SSP_CTRL0_READ (1 << 25)
|
||||
#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
|
||||
#define BP_SSP_CTRL0_BUS_WIDTH 22
|
||||
#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
|
||||
#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
|
||||
#define BM_SSP_CTRL0_GET_RESP (1 << 17)
|
||||
#define BM_SSP_CTRL0_ENABLE (1 << 16)
|
||||
#define BP_SSP_CTRL0_XFER_COUNT 0
|
||||
#define BM_SSP_CTRL0_XFER_COUNT 0xffff
|
||||
#define HW_SSP_CMD0 0x010
|
||||
#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
|
||||
#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
|
||||
#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
|
||||
#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
|
||||
#define BP_SSP_CMD0_BLOCK_SIZE 16
|
||||
#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
|
||||
#define BP_SSP_CMD0_BLOCK_COUNT 8
|
||||
#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
|
||||
#define BP_SSP_CMD0_CMD 0
|
||||
#define BM_SSP_CMD0_CMD 0xff
|
||||
#define HW_SSP_CMD1 0x020
|
||||
#define HW_SSP_XFER_SIZE 0x030
|
||||
#define HW_SSP_BLOCK_SIZE 0x040
|
||||
#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
|
||||
#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
|
||||
#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
|
||||
#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
|
||||
#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
|
||||
#define BP_SSP_TIMING_TIMEOUT 16
|
||||
#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
|
||||
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
|
||||
#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
|
||||
#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
|
||||
(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
|
||||
#define BP_SSP_TIMING_CLOCK_RATE 0
|
||||
#define BM_SSP_TIMING_CLOCK_RATE 0xff
|
||||
#define BF_SSP_TIMING_CLOCK_RATE(v) \
|
||||
(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
|
||||
#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
|
||||
#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
|
||||
#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
|
||||
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
|
||||
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
|
||||
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
|
||||
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
|
||||
#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
|
||||
#define BM_SSP_CTRL1_PHASE (1 << 10)
|
||||
#define BM_SSP_CTRL1_POLARITY (1 << 9)
|
||||
#define BP_SSP_CTRL1_WORD_LENGTH 4
|
||||
#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
|
||||
#define BF_SSP_CTRL1_WORD_LENGTH(v) \
|
||||
(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
|
||||
#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
|
||||
#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
|
||||
#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
|
||||
#define BP_SSP_CTRL1_SSP_MODE 0
|
||||
#define BM_SSP_CTRL1_SSP_MODE 0xf
|
||||
#define BF_SSP_CTRL1_SSP_MODE(v) \
|
||||
(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
|
||||
#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
|
||||
#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
|
||||
#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
|
||||
#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
|
||||
|
||||
#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090)
|
||||
|
||||
#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
|
||||
#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
|
||||
#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
|
||||
#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
|
||||
#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
|
||||
#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
|
||||
#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
|
||||
#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5)
|
||||
|
||||
#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
|
||||
|
||||
#define SSP_PIO_NUM 3
|
||||
|
||||
enum mxs_ssp_id {
|
||||
IMX23_SSP,
|
||||
IMX28_SSP,
|
||||
};
|
||||
|
||||
struct mxs_ssp {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
unsigned int clk_rate;
|
||||
enum mxs_ssp_id devid;
|
||||
|
||||
struct dma_chan *dmach;
|
||||
unsigned int dma_dir;
|
||||
enum dma_transfer_direction slave_dirn;
|
||||
u32 ssp_pio_words[SSP_PIO_NUM];
|
||||
};
|
||||
|
||||
void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
|
||||
|
||||
#endif /* __LINUX_SPI_MXS_SPI_H__ */
|
||||
@@ -0,0 +1,39 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2024 Analog Devices Inc.
|
||||
* Copyright (C) 2024 BayLibre, SAS
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SPI_OFFLOAD_CONSUMER_H
|
||||
#define __LINUX_SPI_OFFLOAD_CONSUMER_H
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/spi/offload/types.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
MODULE_IMPORT_NS("SPI_OFFLOAD");
|
||||
|
||||
struct device;
|
||||
struct spi_device;
|
||||
|
||||
struct spi_offload *devm_spi_offload_get(struct device *dev, struct spi_device *spi,
|
||||
const struct spi_offload_config *config);
|
||||
|
||||
struct spi_offload_trigger
|
||||
*devm_spi_offload_trigger_get(struct device *dev,
|
||||
struct spi_offload *offload,
|
||||
enum spi_offload_trigger_type type);
|
||||
int spi_offload_trigger_validate(struct spi_offload_trigger *trigger,
|
||||
struct spi_offload_trigger_config *config);
|
||||
int spi_offload_trigger_enable(struct spi_offload *offload,
|
||||
struct spi_offload_trigger *trigger,
|
||||
struct spi_offload_trigger_config *config);
|
||||
void spi_offload_trigger_disable(struct spi_offload *offload,
|
||||
struct spi_offload_trigger *trigger);
|
||||
|
||||
struct dma_chan *devm_spi_offload_tx_stream_request_dma_chan(struct device *dev,
|
||||
struct spi_offload *offload);
|
||||
struct dma_chan *devm_spi_offload_rx_stream_request_dma_chan(struct device *dev,
|
||||
struct spi_offload *offload);
|
||||
|
||||
#endif /* __LINUX_SPI_OFFLOAD_CONSUMER_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2024 Analog Devices Inc.
|
||||
* Copyright (C) 2024 BayLibre, SAS
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SPI_OFFLOAD_PROVIDER_H
|
||||
#define __LINUX_SPI_OFFLOAD_PROVIDER_H
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/spi/offload/types.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
MODULE_IMPORT_NS("SPI_OFFLOAD");
|
||||
|
||||
struct device;
|
||||
struct spi_offload_trigger;
|
||||
|
||||
struct spi_offload *devm_spi_offload_alloc(struct device *dev, size_t priv_size);
|
||||
|
||||
struct spi_offload_trigger_ops {
|
||||
bool (*match)(struct spi_offload_trigger *trigger,
|
||||
enum spi_offload_trigger_type type, u64 *args, u32 nargs);
|
||||
int (*request)(struct spi_offload_trigger *trigger,
|
||||
enum spi_offload_trigger_type type, u64 *args, u32 nargs);
|
||||
void (*release)(struct spi_offload_trigger *trigger);
|
||||
int (*validate)(struct spi_offload_trigger *trigger,
|
||||
struct spi_offload_trigger_config *config);
|
||||
int (*enable)(struct spi_offload_trigger *trigger,
|
||||
struct spi_offload_trigger_config *config);
|
||||
void (*disable)(struct spi_offload_trigger *trigger);
|
||||
};
|
||||
|
||||
struct spi_offload_trigger_info {
|
||||
/** @fwnode: Provider fwnode, used to match to consumer. */
|
||||
struct fwnode_handle *fwnode;
|
||||
/** @ops: Provider-specific callbacks. */
|
||||
const struct spi_offload_trigger_ops *ops;
|
||||
/** Provider-specific state to be used in callbacks. */
|
||||
void *priv;
|
||||
};
|
||||
|
||||
int devm_spi_offload_trigger_register(struct device *dev,
|
||||
struct spi_offload_trigger_info *info);
|
||||
void *spi_offload_trigger_get_priv(struct spi_offload_trigger *trigger);
|
||||
|
||||
#endif /* __LINUX_SPI_OFFLOAD_PROVIDER_H */
|
||||
@@ -0,0 +1,109 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2024 Analog Devices Inc.
|
||||
* Copyright (C) 2024 BayLibre, SAS
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SPI_OFFLOAD_TYPES_H
|
||||
#define __LINUX_SPI_OFFLOAD_TYPES_H
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device;
|
||||
|
||||
/* This is write xfer but TX uses external data stream rather than tx_buf. */
|
||||
#define SPI_OFFLOAD_XFER_TX_STREAM BIT(0)
|
||||
/* This is read xfer but RX uses external data stream rather than rx_buf. */
|
||||
#define SPI_OFFLOAD_XFER_RX_STREAM BIT(1)
|
||||
|
||||
/* Offload can be triggered by external hardware event. */
|
||||
#define SPI_OFFLOAD_CAP_TRIGGER BIT(0)
|
||||
/* Offload can record and then play back TX data when triggered. */
|
||||
#define SPI_OFFLOAD_CAP_TX_STATIC_DATA BIT(1)
|
||||
/* Offload can get TX data from an external stream source. */
|
||||
#define SPI_OFFLOAD_CAP_TX_STREAM_DMA BIT(2)
|
||||
/* Offload can send RX data to an external stream sink. */
|
||||
#define SPI_OFFLOAD_CAP_RX_STREAM_DMA BIT(3)
|
||||
|
||||
/**
|
||||
* struct spi_offload_config - offload configuration
|
||||
*
|
||||
* This is used to request an offload with specific configuration.
|
||||
*/
|
||||
struct spi_offload_config {
|
||||
/** @capability_flags: required capabilities. See %SPI_OFFLOAD_CAP_* */
|
||||
u32 capability_flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_offload - offload instance
|
||||
*/
|
||||
struct spi_offload {
|
||||
/** @provider_dev: for get/put reference counting */
|
||||
struct device *provider_dev;
|
||||
/** @priv: provider driver private data */
|
||||
void *priv;
|
||||
/** @ops: callbacks for offload support */
|
||||
const struct spi_offload_ops *ops;
|
||||
/** @xfer_flags: %SPI_OFFLOAD_XFER_* flags supported by provider */
|
||||
u32 xfer_flags;
|
||||
};
|
||||
|
||||
enum spi_offload_trigger_type {
|
||||
/* Indication from SPI peripheral that data is read to read. */
|
||||
SPI_OFFLOAD_TRIGGER_DATA_READY,
|
||||
/* Trigger comes from a periodic source such as a clock. */
|
||||
SPI_OFFLOAD_TRIGGER_PERIODIC,
|
||||
};
|
||||
|
||||
/**
|
||||
* spi_offload_trigger_periodic - configuration parameters for periodic triggers
|
||||
* @frequency_hz: The rate that the trigger should fire in Hz.
|
||||
* @offset_ns: A delay in nanoseconds between when this trigger fires
|
||||
* compared to another trigger. This requires specialized hardware
|
||||
* that supports such synchronization with a delay between two or
|
||||
* more triggers. Set to 0 when not needed.
|
||||
*/
|
||||
struct spi_offload_trigger_periodic {
|
||||
u64 frequency_hz;
|
||||
u64 offset_ns;
|
||||
};
|
||||
|
||||
struct spi_offload_trigger_config {
|
||||
/** @type: type discriminator for union */
|
||||
enum spi_offload_trigger_type type;
|
||||
union {
|
||||
struct spi_offload_trigger_periodic periodic;
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_offload_ops - callbacks implemented by offload providers
|
||||
*/
|
||||
struct spi_offload_ops {
|
||||
/**
|
||||
* @trigger_enable: Optional callback to enable the trigger for the
|
||||
* given offload instance.
|
||||
*/
|
||||
int (*trigger_enable)(struct spi_offload *offload);
|
||||
/**
|
||||
* @trigger_disable: Optional callback to disable the trigger for the
|
||||
* given offload instance.
|
||||
*/
|
||||
void (*trigger_disable)(struct spi_offload *offload);
|
||||
/**
|
||||
* @tx_stream_request_dma_chan: Optional callback for controllers that
|
||||
* have an offload where the TX data stream is connected directly to a
|
||||
* DMA channel.
|
||||
*/
|
||||
struct dma_chan *(*tx_stream_request_dma_chan)(struct spi_offload *offload);
|
||||
/**
|
||||
* @rx_stream_request_dma_chan: Optional callback for controllers that
|
||||
* have an offload where the RX data stream is connected directly to a
|
||||
* DMA channel.
|
||||
*/
|
||||
struct dma_chan *(*rx_stream_request_dma_chan)(struct spi_offload *offload);
|
||||
};
|
||||
|
||||
#endif /* __LINUX_SPI_OFFLOAD_TYPES_H */
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2011 Kuninori Morimoto
|
||||
*/
|
||||
#ifndef SH_HSPI_H
|
||||
#define SH_HSPI_H
|
||||
|
||||
struct sh_hspi_info {
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,146 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __SPI_SH_MSIOF_H__
|
||||
#define __SPI_SH_MSIOF_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bits.h>
|
||||
|
||||
#define SITMDR1 0x00 /* Transmit Mode Register 1 */
|
||||
#define SITMDR2 0x04 /* Transmit Mode Register 2 */
|
||||
#define SITMDR3 0x08 /* Transmit Mode Register 3 */
|
||||
#define SIRMDR1 0x10 /* Receive Mode Register 1 */
|
||||
#define SIRMDR2 0x14 /* Receive Mode Register 2 */
|
||||
#define SIRMDR3 0x18 /* Receive Mode Register 3 */
|
||||
#define SITSCR 0x20 /* Transmit Clock Select Register */
|
||||
#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
|
||||
#define SICTR 0x28 /* Control Register */
|
||||
#define SIFCTR 0x30 /* FIFO Control Register */
|
||||
#define SISTR 0x40 /* Status Register */
|
||||
#define SIIER 0x44 /* Interrupt Enable Register */
|
||||
#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
|
||||
#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
|
||||
#define SITFDR 0x50 /* Transmit FIFO Data Register */
|
||||
#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
|
||||
#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
|
||||
#define SIRFDR 0x60 /* Receive FIFO Data Register */
|
||||
|
||||
/* SITMDR1 and SIRMDR1 */
|
||||
#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
|
||||
#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
|
||||
#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */
|
||||
#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */
|
||||
#define SIMDR1_SYNCMD_LR 3U /* L/R mode */
|
||||
#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
|
||||
#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
|
||||
#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
|
||||
#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
|
||||
#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
|
||||
#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
|
||||
/* SITMDR1 */
|
||||
#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
|
||||
#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */
|
||||
/* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
|
||||
|
||||
/* SITMDR2 and SIRMDR2 */
|
||||
#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */
|
||||
#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
|
||||
#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
|
||||
#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */
|
||||
|
||||
/* SITMDR3 and SIRMDR3 */
|
||||
#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */
|
||||
#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
|
||||
|
||||
/* SITSCR and SIRSCR */
|
||||
#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */
|
||||
#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
|
||||
|
||||
/* SICTR */
|
||||
#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
|
||||
#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
|
||||
#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */
|
||||
#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */
|
||||
#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
|
||||
#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */
|
||||
#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */
|
||||
#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */
|
||||
#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */
|
||||
#define SICTR_TXDIZ_LOW 0U /* 0 */
|
||||
#define SICTR_TXDIZ_HIGH 1U /* 1 */
|
||||
#define SICTR_TXDIZ_HIZ 2U /* High-impedance */
|
||||
#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
|
||||
#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
|
||||
#define SICTR_TXE BIT(9) /* Transmit Enable */
|
||||
#define SICTR_RXE BIT(8) /* Receive Enable */
|
||||
#define SICTR_TXRST BIT(1) /* Transmit Reset */
|
||||
#define SICTR_RXRST BIT(0) /* Receive Reset */
|
||||
|
||||
/* SIFCTR */
|
||||
#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */
|
||||
#define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */
|
||||
#define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */
|
||||
#define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */
|
||||
#define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */
|
||||
#define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */
|
||||
#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */
|
||||
#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */
|
||||
#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */
|
||||
#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */
|
||||
#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */
|
||||
#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */
|
||||
#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */
|
||||
#define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */
|
||||
#define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */
|
||||
#define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */
|
||||
#define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */
|
||||
#define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */
|
||||
#define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */
|
||||
#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
|
||||
|
||||
/* SISTR */
|
||||
#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
|
||||
#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
|
||||
#define SISTR_TEOF BIT(23) /* Frame Transmission End */
|
||||
#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
|
||||
#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
|
||||
#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
|
||||
#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
|
||||
#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
|
||||
#define SISTR_REOF BIT(7) /* Frame Reception End */
|
||||
#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
|
||||
#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
|
||||
#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
|
||||
|
||||
/* SIIER */
|
||||
#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
|
||||
#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
|
||||
#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
|
||||
#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
|
||||
#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
|
||||
#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
|
||||
#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
|
||||
#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
|
||||
#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
|
||||
#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
|
||||
#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
|
||||
#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
|
||||
#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
|
||||
#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
|
||||
|
||||
enum {
|
||||
MSIOF_SPI_HOST,
|
||||
MSIOF_SPI_TARGET,
|
||||
};
|
||||
|
||||
struct sh_msiof_spi_info {
|
||||
int tx_fifo_override;
|
||||
int rx_fifo_override;
|
||||
u16 num_chipselect;
|
||||
int mode;
|
||||
unsigned int dma_tx_id;
|
||||
unsigned int dma_rx_id;
|
||||
u32 dtdl;
|
||||
u32 syncdl;
|
||||
};
|
||||
|
||||
#endif /* __SPI_SH_MSIOF_H__ */
|
||||
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Freescale DSPI controller driver
|
||||
*
|
||||
* Copyright (c) 2017 Angelo Dureghello <angelo@sysam.it>
|
||||
*/
|
||||
|
||||
#ifndef SPI_FSL_DSPI_HEADER_H
|
||||
#define SPI_FSL_DSPI_HEADER_H
|
||||
|
||||
/**
|
||||
* struct fsl_dspi_platform_data - platform data for the Freescale DSPI driver
|
||||
* @bus_num: board specific identifier for this DSPI driver.
|
||||
* @cs_num: number of chip selects supported by this DSPI driver.
|
||||
*/
|
||||
struct fsl_dspi_platform_data {
|
||||
u32 cs_num;
|
||||
u32 bus_num;
|
||||
u32 sck_cs_delay;
|
||||
u32 cs_sck_delay;
|
||||
};
|
||||
|
||||
#endif /* SPI_FSL_DSPI_HEADER_H */
|
||||
@@ -0,0 +1,498 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 Exceet Electronics GmbH
|
||||
* Copyright (C) 2018 Bootlin
|
||||
*
|
||||
* Author:
|
||||
* Peter Pan <peterpandong@micron.com>
|
||||
* Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SPI_MEM_H
|
||||
#define __LINUX_SPI_MEM_H
|
||||
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#define SPI_MEM_OP_CMD(__opcode, __buswidth) \
|
||||
{ \
|
||||
.nbytes = 1, \
|
||||
.buswidth = __buswidth, \
|
||||
.opcode = __opcode, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_RPT_CMD(__opcode, __buswidth) \
|
||||
{ \
|
||||
.nbytes = 2, \
|
||||
.opcode = __opcode | __opcode << 8, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_PACKED_CMD(__opcode, __addr, __buswidth) \
|
||||
{ \
|
||||
.nbytes = 2, \
|
||||
.opcode = __opcode << 8 | __addr, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
|
||||
{ \
|
||||
.nbytes = __nbytes, \
|
||||
.buswidth = __buswidth, \
|
||||
.val = __val, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_ADDR(__nbytes, __val, __buswidth) \
|
||||
{ \
|
||||
.nbytes = __nbytes, \
|
||||
.val = __val, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \
|
||||
{ \
|
||||
.nbytes = 2, \
|
||||
.val = __val | __val << 8, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \
|
||||
{ \
|
||||
.nbytes = 2, \
|
||||
.val = __val | __val << 8, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_OP_NO_ADDR { }
|
||||
|
||||
#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
|
||||
{ \
|
||||
.nbytes = __nbytes, \
|
||||
.buswidth = __buswidth, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_DUMMY(__nbytes, __buswidth) \
|
||||
{ \
|
||||
.nbytes = __nbytes, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_OP_NO_DUMMY { }
|
||||
|
||||
#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
|
||||
{ \
|
||||
.buswidth = __buswidth, \
|
||||
.dir = SPI_MEM_DATA_IN, \
|
||||
.nbytes = __nbytes, \
|
||||
.buf.in = __buf, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_DATA_IN(__nbytes, __buf, __buswidth) \
|
||||
{ \
|
||||
.dir = SPI_MEM_DATA_IN, \
|
||||
.nbytes = __nbytes, \
|
||||
.buf.in = __buf, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
|
||||
{ \
|
||||
.buswidth = __buswidth, \
|
||||
.dir = SPI_MEM_DATA_OUT, \
|
||||
.nbytes = __nbytes, \
|
||||
.buf.out = __buf, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_DTR_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
|
||||
{ \
|
||||
.dir = SPI_MEM_DATA_OUT, \
|
||||
.nbytes = __nbytes, \
|
||||
.buf.out = __buf, \
|
||||
.buswidth = __buswidth, \
|
||||
.dtr = true, \
|
||||
}
|
||||
|
||||
#define SPI_MEM_OP_NO_DATA { }
|
||||
|
||||
/**
|
||||
* enum spi_mem_data_dir - describes the direction of a SPI memory data
|
||||
* transfer from the controller perspective
|
||||
* @SPI_MEM_NO_DATA: no data transferred
|
||||
* @SPI_MEM_DATA_IN: data coming from the SPI memory
|
||||
* @SPI_MEM_DATA_OUT: data sent to the SPI memory
|
||||
*/
|
||||
enum spi_mem_data_dir {
|
||||
SPI_MEM_NO_DATA,
|
||||
SPI_MEM_DATA_IN,
|
||||
SPI_MEM_DATA_OUT,
|
||||
};
|
||||
|
||||
#define SPI_MEM_OP_MAX_FREQ(__freq) \
|
||||
.max_freq = __freq
|
||||
|
||||
/**
|
||||
* struct spi_mem_op - describes a SPI memory operation
|
||||
* @cmd: the complete command
|
||||
* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
|
||||
* sent MSB-first.
|
||||
* @cmd.buswidth: number of IO lines used to transmit the command
|
||||
* @cmd.opcode: operation opcode
|
||||
* @cmd.dtr: whether the command opcode should be sent in DTR mode or not
|
||||
* @addr: the address attributes
|
||||
* @addr.nbytes: number of address bytes to send. Can be zero if the operation
|
||||
* does not need to send an address
|
||||
* @addr.buswidth: number of IO lines used to transmit the address cycles
|
||||
* @addr.dtr: whether the address should be sent in DTR mode or not
|
||||
* @addr.val: address value. This value is always sent MSB first on the bus.
|
||||
* Note that only @addr.nbytes are taken into account in this
|
||||
* address value, so users should make sure the value fits in the
|
||||
* assigned number of bytes.
|
||||
* @dummy: data for dummy operation
|
||||
* @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
|
||||
* be zero if the operation does not require dummy bytes
|
||||
* @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
|
||||
* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
|
||||
* @data: the data attributes
|
||||
* @data.buswidth: number of IO lanes used to send/receive the data
|
||||
* @data.dtr: whether the data should be sent in DTR mode or not
|
||||
* @data.ecc: whether error correction is required or not
|
||||
* @data.swap16: whether the byte order of 16-bit words is swapped when read
|
||||
* or written in Octal DTR mode compared to STR mode.
|
||||
* @data.dir: direction of the transfer
|
||||
* @data.nbytes: number of data bytes to send/receive. Can be zero if the
|
||||
* operation does not involve transferring data
|
||||
* @data.buf.in: input buffer (must be DMA-able)
|
||||
* @data.buf.out: output buffer (must be DMA-able)
|
||||
* @max_freq: frequency limitation wrt this operation. 0 means there is no
|
||||
* specific constraint and the highest achievable frequency can be
|
||||
* attempted.
|
||||
*/
|
||||
struct spi_mem_op {
|
||||
struct {
|
||||
u8 nbytes;
|
||||
u8 buswidth;
|
||||
u8 dtr : 1;
|
||||
u8 __pad : 7;
|
||||
u16 opcode;
|
||||
} cmd;
|
||||
|
||||
struct {
|
||||
u8 nbytes;
|
||||
u8 buswidth;
|
||||
u8 dtr : 1;
|
||||
u8 __pad : 7;
|
||||
u64 val;
|
||||
} addr;
|
||||
|
||||
struct {
|
||||
u8 nbytes;
|
||||
u8 buswidth;
|
||||
u8 dtr : 1;
|
||||
u8 __pad : 7;
|
||||
} dummy;
|
||||
|
||||
struct {
|
||||
u8 buswidth;
|
||||
u8 dtr : 1;
|
||||
u8 ecc : 1;
|
||||
u8 swap16 : 1;
|
||||
u8 __pad : 5;
|
||||
enum spi_mem_data_dir dir;
|
||||
unsigned int nbytes;
|
||||
union {
|
||||
void *in;
|
||||
const void *out;
|
||||
} buf;
|
||||
} data;
|
||||
|
||||
unsigned int max_freq;
|
||||
};
|
||||
|
||||
#define SPI_MEM_OP(__cmd, __addr, __dummy, __data, ...) \
|
||||
{ \
|
||||
.cmd = __cmd, \
|
||||
.addr = __addr, \
|
||||
.dummy = __dummy, \
|
||||
.data = __data, \
|
||||
__VA_ARGS__ \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct spi_mem_dirmap_info - Direct mapping information
|
||||
* @op_tmpl: operation template that should be used by the direct mapping when
|
||||
* the memory device is accessed
|
||||
* @offset: absolute offset this direct mapping is pointing to
|
||||
* @length: length in byte of this direct mapping
|
||||
*
|
||||
* These information are used by the controller specific implementation to know
|
||||
* the portion of memory that is directly mapped and the spi_mem_op that should
|
||||
* be used to access the device.
|
||||
* A direct mapping is only valid for one direction (read or write) and this
|
||||
* direction is directly encoded in the ->op_tmpl.data.dir field.
|
||||
*/
|
||||
struct spi_mem_dirmap_info {
|
||||
struct spi_mem_op op_tmpl;
|
||||
u64 offset;
|
||||
u64 length;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_mem_dirmap_desc - Direct mapping descriptor
|
||||
* @mem: the SPI memory device this direct mapping is attached to
|
||||
* @info: information passed at direct mapping creation time
|
||||
* @nodirmap: set to 1 if the SPI controller does not implement
|
||||
* ->mem_ops->dirmap_create() or when this function returned an
|
||||
* error. If @nodirmap is true, all spi_mem_dirmap_{read,write}()
|
||||
* calls will use spi_mem_exec_op() to access the memory. This is a
|
||||
* degraded mode that allows spi_mem drivers to use the same code
|
||||
* no matter whether the controller supports direct mapping or not
|
||||
* @priv: field pointing to controller specific data
|
||||
*
|
||||
* Common part of a direct mapping descriptor. This object is created by
|
||||
* spi_mem_dirmap_create() and controller implementation of ->create_dirmap()
|
||||
* can create/attach direct mapping resources to the descriptor in the ->priv
|
||||
* field.
|
||||
*/
|
||||
struct spi_mem_dirmap_desc {
|
||||
struct spi_mem *mem;
|
||||
struct spi_mem_dirmap_info info;
|
||||
unsigned int nodirmap;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_mem - describes a SPI memory device
|
||||
* @spi: the underlying SPI device
|
||||
* @drvpriv: spi_mem_driver private data
|
||||
* @name: name of the SPI memory device
|
||||
*
|
||||
* Extra information that describe the SPI memory device and may be needed by
|
||||
* the controller to properly handle this device should be placed here.
|
||||
*
|
||||
* One example would be the device size since some controller expose their SPI
|
||||
* mem devices through a io-mapped region.
|
||||
*/
|
||||
struct spi_mem {
|
||||
struct spi_device *spi;
|
||||
void *drvpriv;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/**
|
||||
* spi_mem_set_drvdata() - attach driver private data to a SPI mem
|
||||
* device
|
||||
* @mem: memory device
|
||||
* @data: data to attach to the memory device
|
||||
*/
|
||||
static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data)
|
||||
{
|
||||
mem->drvpriv = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* spi_mem_get_drvdata() - get driver private data attached to a SPI mem
|
||||
* device
|
||||
* @mem: memory device
|
||||
*
|
||||
* Return: the data attached to the mem device.
|
||||
*/
|
||||
static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
|
||||
{
|
||||
return mem->drvpriv;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct spi_controller_mem_ops - SPI memory operations
|
||||
* @adjust_op_size: shrink the data xfer of an operation to match controller's
|
||||
* limitations (can be alignment or max RX/TX size
|
||||
* limitations)
|
||||
* @supports_op: check if an operation is supported by the controller
|
||||
* @exec_op: execute a SPI memory operation
|
||||
* not all driver provides supports_op(), so it can return -EOPNOTSUPP
|
||||
* if the op is not supported by the driver/controller
|
||||
* @get_name: get a custom name for the SPI mem device from the controller.
|
||||
* This might be needed if the controller driver has been ported
|
||||
* to use the SPI mem layer and a custom name is used to keep
|
||||
* mtdparts compatible.
|
||||
* Note that if the implementation of this function allocates memory
|
||||
* dynamically, then it should do so with devm_xxx(), as we don't
|
||||
* have a ->free_name() function.
|
||||
* @dirmap_create: create a direct mapping descriptor that can later be used to
|
||||
* access the memory device. This method is optional
|
||||
* @dirmap_destroy: destroy a memory descriptor previous created by
|
||||
* ->dirmap_create()
|
||||
* @dirmap_read: read data from the memory device using the direct mapping
|
||||
* created by ->dirmap_create(). The function can return less
|
||||
* data than requested (for example when the request is crossing
|
||||
* the currently mapped area), and the caller of
|
||||
* spi_mem_dirmap_read() is responsible for calling it again in
|
||||
* this case.
|
||||
* @dirmap_write: write data to the memory device using the direct mapping
|
||||
* created by ->dirmap_create(). The function can return less
|
||||
* data than requested (for example when the request is crossing
|
||||
* the currently mapped area), and the caller of
|
||||
* spi_mem_dirmap_write() is responsible for calling it again in
|
||||
* this case.
|
||||
* @poll_status: poll memory device status until (status & mask) == match or
|
||||
* when the timeout has expired. It fills the data buffer with
|
||||
* the last status value.
|
||||
*
|
||||
* This interface should be implemented by SPI controllers providing an
|
||||
* high-level interface to execute SPI memory operation, which is usually the
|
||||
* case for QSPI controllers.
|
||||
*
|
||||
* Note on ->dirmap_{read,write}(): drivers should avoid accessing the direct
|
||||
* mapping from the CPU because doing that can stall the CPU waiting for the
|
||||
* SPI mem transaction to finish, and this will make real-time maintainers
|
||||
* unhappy and might make your system less reactive. Instead, drivers should
|
||||
* use DMA to access this direct mapping.
|
||||
*/
|
||||
struct spi_controller_mem_ops {
|
||||
int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op);
|
||||
bool (*supports_op)(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op);
|
||||
int (*exec_op)(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op);
|
||||
const char *(*get_name)(struct spi_mem *mem);
|
||||
int (*dirmap_create)(struct spi_mem_dirmap_desc *desc);
|
||||
void (*dirmap_destroy)(struct spi_mem_dirmap_desc *desc);
|
||||
ssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *desc,
|
||||
u64 offs, size_t len, void *buf);
|
||||
ssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *desc,
|
||||
u64 offs, size_t len, const void *buf);
|
||||
int (*poll_status)(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op,
|
||||
u16 mask, u16 match,
|
||||
unsigned long initial_delay_us,
|
||||
unsigned long polling_rate_us,
|
||||
unsigned long timeout_ms);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_controller_mem_caps - SPI memory controller capabilities
|
||||
* @dtr: Supports DTR operations
|
||||
* @ecc: Supports operations with error correction
|
||||
* @swap16: Supports swapping bytes on a 16 bit boundary when configured in
|
||||
* Octal DTR
|
||||
* @per_op_freq: Supports per operation frequency switching
|
||||
*/
|
||||
struct spi_controller_mem_caps {
|
||||
bool dtr;
|
||||
bool ecc;
|
||||
bool swap16;
|
||||
bool per_op_freq;
|
||||
};
|
||||
|
||||
#define spi_mem_controller_is_capable(ctlr, cap) \
|
||||
((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
|
||||
|
||||
/**
|
||||
* struct spi_mem_driver - SPI memory driver
|
||||
* @spidrv: inherit from a SPI driver
|
||||
* @probe: probe a SPI memory. Usually where detection/initialization takes
|
||||
* place
|
||||
* @remove: remove a SPI memory
|
||||
* @shutdown: take appropriate action when the system is shutdown
|
||||
*
|
||||
* This is just a thin wrapper around a spi_driver. The core takes care of
|
||||
* allocating the spi_mem object and forwarding the probe/remove/shutdown
|
||||
* request to the spi_mem_driver. The reason we use this wrapper is because
|
||||
* we might have to stuff more information into the spi_mem struct to let
|
||||
* SPI controllers know more about the SPI memory they interact with, and
|
||||
* having this intermediate layer allows us to do that without adding more
|
||||
* useless fields to the spi_device object.
|
||||
*/
|
||||
struct spi_mem_driver {
|
||||
struct spi_driver spidrv;
|
||||
int (*probe)(struct spi_mem *mem);
|
||||
int (*remove)(struct spi_mem *mem);
|
||||
void (*shutdown)(struct spi_mem *mem);
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_MEM)
|
||||
int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
|
||||
const struct spi_mem_op *op,
|
||||
struct sg_table *sg);
|
||||
|
||||
void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
|
||||
const struct spi_mem_op *op,
|
||||
struct sg_table *sg);
|
||||
|
||||
bool spi_mem_default_supports_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op);
|
||||
#else
|
||||
static inline int
|
||||
spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
|
||||
const struct spi_mem_op *op,
|
||||
struct sg_table *sg)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline void
|
||||
spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
|
||||
const struct spi_mem_op *op,
|
||||
struct sg_table *sg)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
bool spi_mem_default_supports_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif /* CONFIG_SPI_MEM */
|
||||
|
||||
int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
|
||||
void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op);
|
||||
u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op);
|
||||
|
||||
bool spi_mem_supports_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op);
|
||||
|
||||
int spi_mem_exec_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op);
|
||||
|
||||
const char *spi_mem_get_name(struct spi_mem *mem);
|
||||
|
||||
struct spi_mem_dirmap_desc *
|
||||
spi_mem_dirmap_create(struct spi_mem *mem,
|
||||
const struct spi_mem_dirmap_info *info);
|
||||
void spi_mem_dirmap_destroy(struct spi_mem_dirmap_desc *desc);
|
||||
ssize_t spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
||||
u64 offs, size_t len, void *buf);
|
||||
ssize_t spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
|
||||
u64 offs, size_t len, const void *buf);
|
||||
struct spi_mem_dirmap_desc *
|
||||
devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem,
|
||||
const struct spi_mem_dirmap_info *info);
|
||||
void devm_spi_mem_dirmap_destroy(struct device *dev,
|
||||
struct spi_mem_dirmap_desc *desc);
|
||||
|
||||
int spi_mem_poll_status(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op,
|
||||
u16 mask, u16 match,
|
||||
unsigned long initial_delay_us,
|
||||
unsigned long polling_delay_us,
|
||||
u16 timeout_ms);
|
||||
|
||||
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
|
||||
struct module *owner);
|
||||
|
||||
void spi_mem_driver_unregister(struct spi_mem_driver *drv);
|
||||
|
||||
#define spi_mem_driver_register(__drv) \
|
||||
spi_mem_driver_register_with_owner(__drv, THIS_MODULE)
|
||||
|
||||
#define module_spi_mem_driver(__drv) \
|
||||
module_driver(__drv, spi_mem_driver_register, \
|
||||
spi_mem_driver_unregister)
|
||||
|
||||
#endif /* __LINUX_SPI_MEM_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __SPI_BITBANG_H
|
||||
#define __SPI_BITBANG_H
|
||||
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
typedef u32 (*spi_bb_txrx_word_fn)(struct spi_device *, unsigned int, u32, u8, unsigned int);
|
||||
|
||||
struct spi_bitbang {
|
||||
struct mutex lock;
|
||||
u8 busy;
|
||||
u8 use_dma;
|
||||
u16 flags; /* extra spi->mode support */
|
||||
|
||||
struct spi_controller *ctlr;
|
||||
|
||||
/* setup_transfer() changes clock and/or wordsize to match settings
|
||||
* for this transfer; zeroes restore defaults from spi_device.
|
||||
*/
|
||||
int (*setup_transfer)(struct spi_device *spi,
|
||||
struct spi_transfer *t);
|
||||
|
||||
void (*chipselect)(struct spi_device *spi, int is_on);
|
||||
#define BITBANG_CS_ACTIVE 1 /* normally nCS, active low */
|
||||
#define BITBANG_CS_INACTIVE 0
|
||||
|
||||
void (*set_mosi_idle)(struct spi_device *spi);
|
||||
/* txrx_bufs() may handle dma mapping for transfers that don't
|
||||
* already have one (transfer.{tx,rx}_dma is zero), or use PIO
|
||||
*/
|
||||
int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
|
||||
|
||||
/* txrx_word[SPI_MODE_*]() just looks like a shift register */
|
||||
spi_bb_txrx_word_fn txrx_word[SPI_MODE_X_MASK + 1];
|
||||
|
||||
int (*set_line_direction)(struct spi_device *spi, bool output);
|
||||
};
|
||||
|
||||
/* you can call these default bitbang->master methods from your custom
|
||||
* methods, if you like.
|
||||
*/
|
||||
extern int spi_bitbang_setup(struct spi_device *spi);
|
||||
extern void spi_bitbang_cleanup(struct spi_device *spi);
|
||||
extern int spi_bitbang_setup_transfer(struct spi_device *spi,
|
||||
struct spi_transfer *t);
|
||||
|
||||
/* start or stop queue processing */
|
||||
extern int spi_bitbang_start(struct spi_bitbang *spi);
|
||||
extern int spi_bitbang_init(struct spi_bitbang *spi);
|
||||
extern void spi_bitbang_stop(struct spi_bitbang *spi);
|
||||
|
||||
#endif /* __SPI_BITBANG_H */
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SPI_GPIO_H
|
||||
#define __LINUX_SPI_GPIO_H
|
||||
|
||||
/*
|
||||
* For each bitbanged SPI bus, set up a platform_device node with:
|
||||
* - name "spi_gpio"
|
||||
* - id the same as the SPI bus number it implements
|
||||
* - dev.platform data pointing to a struct spi_gpio_platform_data
|
||||
*
|
||||
* Use spi_board_info with these busses in the usual way.
|
||||
*
|
||||
* If the bitbanged bus is later switched to a "native" controller,
|
||||
* that platform_device and controller_data should be removed.
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct spi_gpio_platform_data - parameter for bitbanged SPI host controller
|
||||
* @num_chipselect: how many target devices to allow
|
||||
*/
|
||||
struct spi_gpio_platform_data {
|
||||
u16 num_chipselect;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_SPI_GPIO_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _LINUX_SPI_SPI_OC_TINY_H
|
||||
#define _LINUX_SPI_SPI_OC_TINY_H
|
||||
|
||||
/**
|
||||
* struct tiny_spi_platform_data - platform data of the OpenCores tiny SPI
|
||||
* @freq: input clock freq to the core.
|
||||
* @baudwidth: baud rate divider width of the core.
|
||||
*
|
||||
* freq and baudwidth are used only if the divider is programmable.
|
||||
*/
|
||||
struct tiny_spi_platform_data {
|
||||
unsigned int freq;
|
||||
unsigned int baudwidth;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_SPI_SPI_OC_TINY_H */
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __TDO24M_H__
|
||||
#define __TDO24M_H__
|
||||
|
||||
enum tdo24m_model {
|
||||
TDO24M,
|
||||
TDO35S,
|
||||
};
|
||||
|
||||
struct tdo24m_platform_data {
|
||||
enum tdo24m_model model;
|
||||
};
|
||||
|
||||
#endif /* __TDO24M_H__ */
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* tle62x0.h - platform glue to Infineon TLE62x0 driver chips
|
||||
*
|
||||
* Copyright 2007 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*/
|
||||
|
||||
struct tle62x0_pdata {
|
||||
unsigned int init_state;
|
||||
unsigned int gpio_count;
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SPI_XILINX_SPI_H
|
||||
#define __LINUX_SPI_XILINX_SPI_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct spi_board_info;
|
||||
|
||||
/**
|
||||
* struct xspi_platform_data - Platform data of the Xilinx SPI driver
|
||||
* @devices: Devices to add when the driver is probed.
|
||||
* @num_devices: Number of devices in the devices array.
|
||||
* @num_chipselect: Number of chip select by the IP.
|
||||
* @bits_per_word: Number of bits per word.
|
||||
* @force_irq: If set, forces QSPI transaction requirements.
|
||||
*/
|
||||
struct xspi_platform_data {
|
||||
struct spi_board_info *devices;
|
||||
u8 num_devices;
|
||||
u8 num_chipselect;
|
||||
u8 bits_per_word;
|
||||
bool force_irq;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_SPI_XILINX_SPI_H */
|
||||
Reference in New Issue
Block a user