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restore lost packages from 0.2.3 + fix overwritten 0.2.4 files

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- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.)
- Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber)
- Restore 20+ local/scripts (audit, lint, test, build helpers)
- Restore src/cook/scheduler.rs, status.rs, gnu-config/
- Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh
- Recover TLC source from HEAD (was overwritten by 0.2.3 checkout)
- Recover 11 local/docs plans from HEAD (were overwritten)
- Recover qt6-wayland-smoke symlink from HEAD
- Fix MOTD: remove garbled ASCII art, use clean text
- Update version: 0.2.0 -> 0.2.4 in os-release, motd, config
- Reduce filesystem_size: 1536 -> 512 MiB
- Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages
- Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
vasilito
2026-06-19 12:39:14 +03:00
parent ffbe098ef8
commit dc68054305
6418 changed files with 7066233 additions and 8670 deletions
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local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/apr.h
+197
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@@ -0,0 +1,197 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_APR_H_
#define __QCOM_APR_H_
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,gpr.h>
extern const struct bus_type aprbus;
#define APR_HDR_LEN(hdr_len) ((hdr_len)/4)
/*
* HEADER field
* version:0:3
* header_size : 4:7
* message_type : 8:9
* reserved: 10:15
*/
#define APR_HDR_FIELD(msg_type, hdr_len, ver)\
(((msg_type & 0x3) << 8) | ((hdr_len & 0xF) << 4) | (ver & 0xF))
#define APR_HDR_SIZE sizeof(struct apr_hdr)
#define APR_SEQ_CMD_HDR_FIELD APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, \
APR_HDR_LEN(APR_HDR_SIZE), \
APR_PKT_VER)
/* Version */
#define APR_PKT_VER 0x0
/* Command and Response Types */
#define APR_MSG_TYPE_EVENT 0x0
#define APR_MSG_TYPE_CMD_RSP 0x1
#define APR_MSG_TYPE_SEQ_CMD 0x2
#define APR_MSG_TYPE_NSEQ_CMD 0x3
#define APR_MSG_TYPE_MAX 0x04
/* APR Basic Response Message */
#define APR_BASIC_RSP_RESULT 0x000110E8
#define APR_RSP_ACCEPTED 0x000100BE
struct aprv2_ibasic_rsp_result_t {
uint32_t opcode;
uint32_t status;
};
/* hdr field Ver [0:3], Size [4:7], Message type [8:10] */
#define APR_HDR_FIELD_VER(h) (h & 0x000F)
#define APR_HDR_FIELD_SIZE(h) ((h & 0x00F0) >> 4)
#define APR_HDR_FIELD_SIZE_BYTES(h) (((h & 0x00F0) >> 4) * 4)
#define APR_HDR_FIELD_MT(h) ((h & 0x0300) >> 8)
struct apr_hdr {
uint16_t hdr_field;
uint16_t pkt_size;
uint8_t src_svc;
uint8_t src_domain;
uint16_t src_port;
uint8_t dest_svc;
uint8_t dest_domain;
uint16_t dest_port;
uint32_t token;
uint32_t opcode;
} __packed;
struct apr_pkt {
struct apr_hdr hdr;
uint8_t payload[];
};
struct apr_resp_pkt {
struct apr_hdr hdr;
void *payload;
int payload_size;
};
struct gpr_hdr {
uint32_t version:4;
uint32_t hdr_size:4;
uint32_t pkt_size:24;
uint32_t dest_domain:8;
uint32_t src_domain:8;
uint32_t reserved:16;
uint32_t src_port;
uint32_t dest_port;
uint32_t token;
uint32_t opcode;
} __packed;
struct gpr_pkt {
struct gpr_hdr hdr;
uint32_t payload[];
};
struct gpr_resp_pkt {
struct gpr_hdr hdr;
void *payload;
int payload_size;
};
#define GPR_HDR_SIZE sizeof(struct gpr_hdr)
#define GPR_PKT_VER 0x0
#define GPR_PKT_HEADER_WORD_SIZE ((sizeof(struct gpr_pkt) + 3) >> 2)
#define GPR_PKT_HEADER_BYTE_SIZE (GPR_PKT_HEADER_WORD_SIZE << 2)
#define GPR_BASIC_RSP_RESULT 0x02001005
struct gpr_ibasic_rsp_result_t {
uint32_t opcode;
uint32_t status;
};
#define GPR_BASIC_EVT_ACCEPTED 0x02001006
struct gpr_ibasic_rsp_accepted_t {
uint32_t opcode;
};
/* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */
#define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF)
#define APR_SVC_MINOR_VERSION(v) (v & 0xFF)
typedef int (*gpr_port_cb) (const struct gpr_resp_pkt *d, void *priv, int op);
struct packet_router;
struct pkt_router_svc {
struct device *dev;
gpr_port_cb callback;
struct packet_router *pr;
spinlock_t lock;
int id;
void *priv;
};
typedef struct pkt_router_svc gpr_port_t;
struct apr_device {
struct device dev;
uint16_t svc_id;
uint16_t domain_id;
uint32_t version;
char name[APR_NAME_SIZE];
const char *service_path;
struct pkt_router_svc svc;
struct list_head node;
};
typedef struct apr_device gpr_device_t;
#define to_apr_device(d) container_of(d, struct apr_device, dev)
#define svc_to_apr_device(d) container_of(d, struct apr_device, svc)
struct apr_driver {
int (*probe)(struct apr_device *sl);
void (*remove)(struct apr_device *sl);
int (*callback)(struct apr_device *a,
const struct apr_resp_pkt *d);
gpr_port_cb gpr_callback;
struct device_driver driver;
const struct apr_device_id *id_table;
};
typedef struct apr_driver gpr_driver_t;
#define to_apr_driver(d) container_of_const(d, struct apr_driver, driver)
/*
* use a macro to avoid include chaining to get THIS_MODULE
*/
#define apr_driver_register(drv) __apr_driver_register(drv, THIS_MODULE)
int __apr_driver_register(struct apr_driver *drv, struct module *owner);
void apr_driver_unregister(struct apr_driver *drv);
/**
* module_apr_driver() - Helper macro for registering a aprbus driver
* @__apr_driver: apr_driver struct
*
* Helper macro for aprbus drivers which do not do anything special in
* module init/exit. This eliminates a lot of boilerplate. Each module
* may only use this macro once, and calling it replaces module_init()
* and module_exit()
*/
#define module_apr_driver(__apr_driver) \
module_driver(__apr_driver, apr_driver_register, \
apr_driver_unregister)
#define module_gpr_driver(__gpr_driver) module_apr_driver(__gpr_driver)
int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt);
gpr_port_t *gpr_alloc_port(gpr_device_t *gdev, struct device *dev,
gpr_port_cb cb, void *priv);
void gpr_free_port(gpr_port_t *port);
int gpr_send_port_pkt(gpr_port_t *port, const struct gpr_pkt *pkt);
int gpr_send_pkt(gpr_device_t *gdev, const struct gpr_pkt *pkt);
#endif /* __QCOM_APR_H_ */
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/geni-se.h
+539
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@@ -0,0 +1,539 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
#include <linux/interconnect.h>
/**
* enum geni_se_xfer_mode: Transfer modes supported by Serial Engines
*
* @GENI_SE_INVALID: Invalid mode
* @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
* by programmed IO method
* @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred
* with SE by DMAengine internal to SE
* @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine
* configured by a firmware residing on a GSI engine. This DMA name is
* interchangeably used as GSI or GPI which seem to imply the same DMAengine
*/
enum geni_se_xfer_mode {
GENI_SE_INVALID,
GENI_SE_FIFO,
GENI_SE_DMA,
GENI_GPI_DMA,
};
/* Protocols supported by GENI Serial Engines */
enum geni_se_protocol_type {
GENI_SE_NONE,
GENI_SE_SPI,
GENI_SE_UART,
GENI_SE_I2C,
GENI_SE_I3C,
GENI_SE_SPI_SLAVE,
GENI_SE_INVALID_PROTO = 255,
};
struct geni_wrapper;
struct clk;
enum geni_icc_path_index {
GENI_TO_CORE,
CPU_TO_GENI,
GENI_TO_DDR
};
struct geni_icc_path {
struct icc_path *path;
unsigned int avg_bw;
};
/**
* struct geni_se - GENI Serial Engine
* @base: Base Address of the Serial Engine's register block
* @dev: Pointer to the Serial Engine device
* @wrapper: Pointer to the parent QUP Wrapper core
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
* @icc_paths: Array of ICC paths for SE
*/
struct geni_se {
void __iomem *base;
struct device *dev;
struct geni_wrapper *wrapper;
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
struct geni_icc_path icc_paths[3];
};
/* Common SE registers */
#define GENI_FORCE_DEFAULT_REG 0x20
#define GENI_OUTPUT_CTRL 0x24
#define SE_GENI_STATUS 0x40
#define GENI_SER_M_CLK_CFG 0x48
#define GENI_SER_S_CLK_CFG 0x4c
#define GENI_IF_DISABLE_RO 0x64
#define GENI_FW_REVISION_RO 0x68
#define SE_GENI_CLK_SEL 0x7c
#define SE_GENI_CFG_SEQ_START 0x84
#define SE_GENI_DMA_MODE_EN 0x258
#define SE_GENI_M_CMD0 0x600
#define SE_GENI_M_CMD_CTRL_REG 0x604
#define SE_GENI_M_IRQ_STATUS 0x610
#define SE_GENI_M_IRQ_EN 0x614
#define SE_GENI_M_IRQ_CLEAR 0x618
#define SE_GENI_M_IRQ_EN_SET 0x61c
#define SE_GENI_M_IRQ_EN_CLEAR 0x620
#define SE_GENI_S_CMD0 0x630
#define SE_GENI_S_CMD_CTRL_REG 0x634
#define SE_GENI_S_IRQ_STATUS 0x640
#define SE_GENI_S_IRQ_EN 0x644
#define SE_GENI_S_IRQ_CLEAR 0x648
#define SE_GENI_S_IRQ_EN_SET 0x64c
#define SE_GENI_S_IRQ_EN_CLEAR 0x650
#define SE_GENI_TX_FIFOn 0x700
#define SE_GENI_RX_FIFOn 0x780
#define SE_GENI_TX_FIFO_STATUS 0x800
#define SE_GENI_RX_FIFO_STATUS 0x804
#define SE_GENI_TX_WATERMARK_REG 0x80c
#define SE_GENI_RX_WATERMARK_REG 0x810
#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
#define SE_GENI_IOS 0x908
#define SE_GENI_M_GP_LENGTH 0x910
#define SE_GENI_S_GP_LENGTH 0x914
#define SE_DMA_TX_IRQ_STAT 0xc40
#define SE_DMA_TX_IRQ_CLR 0xc44
#define SE_DMA_TX_FSM_RST 0xc58
#define SE_DMA_RX_IRQ_STAT 0xd40
#define SE_DMA_RX_IRQ_CLR 0xd44
#define SE_DMA_RX_LEN_IN 0xd54
#define SE_DMA_RX_FSM_RST 0xd58
#define SE_HW_PARAM_0 0xe24
#define SE_HW_PARAM_1 0xe28
/* GENI_FORCE_DEFAULT_REG fields */
#define FORCE_DEFAULT BIT(0)
/* GENI_OUTPUT_CTRL fields */
#define GENI_IO_MUX_0_EN BIT(0)
/* GENI_STATUS fields */
#define M_GENI_CMD_ACTIVE BIT(0)
#define S_GENI_CMD_ACTIVE BIT(12)
/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
#define SER_CLK_EN BIT(0)
#define CLK_DIV_MSK GENMASK(15, 4)
#define CLK_DIV_SHFT 4
/* GENI_IF_DISABLE_RO fields */
#define FIFO_IF_DISABLE (BIT(0))
/* GENI_FW_REVISION_RO fields */
#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
#define FW_REV_PROTOCOL_SHFT 8
/* GENI_CLK_SEL fields */
#define CLK_SEL_MSK GENMASK(2, 0)
/* SE_GENI_CFG_SEQ_START fields */
#define START_TRIGGER BIT(0)
/* SE_GENI_DMA_MODE_EN */
#define GENI_DMA_MODE_EN BIT(0)
/* GENI_M_CMD0 fields */
#define M_OPCODE_MSK GENMASK(31, 27)
#define M_OPCODE_SHFT 27
#define M_PARAMS_MSK GENMASK(26, 0)
/* GENI_M_CMD_CTRL_REG */
#define M_GENI_CMD_CANCEL BIT(2)
#define M_GENI_CMD_ABORT BIT(1)
#define M_GENI_DISABLE BIT(0)
/* GENI_S_CMD0 fields */
#define S_OPCODE_MSK GENMASK(31, 27)
#define S_OPCODE_SHFT 27
#define S_PARAMS_MSK GENMASK(26, 0)
/* GENI_S_CMD_CTRL_REG */
#define S_GENI_CMD_CANCEL BIT(2)
#define S_GENI_CMD_ABORT BIT(1)
#define S_GENI_DISABLE BIT(0)
/* GENI_M_IRQ_EN fields */
#define M_CMD_DONE_EN BIT(0)
#define M_CMD_OVERRUN_EN BIT(1)
#define M_ILLEGAL_CMD_EN BIT(2)
#define M_CMD_FAILURE_EN BIT(3)
#define M_CMD_CANCEL_EN BIT(4)
#define M_CMD_ABORT_EN BIT(5)
#define M_TIMESTAMP_EN BIT(6)
#define M_RX_IRQ_EN BIT(7)
#define M_GP_SYNC_IRQ_0_EN BIT(8)
#define M_GP_IRQ_0_EN BIT(9)
#define M_GP_IRQ_1_EN BIT(10)
#define M_GP_IRQ_2_EN BIT(11)
#define M_GP_IRQ_3_EN BIT(12)
#define M_GP_IRQ_4_EN BIT(13)
#define M_GP_IRQ_5_EN BIT(14)
#define M_TX_FIFO_NOT_EMPTY_EN BIT(21)
#define M_IO_DATA_DEASSERT_EN BIT(22)
#define M_IO_DATA_ASSERT_EN BIT(23)
#define M_RX_FIFO_RD_ERR_EN BIT(24)
#define M_RX_FIFO_WR_ERR_EN BIT(25)
#define M_RX_FIFO_WATERMARK_EN BIT(26)
#define M_RX_FIFO_LAST_EN BIT(27)
#define M_TX_FIFO_RD_ERR_EN BIT(28)
#define M_TX_FIFO_WR_ERR_EN BIT(29)
#define M_TX_FIFO_WATERMARK_EN BIT(30)
#define M_SEC_IRQ_EN BIT(31)
#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
M_IO_DATA_DEASSERT_EN | \
M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
M_TX_FIFO_WR_ERR_EN)
/* GENI_S_IRQ_EN fields */
#define S_CMD_DONE_EN BIT(0)
#define S_CMD_OVERRUN_EN BIT(1)
#define S_ILLEGAL_CMD_EN BIT(2)
#define S_CMD_FAILURE_EN BIT(3)
#define S_CMD_CANCEL_EN BIT(4)
#define S_CMD_ABORT_EN BIT(5)
#define S_GP_SYNC_IRQ_0_EN BIT(8)
#define S_GP_IRQ_0_EN BIT(9)
#define S_GP_IRQ_1_EN BIT(10)
#define S_GP_IRQ_2_EN BIT(11)
#define S_GP_IRQ_3_EN BIT(12)
#define S_GP_IRQ_4_EN BIT(13)
#define S_GP_IRQ_5_EN BIT(14)
#define S_IO_DATA_DEASSERT_EN BIT(22)
#define S_IO_DATA_ASSERT_EN BIT(23)
#define S_RX_FIFO_RD_ERR_EN BIT(24)
#define S_RX_FIFO_WR_ERR_EN BIT(25)
#define S_RX_FIFO_WATERMARK_EN BIT(26)
#define S_RX_FIFO_LAST_EN BIT(27)
#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
#define WATERMARK_MSK GENMASK(5, 0)
/* GENI_TX_FIFO_STATUS fields */
#define TX_FIFO_WC GENMASK(27, 0)
/* GENI_RX_FIFO_STATUS fields */
#define RX_LAST BIT(31)
#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
#define RX_LAST_BYTE_VALID_SHFT 28
#define RX_FIFO_WC_MSK GENMASK(24, 0)
/* SE_GENI_IOS fields */
#define IO2_DATA_IN BIT(1)
#define RX_DATA_IN BIT(0)
/* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */
#define GP_LENGTH GENMASK(31, 0)
/* SE_DMA_TX_IRQ_STAT Register fields */
#define TX_DMA_DONE BIT(0)
#define TX_EOT BIT(1)
#define TX_SBE BIT(2)
#define TX_RESET_DONE BIT(3)
/* SE_DMA_RX_IRQ_STAT Register fields */
#define RX_DMA_DONE BIT(0)
#define RX_EOT BIT(1)
#define RX_SBE BIT(2)
#define RX_RESET_DONE BIT(3)
#define RX_FLUSH_DONE BIT(4)
#define RX_DMA_PARITY_ERR BIT(5)
#define RX_DMA_BREAK GENMASK(8, 7)
#define RX_GENI_GP_IRQ GENMASK(10, 5)
#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
#define RX_GENI_CANCEL_IRQ BIT(14)
/* SE_HW_PARAM_0 fields */
#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
#define TX_FIFO_WIDTH_SHFT 24
/*
* For QUP HW Version >= 3.10 Tx fifo depth support is increased
* to 256bytes and corresponding bits are 16 to 23
*/
#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
#define TX_FIFO_DEPTH_SHFT 16
/* SE_HW_PARAM_1 fields */
#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
#define RX_FIFO_WIDTH_SHFT 24
/*
* For QUP HW Version >= 3.10 Rx fifo depth support is increased
* to 256bytes and corresponding bits are 16 to 23
*/
#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
#define RX_FIFO_DEPTH_SHFT 16
#define HW_VER_MAJOR_MASK GENMASK(31, 28)
#define HW_VER_MAJOR_SHFT 28
#define HW_VER_MINOR_MASK GENMASK(27, 16)
#define HW_VER_MINOR_SHFT 16
#define HW_VER_STEP_MASK GENMASK(15, 0)
#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
/* QUP SE VERSION value for major number 2 and minor number 5 */
#define QUP_SE_VERSION_2_5 0x20050000
/*
* Define bandwidth thresholds that cause the underlying Core 2X interconnect
* clock to run at the named frequency. These baseline values are recommended
* by the hardware team, and are not dynamically scaled with GENI bandwidth
* beyond basic on/off.
*/
#define CORE_2X_19_2_MHZ 960
#define CORE_2X_50_MHZ 2500
#define CORE_2X_100_MHZ 5000
#define CORE_2X_150_MHZ 7500
#define CORE_2X_200_MHZ 10000
#define CORE_2X_236_MHZ 16383
#define GENI_DEFAULT_BW Bps_to_icc(1000)
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
u32 geni_se_get_qup_hw_version(struct geni_se *se);
/**
* geni_se_read_proto() - Read the protocol configured for a serial engine
* @se: Pointer to the concerned serial engine.
*
* Return: Protocol value as configured in the serial engine.
*/
static inline u32 geni_se_read_proto(struct geni_se *se)
{
u32 val;
val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
}
/**
* geni_se_setup_m_cmd() - Setup the primary sequencer
* @se: Pointer to the concerned serial engine.
* @cmd: Command/Operation to setup in the primary sequencer.
* @params: Parameter for the sequencer command.
*
* This function is used to configure the primary sequencer with the
* command and its associated parameters.
*/
static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
{
u32 m_cmd;
m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
writel(m_cmd, se->base + SE_GENI_M_CMD0);
}
/**
* geni_se_setup_s_cmd() - Setup the secondary sequencer
* @se: Pointer to the concerned serial engine.
* @cmd: Command/Operation to setup in the secondary sequencer.
* @params: Parameter for the sequencer command.
*
* This function is used to configure the secondary sequencer with the
* command and its associated parameters.
*/
static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
{
u32 s_cmd;
s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
s_cmd |= (cmd << S_OPCODE_SHFT);
s_cmd |= (params & S_PARAMS_MSK);
writel(s_cmd, se->base + SE_GENI_S_CMD0);
}
/**
* geni_se_cancel_m_cmd() - Cancel the command configured in the primary
* sequencer
* @se: Pointer to the concerned serial engine.
*
* This function is used to cancel the currently configured command in the
* primary sequencer.
*/
static inline void geni_se_cancel_m_cmd(struct geni_se *se)
{
writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
}
/**
* geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
* sequencer
* @se: Pointer to the concerned serial engine.
*
* This function is used to cancel the currently configured command in the
* secondary sequencer.
*/
static inline void geni_se_cancel_s_cmd(struct geni_se *se)
{
writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
}
/**
* geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
* @se: Pointer to the concerned serial engine.
*
* This function is used to force abort the currently configured command in the
* primary sequencer.
*/
static inline void geni_se_abort_m_cmd(struct geni_se *se)
{
writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
}
/**
* geni_se_abort_s_cmd() - Abort the command configured in the secondary
* sequencer
* @se: Pointer to the concerned serial engine.
*
* This function is used to force abort the currently configured command in the
* secondary sequencer.
*/
static inline void geni_se_abort_s_cmd(struct geni_se *se)
{
writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
}
/**
* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
* based on QUP HW version
* @se: Pointer to the concerned serial engine.
*
* This function is used to get the depth i.e. number of elements in the
* TX fifo of the serial engine.
*
* Return: TX fifo depth in units of FIFO words.
*/
static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
{
u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask;
hw_version = geni_se_get_qup_hw_version(se);
hw_major = GENI_SE_VERSION_MAJOR(hw_version);
hw_minor = GENI_SE_VERSION_MINOR(hw_version);
if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES;
else
tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK;
val = readl_relaxed(se->base + SE_HW_PARAM_0);
return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT;
}
/**
* geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
* @se: Pointer to the concerned serial engine.
*
* This function is used to get the width i.e. word size per element in the
* TX fifo of the serial engine.
*
* Return: TX fifo width in bits
*/
static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
{
u32 val;
val = readl_relaxed(se->base + SE_HW_PARAM_0);
return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
}
/**
* geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
* based on QUP HW version
* @se: Pointer to the concerned serial engine.
*
* This function is used to get the depth i.e. number of elements in the
* RX fifo of the serial engine.
*
* Return: RX fifo depth in units of FIFO words
*/
static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
{
u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask;
hw_version = geni_se_get_qup_hw_version(se);
hw_major = GENI_SE_VERSION_MAJOR(hw_version);
hw_minor = GENI_SE_VERSION_MINOR(hw_version);
if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES;
else
rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK;
val = readl_relaxed(se->base + SE_HW_PARAM_1);
return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT;
}
void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
int geni_se_resources_off(struct geni_se *se);
int geni_se_resources_on(struct geni_se *se);
int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
unsigned int *index, unsigned long *res_freq,
bool exact);
void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len);
int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
dma_addr_t *iova);
void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len);
int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
dma_addr_t *iova);
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
int geni_icc_get(struct geni_se *se, const char *icc_ddr);
int geni_icc_set_bw(struct geni_se *se);
void geni_icc_set_tag(struct geni_se *se, u32 tag);
int geni_icc_enable(struct geni_se *se);
int geni_icc_disable(struct geni_se *se);
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __QCOM_IRQ_H
#define __QCOM_IRQ_H
#include <linux/irqdomain.h>
#define GPIO_NO_WAKE_IRQ ~0U
/*
* QCOM specific IRQ domain flags that distinguishes the handling of wakeup
* capable interrupts by different interrupt controllers.
*
* IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the
* interrupt configuration is done at PDC
* IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM
*/
#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)
/**
* irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
* configuration
* @d: irq domain
*
* This QCOM specific irq domain call returns if the interrupt controller
* requires the interrupt be masked at the child interrupt controller.
*/
static inline bool irq_domain_qcom_handle_wakeup(const struct irq_domain *d)
{
return (d->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
}
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/llcc-qcom.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
*/
#include <linux/platform_device.h>
#ifndef __LLCC_QCOM__
#define __LLCC_QCOM__
#define LLCC_CPUSS 1
#define LLCC_VIDSC0 2
#define LLCC_VIDSC1 3
#define LLCC_ROTATOR 4
#define LLCC_VOICE 5
#define LLCC_AUDIO 6
#define LLCC_MDMHPGRW 7
#define LLCC_MDM 8
#define LLCC_MODHW 9
#define LLCC_CMPT 10
#define LLCC_GPUHTW 11
#define LLCC_GPU 12
#define LLCC_MMUHWT 13
#define LLCC_CMPTDMA 15
#define LLCC_DISP 16
#define LLCC_VIDFW 17
#define LLCC_CAMFW 18
#define LLCC_MDMHPFX 20
#define LLCC_MDMPNG 21
#define LLCC_AUDHW 22
#define LLCC_NPU 23
#define LLCC_WLHW 24
#define LLCC_PIMEM 25
#define LLCC_ECC 26
#define LLCC_CVP 28
#define LLCC_MODPE 29
#define LLCC_APTCM 30
#define LLCC_WRCACHE 31
#define LLCC_CVPFW 32
#define LLCC_CPUSS1 33
#define LLCC_CAMEXP0 34
#define LLCC_CPUMTE 35
#define LLCC_CPUHWT 36
#define LLCC_MDMCLAD2 37
#define LLCC_CAMEXP1 38
#define LLCC_CMPTHCP 39
#define LLCC_LCPDARE 40
#define LLCC_AENPU 45
#define LLCC_ISLAND1 46
#define LLCC_ISLAND2 47
#define LLCC_ISLAND3 48
#define LLCC_ISLAND4 49
#define LLCC_CAMEXP2 50
#define LLCC_CAMEXP3 51
#define LLCC_CAMEXP4 52
#define LLCC_DISP_WB 53
#define LLCC_DISP_1 54
#define LLCC_VIEYE 57
#define LLCC_VIDPTH 58
#define LLCC_GPUMV 59
#define LLCC_EVA_LEFT 60
#define LLCC_EVA_RIGHT 61
#define LLCC_EVAGAIN 62
#define LLCC_VIPTH 63
#define LLCC_VIDVSP 64
#define LLCC_DISP_LEFT 65
#define LLCC_DISP_RIGHT 66
#define LLCC_EVCS_LEFT 67
#define LLCC_EVCS_RIGHT 68
#define LLCC_SPAD 69
#define LLCC_VIDDEC 70
#define LLCC_CAMOFE 71
#define LLCC_CAMRTIP 72
#define LLCC_CAMSRTIP 73
#define LLCC_CAMRTRF 74
#define LLCC_CAMSRTRF 75
#define LLCC_OOBM_NS 81
#define LLCC_OOBM_S 82
#define LLCC_VIDEO_APV 83
#define LLCC_COMPUTE1 87
#define LLCC_CPUSS_OPP 88
#define LLCC_CPUSSMPAM 89
#define LLCC_VIDSC_VSP1 91
#define LLCC_CAM_IPE_STROV 92
#define LLCC_CAM_OFE_STROV 93
#define LLCC_CPUSS_HEU 94
#define LLCC_PCIE_TCU 97
#define LLCC_MDM_PNG_FIXED 100
/**
* struct llcc_slice_desc - Cache slice descriptor
* @slice_id: llcc slice id
* @slice_size: Size allocated for the llcc slice
* @refcount: Atomic counter to track activate/deactivate calls
*/
struct llcc_slice_desc {
u32 slice_id;
size_t slice_size;
refcount_t refcount;
};
/**
* struct llcc_edac_reg_data - llcc edac registers data for each error type
* @name: Name of the error
* @reg_cnt: Number of registers
* @count_mask: Mask value to get the error count
* @ways_mask: Mask value to get the error ways
* @count_shift: Shift value to get the error count
* @ways_shift: Shift value to get the error ways
*/
struct llcc_edac_reg_data {
char *name;
u32 reg_cnt;
u32 count_mask;
u32 ways_mask;
u8 count_shift;
u8 ways_shift;
};
struct llcc_edac_reg_offset {
/* LLCC TRP registers */
u32 trp_ecc_error_status0;
u32 trp_ecc_error_status1;
u32 trp_ecc_sb_err_syn0;
u32 trp_ecc_db_err_syn0;
u32 trp_ecc_error_cntr_clear;
u32 trp_interrupt_0_status;
u32 trp_interrupt_0_clear;
u32 trp_interrupt_0_enable;
/* LLCC Common registers */
u32 cmn_status0;
u32 cmn_interrupt_0_enable;
u32 cmn_interrupt_2_enable;
/* LLCC DRP registers */
u32 drp_ecc_error_cfg;
u32 drp_ecc_error_cntr_clear;
u32 drp_interrupt_status;
u32 drp_interrupt_clear;
u32 drp_interrupt_enable;
u32 drp_ecc_error_status0;
u32 drp_ecc_error_status1;
u32 drp_ecc_sb_err_syn0;
u32 drp_ecc_db_err_syn0;
};
/**
* struct llcc_drv_data - Data associated with the llcc driver
* @regmaps: regmaps associated with the llcc device
* @bcast_regmap: regmap associated with llcc broadcast OR offset
* @bcast_and_regmap: regmap associated with llcc broadcast AND offset
* @cfg: pointer to the data structure for slice configuration
* @edac_reg_offset: Offset of the LLCC EDAC registers
* @lock: mutex associated with each slice
* @cfg_size: size of the config data table
* @num_banks: Number of llcc banks
* @ecc_irq: interrupt for llcc cache error detection and reporting
* @ecc_irq_configured: 'True' if firmware has already configured the irq propagation
* @desc: Array pointer of pre-allocated LLCC slice descriptors
* @version: Indicates the LLCC version
*/
struct llcc_drv_data {
struct regmap **regmaps;
struct regmap *bcast_regmap;
struct regmap *bcast_and_regmap;
const struct llcc_slice_config *cfg;
const struct llcc_edac_reg_offset *edac_reg_offset;
struct mutex lock;
u32 cfg_size;
u32 num_banks;
int ecc_irq;
bool ecc_irq_configured;
u32 version;
struct llcc_slice_desc *desc;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)
/**
* llcc_slice_getd - get llcc slice descriptor
* @uid: usecase_id of the client
*/
struct llcc_slice_desc *llcc_slice_getd(u32 uid);
/**
* llcc_slice_putd - llcc slice descritpor
* @desc: Pointer to llcc slice descriptor
*/
void llcc_slice_putd(struct llcc_slice_desc *desc);
/**
* llcc_get_slice_id - get slice id
* @desc: Pointer to llcc slice descriptor
*/
int llcc_get_slice_id(struct llcc_slice_desc *desc);
/**
* llcc_get_slice_size - llcc slice size
* @desc: Pointer to llcc slice descriptor
*/
size_t llcc_get_slice_size(struct llcc_slice_desc *desc);
/**
* llcc_slice_activate - Activate the llcc slice
* @desc: Pointer to llcc slice descriptor
*/
int llcc_slice_activate(struct llcc_slice_desc *desc);
/**
* llcc_slice_deactivate - Deactivate the llcc slice
* @desc: Pointer to llcc slice descriptor
*/
int llcc_slice_deactivate(struct llcc_slice_desc *desc);
#else
static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid)
{
return NULL;
}
static inline void llcc_slice_putd(struct llcc_slice_desc *desc)
{
};
static inline int llcc_get_slice_id(struct llcc_slice_desc *desc)
{
return -EINVAL;
}
static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
{
return 0;
}
static inline int llcc_slice_activate(struct llcc_slice_desc *desc)
{
return -EINVAL;
}
static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc)
{
return -EINVAL;
}
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/mdt_loader.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_MDT_LOADER_H__
#define __QCOM_MDT_LOADER_H__
#include <linux/types.h>
#define QCOM_MDT_TYPE_MASK (7 << 24)
#define QCOM_MDT_TYPE_HASH (2 << 24)
#define QCOM_MDT_RELOCATABLE BIT(27)
struct device;
struct firmware;
struct qcom_scm_pas_context;
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
ssize_t qcom_mdt_get_size(const struct firmware *fw);
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base);
int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
const char *firmware, void *mem_region, phys_addr_t *reloc_base);
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
const char *fw_name, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base);
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
const char *fw_name, struct device *dev);
#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
{
return -ENODEV;
}
static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id,
void *mem_region, phys_addr_t mem_phys,
size_t mem_size, phys_addr_t *reloc_base)
{
return -ENODEV;
}
static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx,
const struct firmware *fw, const char *firmware,
void *mem_region, phys_addr_t *reloc_base)
{
return -ENODEV;
}
static inline int qcom_mdt_load_no_init(struct device *dev,
const struct firmware *fw,
const char *fw_name, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base)
{
return -ENODEV;
}
static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
size_t *data_len, const char *fw_name,
struct device *dev)
{
return ERR_PTR(-ENODEV);
}
#endif /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/pdr.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_PDR_HELPER__
#define __QCOM_PDR_HELPER__
#include <linux/soc/qcom/qmi.h>
#define SERVREG_NAME_LENGTH 64
#define SERVREG_PFR_LENGTH 256
struct pdr_service;
struct pdr_handle;
enum servreg_service_state {
SERVREG_LOCATOR_ERR = 0x1,
SERVREG_SERVICE_STATE_DOWN = 0x0FFFFFFF,
SERVREG_SERVICE_STATE_UP = 0x1FFFFFFF,
SERVREG_SERVICE_STATE_EARLY_DOWN = 0x2FFFFFFF,
SERVREG_SERVICE_STATE_UNINIT = 0x7FFFFFFF,
};
struct pdr_handle *pdr_handle_alloc(void (*status)(int state,
char *service_path,
void *priv), void *priv);
struct pdr_service *pdr_add_lookup(struct pdr_handle *pdr,
const char *service_name,
const char *service_path);
int pdr_restart_pd(struct pdr_handle *pdr, struct pdr_service *pds);
void pdr_handle_release(struct pdr_handle *pdr);
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/pmic_glink.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Linaro Ltd
*/
#ifndef __SOC_QCOM_PMIC_GLINK_H__
#define __SOC_QCOM_PMIC_GLINK_H__
struct pmic_glink;
struct pmic_glink_client;
#define PMIC_GLINK_OWNER_BATTMGR 32778
#define PMIC_GLINK_OWNER_USBC 32779
#define PMIC_GLINK_OWNER_USBC_PAN 32780
#define PMIC_GLINK_REQ_RESP 1
#define PMIC_GLINK_NOTIFY 2
struct pmic_glink_hdr {
__le32 owner;
__le32 type;
__le32 opcode;
};
int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len);
struct pmic_glink_client *devm_pmic_glink_client_alloc(struct device *dev,
unsigned int id,
void (*cb)(const void *, size_t, void *),
void (*pdr)(void *, int),
void *priv);
void pmic_glink_client_register(struct pmic_glink_client *client);
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/qcom-pbs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _QCOM_PBS_H
#define _QCOM_PBS_H
#include <linux/errno.h>
#include <linux/types.h>
struct device_node;
struct pbs_dev;
#if IS_ENABLED(CONFIG_QCOM_PBS)
int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap);
struct pbs_dev *get_pbs_client_device(struct device *client_dev);
#else
static inline int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap)
{
return -ENODEV;
}
static inline struct pbs_dev *get_pbs_client_device(struct device *client_dev)
{
return ERR_PTR(-ENODEV);
}
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/qcom_aoss.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef __QCOM_AOSS_H__
#define __QCOM_AOSS_H__
#include <linux/err.h>
#include <linux/device.h>
struct qmp;
#if IS_ENABLED(CONFIG_QCOM_AOSS_QMP)
int qmp_send(struct qmp *qmp, const char *fmt, ...);
struct qmp *qmp_get(struct device *dev);
void qmp_put(struct qmp *qmp);
#else
static inline int qmp_send(struct qmp *qmp, const char *fmt, ...)
{
return -ENODEV;
}
static inline struct qmp *qmp_get(struct device *dev)
{
return ERR_PTR(-ENODEV);
}
static inline void qmp_put(struct qmp *qmp)
{
}
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/qmi.h
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2017, Linaro Ltd.
*/
#ifndef __QMI_HELPERS_H__
#define __QMI_HELPERS_H__
#include <linux/completion.h>
#include <linux/idr.h>
#include <linux/list.h>
#include <linux/qrtr.h>
#include <linux/types.h>
#include <linux/workqueue.h>
struct socket;
/**
* struct qmi_header - wireformat header of QMI messages
* @type: type of message
* @txn_id: transaction id
* @msg_id: message id
* @msg_len: length of message payload following header
*/
struct qmi_header {
u8 type;
__le16 txn_id;
__le16 msg_id;
__le16 msg_len;
} __packed;
#define QMI_REQUEST 0
#define QMI_RESPONSE 2
#define QMI_INDICATION 4
#define QMI_COMMON_TLV_TYPE 0
enum qmi_elem_type {
QMI_EOTI,
QMI_OPT_FLAG,
QMI_DATA_LEN,
QMI_UNSIGNED_1_BYTE,
QMI_UNSIGNED_2_BYTE,
QMI_UNSIGNED_4_BYTE,
QMI_UNSIGNED_8_BYTE,
QMI_SIGNED_2_BYTE_ENUM,
QMI_SIGNED_4_BYTE_ENUM,
QMI_STRUCT,
QMI_STRING,
};
enum qmi_array_type {
NO_ARRAY,
STATIC_ARRAY,
VAR_LEN_ARRAY,
};
/**
* struct qmi_elem_info - describes how to encode a single QMI element
* @data_type: Data type of this element.
* @elem_len: Array length of this element, if an array.
* @elem_size: Size of a single instance of this data type.
* @array_type: Array type of this element.
* @tlv_type: QMI message specific type to identify which element
* is present in an incoming message.
* @offset: Specifies the offset of the first instance of this
* element in the data structure.
* @ei_array: Null-terminated array of @qmi_elem_info to describe nested
* structures.
*/
struct qmi_elem_info {
enum qmi_elem_type data_type;
u32 elem_len;
u32 elem_size;
enum qmi_array_type array_type;
u8 tlv_type;
u32 offset;
const struct qmi_elem_info *ei_array;
};
#define QMI_RESULT_SUCCESS_V01 0
#define QMI_RESULT_FAILURE_V01 1
#define QMI_ERR_NONE_V01 0
#define QMI_ERR_MALFORMED_MSG_V01 1
#define QMI_ERR_NO_MEMORY_V01 2
#define QMI_ERR_INTERNAL_V01 3
#define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 5
#define QMI_ERR_INVALID_ID_V01 41
#define QMI_ERR_ENCODING_V01 58
#define QMI_ERR_DISABLED_V01 69
#define QMI_ERR_INCOMPATIBLE_STATE_V01 90
#define QMI_ERR_NOT_SUPPORTED_V01 94
/*
* Enumerate the IDs of the QMI services
*/
#define QMI_SERVICE_ID_TEST 0x0f /* 15 */
#define QMI_SERVICE_ID_SSCTL 0x2b /* 43 */
#define QMI_SERVICE_ID_IPA 0x31 /* 49 */
#define QMI_SERVICE_ID_SERVREG_LOC 0x40 /* 64 */
#define QMI_SERVICE_ID_SERVREG_NOTIF 0x42 /* 66 */
#define QMI_SERVICE_ID_WLFW 0x45 /* 69 */
#define QMI_SERVICE_ID_SLIMBUS 0x301 /* 769 */
#define QMI_SERVICE_ID_USB_AUDIO_STREAM 0x41d /* 1053 */
/**
* struct qmi_response_type_v01 - common response header (decoded)
* @result: result of the transaction
* @error: error value, when @result is QMI_RESULT_FAILURE_V01
*/
struct qmi_response_type_v01 {
u16 result;
u16 error;
};
extern const struct qmi_elem_info qmi_response_type_v01_ei[];
/**
* struct qmi_service - context to track lookup-results
* @service: service type
* @version: version of the @service
* @instance: instance id of the @service
* @node: node of the service
* @port: port of the service
* @priv: handle for client's use
* @list_node: list_head for house keeping
*/
struct qmi_service {
unsigned int service;
unsigned int version;
unsigned int instance;
unsigned int node;
unsigned int port;
void *priv;
struct list_head list_node;
};
struct qmi_handle;
/**
* struct qmi_ops - callbacks for qmi_handle
* @new_server: inform client of a new_server lookup-result, returning
* successfully from this call causes the library to call
* @del_server as the service is removed from the
* lookup-result. @priv of the qmi_service can be used by
* the client
* @del_server: inform client of a del_server lookup-result
* @net_reset: inform client that the name service was restarted and
* that and any state needs to be released
* @msg_handler: invoked for incoming messages, allows a client to
* override the usual QMI message handler
* @bye: inform a client that all clients from a node are gone
* @del_client: inform a client that a particular client is gone
*/
struct qmi_ops {
int (*new_server)(struct qmi_handle *qmi, struct qmi_service *svc);
void (*del_server)(struct qmi_handle *qmi, struct qmi_service *svc);
void (*net_reset)(struct qmi_handle *qmi);
void (*msg_handler)(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
const void *data, size_t count);
void (*bye)(struct qmi_handle *qmi, unsigned int node);
void (*del_client)(struct qmi_handle *qmi,
unsigned int node, unsigned int port);
};
/**
* struct qmi_txn - transaction context
* @qmi: QMI handle this transaction is associated with
* @id: transaction id
* @lock: for synchronization between handler and waiter of messages
* @completion: completion object as the transaction receives a response
* @result: result code for the completed transaction
* @ei: description of the QMI encoded response (optional)
* @dest: destination buffer to decode message into (optional)
*/
struct qmi_txn {
struct qmi_handle *qmi;
u16 id;
struct mutex lock;
struct completion completion;
int result;
const struct qmi_elem_info *ei;
void *dest;
};
/**
* struct qmi_msg_handler - description of QMI message handler
* @type: type of message
* @msg_id: message id
* @ei: description of the QMI encoded message
* @decoded_size: size of the decoded object
* @fn: function to invoke as the message is decoded
*/
struct qmi_msg_handler {
unsigned int type;
unsigned int msg_id;
const struct qmi_elem_info *ei;
size_t decoded_size;
void (*fn)(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
struct qmi_txn *txn, const void *decoded);
};
/**
* struct qmi_handle - QMI context
* @sock: socket handle
* @sock_lock: synchronization of @sock modifications
* @sq: sockaddr of @sock
* @work: work for handling incoming messages
* @wq: workqueue to post @work on
* @recv_buf: scratch buffer for handling incoming messages
* @recv_buf_size: size of @recv_buf
* @lookups: list of registered lookup requests
* @lookup_results: list of lookup-results advertised to the client
* @services: list of registered services (by this client)
* @ops: reference to callbacks
* @txns: outstanding transactions
* @txn_lock: lock for modifications of @txns
* @handlers: list of handlers for incoming messages
*/
struct qmi_handle {
struct socket *sock;
struct mutex sock_lock;
struct sockaddr_qrtr sq;
struct work_struct work;
struct workqueue_struct *wq;
void *recv_buf;
size_t recv_buf_size;
struct list_head lookups;
struct list_head lookup_results;
struct list_head services;
struct qmi_ops ops;
struct idr txns;
struct mutex txn_lock;
const struct qmi_msg_handler *handlers;
};
int qmi_add_lookup(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
int qmi_handle_init(struct qmi_handle *qmi, size_t max_msg_len,
const struct qmi_ops *ops,
const struct qmi_msg_handler *handlers);
void qmi_handle_release(struct qmi_handle *qmi);
ssize_t qmi_send_request(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
struct qmi_txn *txn, int msg_id, size_t len,
const struct qmi_elem_info *ei, const void *c_struct);
ssize_t qmi_send_response(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
struct qmi_txn *txn, int msg_id, size_t len,
const struct qmi_elem_info *ei, const void *c_struct);
ssize_t qmi_send_indication(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
int msg_id, size_t len, const struct qmi_elem_info *ei,
const void *c_struct);
void *qmi_encode_message(int type, unsigned int msg_id, size_t *len,
unsigned int txn_id, const struct qmi_elem_info *ei,
const void *c_struct);
int qmi_decode_message(const void *buf, size_t len,
const struct qmi_elem_info *ei, void *c_struct);
int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn,
const struct qmi_elem_info *ei, void *c_struct);
int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout);
void qmi_txn_cancel(struct qmi_txn *txn);
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/smd-rpm.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_SMD_RPM_H__
#define __QCOM_SMD_RPM_H__
#include <linux/types.h>
struct qcom_smd_rpm;
#define QCOM_SMD_RPM_ACTIVE_STATE 0
#define QCOM_SMD_RPM_SLEEP_STATE 1
#define QCOM_SMD_RPM_STATE_NUM 2
/*
* Constants used for addressing resources in the RPM.
*/
#define QCOM_SMD_RPM_BBYB 0x62796262
#define QCOM_SMD_RPM_BOBB 0x62626f62
#define QCOM_SMD_RPM_BOOST 0x61747362
#define QCOM_SMD_RPM_BUS_CLK 0x316b6c63
#define QCOM_SMD_RPM_BUS_MASTER 0x73616d62
#define QCOM_SMD_RPM_BUS_SLAVE 0x766c7362
#define QCOM_SMD_RPM_CLK_BUF_A 0x616B6C63
#define QCOM_SMD_RPM_LDOA 0x616f646c
#define QCOM_SMD_RPM_LDOB 0x626F646C
#define QCOM_SMD_RPM_LDOE 0x656f646c
#define QCOM_SMD_RPM_RWCX 0x78637772
#define QCOM_SMD_RPM_RWMX 0x786d7772
#define QCOM_SMD_RPM_RWLC 0x636c7772
#define QCOM_SMD_RPM_RWLM 0x6d6c7772
#define QCOM_SMD_RPM_MEM_CLK 0x326b6c63
#define QCOM_SMD_RPM_MISC_CLK 0x306b6c63
#define QCOM_SMD_RPM_NCPA 0x6170636E
#define QCOM_SMD_RPM_NCPB 0x6270636E
#define QCOM_SMD_RPM_OCMEM_PWR 0x706d636f
#define QCOM_SMD_RPM_QPIC_CLK 0x63697071
#define QCOM_SMD_RPM_QUP_CLK 0x707571
#define QCOM_SMD_RPM_SMPA 0x61706d73
#define QCOM_SMD_RPM_SMPB 0x62706d73
#define QCOM_SMD_RPM_SMPE 0x65706d73
#define QCOM_SMD_RPM_SPDM 0x63707362
#define QCOM_SMD_RPM_VSA 0x00617376
#define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d
#define QCOM_SMD_RPM_IPA_CLK 0x617069
#define QCOM_SMD_RPM_CE_CLK 0x6563
#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
#define QCOM_RPM_SMD_KEY_STATE 0x54415453
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
struct clk_smd_rpm_req {
__le32 key;
__le32 nbytes;
__le32 value;
};
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,
u32 resource_type, u32 resource_id,
void *buf, size_t count);
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/smem.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_SMEM_H__
#define __QCOM_SMEM_H__
#define QCOM_SMEM_HOST_ANY -1
bool qcom_smem_is_available(void);
int qcom_smem_alloc(unsigned host, unsigned item, size_t size);
void *qcom_smem_get(unsigned host, unsigned item, size_t *size);
int qcom_smem_get_free_space(unsigned host);
phys_addr_t qcom_smem_virt_to_phys(void *p);
int qcom_smem_get_soc_id(u32 *id);
int qcom_smem_get_feature_code(u32 *code);
int qcom_smem_bust_hwspin_lock_by_host(unsigned int host);
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/smem_state.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_SMEM_STATE__
#define __QCOM_SMEM_STATE__
#include <linux/err.h>
struct device_node;
struct qcom_smem_state;
struct qcom_smem_state_ops {
int (*update_bits)(void *, u32, u32);
};
#ifdef CONFIG_QCOM_SMEM_STATE
struct qcom_smem_state *qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
struct qcom_smem_state *devm_qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
void qcom_smem_state_put(struct qcom_smem_state *);
int qcom_smem_state_update_bits(struct qcom_smem_state *state, u32 mask, u32 value);
struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node, const struct qcom_smem_state_ops *ops, void *data);
void qcom_smem_state_unregister(struct qcom_smem_state *state);
#else
static inline struct qcom_smem_state *qcom_smem_state_get(struct device *dev,
const char *con_id, unsigned *bit)
{
return ERR_PTR(-EINVAL);
}
static inline struct qcom_smem_state *devm_qcom_smem_state_get(struct device *dev,
const char *con_id,
unsigned *bit)
{
return ERR_PTR(-EINVAL);
}
static inline void qcom_smem_state_put(struct qcom_smem_state *state)
{
}
static inline int qcom_smem_state_update_bits(struct qcom_smem_state *state,
u32 mask, u32 value)
{
return -EINVAL;
}
static inline struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node,
const struct qcom_smem_state_ops *ops, void *data)
{
return ERR_PTR(-EINVAL);
}
static inline void qcom_smem_state_unregister(struct qcom_smem_state *state)
{
}
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/socinfo.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __QCOM_SOCINFO_H__
#define __QCOM_SOCINFO_H__
#include <linux/types.h>
/*
* SMEM item id, used to acquire handles to respective
* SMEM region.
*/
#define SMEM_HW_SW_BUILD_ID 137
#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
/*
* SoC version type with major number in the upper 16 bits and minor
* number in the lower 16 bits.
*/
#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
/* Socinfo SMEM item structure */
struct socinfo {
__le32 fmt;
__le32 id;
__le32 ver;
char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
/* Version 2 */
__le32 raw_id;
__le32 raw_ver;
/* Version 3 */
__le32 hw_plat;
/* Version 4 */
__le32 plat_ver;
/* Version 5 */
__le32 accessory_chip;
/* Version 6 */
__le32 hw_plat_subtype;
/* Version 7 */
__le32 pmic_model;
__le32 pmic_die_rev;
/* Version 8 */
__le32 pmic_model_1;
__le32 pmic_die_rev_1;
__le32 pmic_model_2;
__le32 pmic_die_rev_2;
/* Version 9 */
__le32 foundry_id;
/* Version 10 */
__le32 serial_num;
/* Version 11 */
__le32 num_pmics;
__le32 pmic_array_offset;
/* Version 12 */
__le32 chip_family;
__le32 raw_device_family;
__le32 raw_device_num;
/* Version 13 */
__le32 nproduct_id;
char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
/* Version 14 */
__le32 num_clusters;
__le32 ncluster_array_offset;
__le32 num_subset_parts;
__le32 nsubset_parts_array_offset;
/* Version 15 */
__le32 nmodem_supported;
/* Version 16 */
__le32 feature_code;
__le32 pcode;
__le32 npartnamemap_offset;
__le32 nnum_partname_mapping;
/* Version 17 */
__le32 oem_variant;
/* Version 18 */
__le32 num_kvps;
__le32 kvps_offset;
/* Version 19 */
__le32 num_func_clusters;
__le32 boot_cluster;
__le32 boot_core;
/* Version 20 */
__le32 raw_package_type;
/* Version 21, 22, 23 */
__le32 reserve1[4];
};
/* Internal feature codes */
enum qcom_socinfo_feature_code {
/* External feature codes */
SOCINFO_FC_UNKNOWN = 0x0,
SOCINFO_FC_AA,
SOCINFO_FC_AB,
SOCINFO_FC_AC,
SOCINFO_FC_AD,
SOCINFO_FC_AE,
SOCINFO_FC_AF,
SOCINFO_FC_AG,
SOCINFO_FC_AH,
};
/* Internal feature codes */
/* Valid values: 0 <= n <= 0xf */
#define SOCINFO_FC_Yn(n) (0xf1 + (n))
#define SOCINFO_FC_INT_MAX SOCINFO_FC_Yn(0xf)
/* Product codes */
#define SOCINFO_PC_UNKNOWN 0
#define SOCINFO_PCn(n) ((n) + 1)
#define SOCINFO_PC_RESERVE (BIT(31) - 1)
#endif
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/ubwc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __QCOM_UBWC_H__
#define __QCOM_UBWC_H__
#include <linux/bits.h>
#include <linux/printk.h>
#include <linux/types.h>
struct qcom_ubwc_cfg_data {
u32 ubwc_enc_version;
/* Can be read from MDSS_BASE + 0x58 */
u32 ubwc_dec_version;
/**
* @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
*
* UBWC 1.0 always enables all three levels.
* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
*/
u32 ubwc_swizzle;
#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
/**
* @highest_bank_bit: Highest Bank Bit
*
* The Highest Bank Bit value represents the bit of the highest
* DDR bank. This should ideally use DRAM type detection.
*/
int highest_bank_bit;
bool ubwc_bank_spread;
/**
* @macrotile_mode: Macrotile Mode
*
* Whether to use 4-channel macrotiling mode or the newer
* 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
* 4-channel and 1 is 8-channel.
*/
bool macrotile_mode;
};
#define UBWC_1_0 0x10000000
#define UBWC_2_0 0x20000000
#define UBWC_3_0 0x30000000
#define UBWC_4_0 0x40000000
#define UBWC_4_3 0x40030000
#define UBWC_5_0 0x50000000
#define UBWC_6_0 0x60000000
#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG)
const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
#else
static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
{
return ERR_PTR(-EOPNOTSUPP);
}
#endif
static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
{
bool ret = cfg->ubwc_enc_version == UBWC_1_0;
if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
return ret;
}
/*
* This is the best guess, based on the MDSS driver, which worked so far.
*/
static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg)
{
return cfg->ubwc_enc_version == UBWC_1_0 &&
(cfg->ubwc_dec_version == UBWC_2_0 ||
cfg->ubwc_dec_version == UBWC_3_0);
}
static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg)
{
return cfg->macrotile_mode;
}
static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg)
{
return cfg->ubwc_bank_spread;
}
static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
{
return cfg->ubwc_swizzle;
}
#endif /* __QCOM_UBWC_H__ */
local/recipes/gpu/amdgpu-source/include/linux/soc/qcom/wcnss_ctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __WCNSS_CTRL_H__
#define __WCNSS_CTRL_H__
#include <linux/rpmsg.h>
#if IS_ENABLED(CONFIG_QCOM_WCNSS_CTRL)
struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss, const char *name,
rpmsg_rx_cb_t cb, void *priv);
#else
static struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss,
const char *name,
rpmsg_rx_cb_t cb,
void *priv)
{
WARN_ON(1);
return ERR_PTR(-ENXIO);
}
#endif
#endif