restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
@@ -0,0 +1,11 @@
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/*
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* Copyright (c) 2017 Andreas Färber
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef SOC_ACTIONS_OWL_SPS_H
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#define SOC_ACTIONS_OWL_SPS_H
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int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
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#endif
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@@ -0,0 +1,317 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 AIROHA Inc
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* Author: Lorenzo Bianconi <lorenzo@kernel.org>
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*/
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#ifndef AIROHA_OFFLOAD_H
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#define AIROHA_OFFLOAD_H
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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enum {
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PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
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};
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struct airoha_ppe_dev {
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struct {
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int (*setup_tc_block_cb)(struct airoha_ppe_dev *dev,
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void *type_data);
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void (*check_skb)(struct airoha_ppe_dev *dev,
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struct sk_buff *skb, u16 hash,
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bool rx_wlan);
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} ops;
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void *priv;
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};
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#if (IS_BUILTIN(CONFIG_NET_AIROHA) || IS_MODULE(CONFIG_NET_AIROHA))
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struct airoha_ppe_dev *airoha_ppe_get_dev(struct device *dev);
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void airoha_ppe_put_dev(struct airoha_ppe_dev *dev);
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static inline int airoha_ppe_dev_setup_tc_block_cb(struct airoha_ppe_dev *dev,
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void *type_data)
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{
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return dev->ops.setup_tc_block_cb(dev, type_data);
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}
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static inline void airoha_ppe_dev_check_skb(struct airoha_ppe_dev *dev,
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struct sk_buff *skb,
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u16 hash, bool rx_wlan)
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{
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dev->ops.check_skb(dev, skb, hash, rx_wlan);
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}
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#else
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static inline struct airoha_ppe_dev *airoha_ppe_get_dev(struct device *dev)
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{
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return NULL;
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}
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static inline void airoha_ppe_put_dev(struct airoha_ppe_dev *dev)
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{
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}
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static inline int airoha_ppe_dev_setup_tc_block_cb(struct airoha_ppe_dev *dev,
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void *type_data)
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{
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return -EOPNOTSUPP;
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}
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static inline void airoha_ppe_dev_check_skb(struct airoha_ppe_dev *dev,
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struct sk_buff *skb, u16 hash,
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bool rx_wlan)
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{
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}
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#endif
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#define NPU_NUM_CORES 8
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#define NPU_NUM_IRQ 6
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#define NPU_RX0_DESC_NUM 512
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#define NPU_RX1_DESC_NUM 512
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/* CTRL */
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#define NPU_RX_DMA_DESC_LAST_MASK BIT(29)
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#define NPU_RX_DMA_DESC_LEN_MASK GENMASK(28, 15)
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#define NPU_RX_DMA_DESC_CUR_LEN_MASK GENMASK(14, 1)
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#define NPU_RX_DMA_DESC_DONE_MASK BIT(0)
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/* INFO */
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#define NPU_RX_DMA_PKT_COUNT_MASK GENMASK(31, 29)
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#define NPU_RX_DMA_PKT_ID_MASK GENMASK(28, 26)
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#define NPU_RX_DMA_SRC_PORT_MASK GENMASK(25, 21)
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#define NPU_RX_DMA_CRSN_MASK GENMASK(20, 16)
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#define NPU_RX_DMA_FOE_ID_MASK GENMASK(15, 0)
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/* DATA */
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#define NPU_RX_DMA_SID_MASK GENMASK(31, 16)
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#define NPU_RX_DMA_FRAG_TYPE_MASK GENMASK(15, 14)
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#define NPU_RX_DMA_PRIORITY_MASK GENMASK(13, 10)
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#define NPU_RX_DMA_RADIO_ID_MASK GENMASK(9, 6)
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#define NPU_RX_DMA_VAP_ID_MASK GENMASK(5, 2)
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#define NPU_RX_DMA_FRAME_TYPE_MASK GENMASK(1, 0)
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struct airoha_npu_rx_dma_desc {
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u32 ctrl;
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u32 info;
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u32 data;
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u32 addr;
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u64 rsv;
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} __packed;
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/* CTRL */
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#define NPU_TX_DMA_DESC_SCHED_MASK BIT(31)
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#define NPU_TX_DMA_DESC_LEN_MASK GENMASK(30, 18)
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#define NPU_TX_DMA_DESC_VEND_LEN_MASK GENMASK(17, 1)
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#define NPU_TX_DMA_DESC_DONE_MASK BIT(0)
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#define NPU_TXWI_LEN 192
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struct airoha_npu_tx_dma_desc {
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u32 ctrl;
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u32 addr;
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u64 rsv;
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u8 txwi[NPU_TXWI_LEN];
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} __packed;
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enum airoha_npu_wlan_set_cmd {
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WLAN_FUNC_SET_WAIT_PCIE_ADDR,
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WLAN_FUNC_SET_WAIT_DESC,
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WLAN_FUNC_SET_WAIT_NPU_INIT_DONE,
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WLAN_FUNC_SET_WAIT_TRAN_TO_CPU,
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WLAN_FUNC_SET_WAIT_BA_WIN_SIZE,
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WLAN_FUNC_SET_WAIT_DRIVER_MODEL,
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WLAN_FUNC_SET_WAIT_DEL_STA,
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WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR,
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WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR,
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WLAN_FUNC_SET_WAIT_IS_TEST_NOBA,
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WLAN_FUNC_SET_WAIT_FLUSHONE_TIMEOUT,
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WLAN_FUNC_SET_WAIT_FLUSHALL_TIMEOUT,
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WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU,
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WLAN_FUNC_SET_WAIT_PCIE_STATE,
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WLAN_FUNC_SET_WAIT_PCIE_PORT_TYPE,
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WLAN_FUNC_SET_WAIT_ERROR_RETRY_TIMES,
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WLAN_FUNC_SET_WAIT_BAR_INFO,
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WLAN_FUNC_SET_WAIT_FAST_FLAG,
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WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU,
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WLAN_FUNC_SET_WAIT_TX_RING_PCIE_ADDR,
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WLAN_FUNC_SET_WAIT_TX_DESC_HW_BASE,
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WLAN_FUNC_SET_WAIT_TX_BUF_SPACE_HW_BASE,
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||||
WLAN_FUNC_SET_WAIT_RX_RING_FOR_TXDONE_HW_BASE,
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WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR,
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||||
WLAN_FUNC_SET_WAIT_INODE_TXRX_REG_ADDR,
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||||
WLAN_FUNC_SET_WAIT_INODE_DEBUG_FLAG,
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WLAN_FUNC_SET_WAIT_INODE_HW_CFG_INFO,
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WLAN_FUNC_SET_WAIT_INODE_STOP_ACTION,
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||||
WLAN_FUNC_SET_WAIT_INODE_PCIE_SWAP,
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WLAN_FUNC_SET_WAIT_RATELIMIT_CTRL,
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||||
WLAN_FUNC_SET_WAIT_HWNAT_INIT,
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||||
WLAN_FUNC_SET_WAIT_ARHT_CHIP_INFO,
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||||
WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR,
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||||
WLAN_FUNC_SET_WAIT_TOKEN_ID_SIZE,
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||||
};
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||||
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||||
enum airoha_npu_wlan_get_cmd {
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||||
WLAN_FUNC_GET_WAIT_NPU_INFO,
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WLAN_FUNC_GET_WAIT_LAST_RATE,
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WLAN_FUNC_GET_WAIT_COUNTER,
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||||
WLAN_FUNC_GET_WAIT_DBG_COUNTER,
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||||
WLAN_FUNC_GET_WAIT_RXDESC_BASE,
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||||
WLAN_FUNC_GET_WAIT_WCID_DBG_COUNTER,
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||||
WLAN_FUNC_GET_WAIT_DMA_ADDR,
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||||
WLAN_FUNC_GET_WAIT_RING_SIZE,
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||||
WLAN_FUNC_GET_WAIT_NPU_SUPPORT_MAP,
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||||
WLAN_FUNC_GET_WAIT_MDC_LOCK_ADDRESS,
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||||
WLAN_FUNC_GET_WAIT_NPU_VERSION,
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||||
};
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||||
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struct airoha_npu {
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||||
#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU))
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struct device *dev;
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struct regmap *regmap;
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struct airoha_npu_core {
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||||
struct airoha_npu *npu;
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||||
/* protect concurrent npu memory accesses */
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spinlock_t lock;
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struct work_struct wdt_work;
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} cores[NPU_NUM_CORES];
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int irqs[NPU_NUM_IRQ];
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struct airoha_foe_stats __iomem *stats;
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struct {
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int (*ppe_init)(struct airoha_npu *npu);
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int (*ppe_deinit)(struct airoha_npu *npu);
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int (*ppe_init_stats)(struct airoha_npu *npu,
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dma_addr_t addr, u32 num_stats_entries);
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||||
int (*ppe_flush_sram_entries)(struct airoha_npu *npu,
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dma_addr_t foe_addr,
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int sram_num_entries);
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int (*ppe_foe_commit_entry)(struct airoha_npu *npu,
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dma_addr_t foe_addr,
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u32 entry_size, u32 hash,
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bool ppe2);
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int (*wlan_init_reserved_memory)(struct airoha_npu *npu);
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int (*wlan_send_msg)(struct airoha_npu *npu, int ifindex,
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enum airoha_npu_wlan_set_cmd func_id,
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void *data, int data_len, gfp_t gfp);
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int (*wlan_get_msg)(struct airoha_npu *npu, int ifindex,
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enum airoha_npu_wlan_get_cmd func_id,
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void *data, int data_len, gfp_t gfp);
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u32 (*wlan_get_queue_addr)(struct airoha_npu *npu, int qid,
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bool xmit);
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void (*wlan_set_irq_status)(struct airoha_npu *npu, u32 val);
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u32 (*wlan_get_irq_status)(struct airoha_npu *npu, int q);
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void (*wlan_enable_irq)(struct airoha_npu *npu, int q);
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void (*wlan_disable_irq)(struct airoha_npu *npu, int q);
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} ops;
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#endif
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};
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#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU))
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struct airoha_npu *airoha_npu_get(struct device *dev);
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void airoha_npu_put(struct airoha_npu *npu);
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static inline int airoha_npu_wlan_init_reserved_memory(struct airoha_npu *npu)
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{
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return npu->ops.wlan_init_reserved_memory(npu);
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||||
}
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static inline int airoha_npu_wlan_send_msg(struct airoha_npu *npu,
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int ifindex,
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enum airoha_npu_wlan_set_cmd cmd,
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||||
void *data, int data_len, gfp_t gfp)
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||||
{
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||||
return npu->ops.wlan_send_msg(npu, ifindex, cmd, data, data_len, gfp);
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||||
}
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||||
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||||
static inline int airoha_npu_wlan_get_msg(struct airoha_npu *npu, int ifindex,
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||||
enum airoha_npu_wlan_get_cmd cmd,
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||||
void *data, int data_len, gfp_t gfp)
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||||
{
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||||
return npu->ops.wlan_get_msg(npu, ifindex, cmd, data, data_len, gfp);
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||||
}
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||||
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||||
static inline u32 airoha_npu_wlan_get_queue_addr(struct airoha_npu *npu,
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||||
int qid, bool xmit)
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||||
{
|
||||
return npu->ops.wlan_get_queue_addr(npu, qid, xmit);
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||||
}
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||||
|
||||
static inline void airoha_npu_wlan_set_irq_status(struct airoha_npu *npu,
|
||||
u32 val)
|
||||
{
|
||||
npu->ops.wlan_set_irq_status(npu, val);
|
||||
}
|
||||
|
||||
static inline u32 airoha_npu_wlan_get_irq_status(struct airoha_npu *npu, int q)
|
||||
{
|
||||
return npu->ops.wlan_get_irq_status(npu, q);
|
||||
}
|
||||
|
||||
static inline void airoha_npu_wlan_enable_irq(struct airoha_npu *npu, int q)
|
||||
{
|
||||
npu->ops.wlan_enable_irq(npu, q);
|
||||
}
|
||||
|
||||
static inline void airoha_npu_wlan_disable_irq(struct airoha_npu *npu, int q)
|
||||
{
|
||||
npu->ops.wlan_disable_irq(npu, q);
|
||||
}
|
||||
#else
|
||||
static inline struct airoha_npu *airoha_npu_get(struct device *dev)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void airoha_npu_put(struct airoha_npu *npu)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int airoha_npu_wlan_init_reserved_memory(struct airoha_npu *npu)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int airoha_npu_wlan_send_msg(struct airoha_npu *npu,
|
||||
int ifindex,
|
||||
enum airoha_npu_wlan_set_cmd cmd,
|
||||
void *data, int data_len, gfp_t gfp)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int airoha_npu_wlan_get_msg(struct airoha_npu *npu, int ifindex,
|
||||
enum airoha_npu_wlan_get_cmd cmd,
|
||||
void *data, int data_len, gfp_t gfp)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline u32 airoha_npu_wlan_get_queue_addr(struct airoha_npu *npu,
|
||||
int qid, bool xmit)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void airoha_npu_wlan_set_irq_status(struct airoha_npu *npu,
|
||||
u32 val)
|
||||
{
|
||||
}
|
||||
|
||||
static inline u32 airoha_npu_wlan_get_irq_status(struct airoha_npu *npu,
|
||||
int q)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void airoha_npu_wlan_enable_irq(struct airoha_npu *npu, int q)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void airoha_npu_wlan_disable_irq(struct airoha_npu *npu, int q)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* AIROHA_OFFLOAD_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_ISP4_MISC_H
|
||||
#define __SOC_ISP4_MISC_H
|
||||
|
||||
#define AMDISP_I2C_ADAP_NAME "AMDISP DesignWare I2C adapter"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,66 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 BayLibre, SAS
|
||||
*/
|
||||
#ifndef __SOC_MESON_CANVAS_H
|
||||
#define __SOC_MESON_CANVAS_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define MESON_CANVAS_WRAP_NONE 0x00
|
||||
#define MESON_CANVAS_WRAP_X 0x01
|
||||
#define MESON_CANVAS_WRAP_Y 0x02
|
||||
|
||||
#define MESON_CANVAS_BLKMODE_LINEAR 0x00
|
||||
#define MESON_CANVAS_BLKMODE_32x32 0x01
|
||||
#define MESON_CANVAS_BLKMODE_64x64 0x02
|
||||
|
||||
#define MESON_CANVAS_ENDIAN_SWAP16 0x1
|
||||
#define MESON_CANVAS_ENDIAN_SWAP32 0x3
|
||||
#define MESON_CANVAS_ENDIAN_SWAP64 0x7
|
||||
#define MESON_CANVAS_ENDIAN_SWAP128 0xf
|
||||
|
||||
struct device;
|
||||
struct meson_canvas;
|
||||
|
||||
/**
|
||||
* meson_canvas_get() - get a canvas provider instance
|
||||
*
|
||||
* @dev: consumer device pointer
|
||||
*/
|
||||
struct meson_canvas *meson_canvas_get(struct device *dev);
|
||||
|
||||
/**
|
||||
* meson_canvas_alloc() - take ownership of a canvas
|
||||
*
|
||||
* @canvas: canvas provider instance retrieved from meson_canvas_get()
|
||||
* @canvas_index: will be filled with the canvas ID
|
||||
*/
|
||||
int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index);
|
||||
|
||||
/**
|
||||
* meson_canvas_free() - remove ownership from a canvas
|
||||
*
|
||||
* @canvas: canvas provider instance retrieved from meson_canvas_get()
|
||||
* @canvas_index: canvas ID that was obtained via meson_canvas_alloc()
|
||||
*/
|
||||
int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index);
|
||||
|
||||
/**
|
||||
* meson_canvas_config() - configure a canvas
|
||||
*
|
||||
* @canvas: canvas provider instance retrieved from meson_canvas_get()
|
||||
* @canvas_index: canvas ID that was obtained via meson_canvas_alloc()
|
||||
* @addr: physical address to the pixel buffer
|
||||
* @stride: width of the buffer
|
||||
* @height: height of the buffer
|
||||
* @wrap: undocumented
|
||||
* @blkmode: block mode (linear, 32x32, 64x64)
|
||||
* @endian: byte swapping (swap16, swap32, swap64, swap128)
|
||||
*/
|
||||
int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index,
|
||||
u32 addr, u32 stride, u32 height,
|
||||
unsigned int wrap, unsigned int blkmode,
|
||||
unsigned int endian);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2023 Andes Technology Corporation
|
||||
*/
|
||||
#ifndef __ANDES_IRQ_H
|
||||
#define __ANDES_IRQ_H
|
||||
|
||||
/* Andes PMU irq number */
|
||||
#define ANDES_RV_IRQ_PMOVI 18
|
||||
#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
|
||||
#define ANDES_SLI_CAUSE_BASE 256
|
||||
|
||||
/* Andes PMU related registers */
|
||||
#define ANDES_CSR_SLIE 0x9c4
|
||||
#define ANDES_CSR_SLIP 0x9c5
|
||||
#define ANDES_CSR_SCOUNTEROF 0x9d4
|
||||
|
||||
#endif /* __ANDES_IRQ_H */
|
||||
@@ -0,0 +1,182 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/*
|
||||
* Apple RTKit IPC Library
|
||||
* Copyright (C) The Asahi Linux Contributors
|
||||
*
|
||||
* Apple's SoCs come with various co-processors running their RTKit operating
|
||||
* system. This protocol library is used by client drivers to use the
|
||||
* features provided by them.
|
||||
*/
|
||||
#ifndef _LINUX_APPLE_RTKIT_H_
|
||||
#define _LINUX_APPLE_RTKIT_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mailbox_client.h>
|
||||
|
||||
/*
|
||||
* Struct to represent implementation-specific RTKit operations.
|
||||
*
|
||||
* @buffer: Shared memory buffer allocated inside normal RAM.
|
||||
* @iomem: Shared memory buffer controlled by the co-processors.
|
||||
* @size: Size of the shared memory buffer.
|
||||
* @iova: Device VA of shared memory buffer.
|
||||
* @is_mapped: Shared memory buffer is managed by the co-processor.
|
||||
* @private: Private data pointer for the parent driver.
|
||||
*/
|
||||
|
||||
struct apple_rtkit_shmem {
|
||||
void *buffer;
|
||||
void __iomem *iomem;
|
||||
size_t size;
|
||||
dma_addr_t iova;
|
||||
bool is_mapped;
|
||||
void *private;
|
||||
};
|
||||
|
||||
/*
|
||||
* Struct to represent implementation-specific RTKit operations.
|
||||
*
|
||||
* @crashed: Called when the co-processor has crashed. Runs in process
|
||||
* context.
|
||||
* @recv_message: Function called when a message from RTKit is received
|
||||
* on a non-system endpoint. Called from a worker thread.
|
||||
* @recv_message_early:
|
||||
* Like recv_message, but called from atomic context. It
|
||||
* should return true if it handled the message. If it
|
||||
* returns false, the message will be passed on to the
|
||||
* worker thread.
|
||||
* @shmem_setup: Setup shared memory buffer. If bfr.is_iomem is true the
|
||||
* buffer is managed by the co-processor and needs to be mapped.
|
||||
* Otherwise the buffer is managed by Linux and needs to be
|
||||
* allocated. If not specified dma_alloc_coherent is used.
|
||||
* Called in process context.
|
||||
* @shmem_destroy: Undo the shared memory buffer setup in shmem_setup. If not
|
||||
* specified dma_free_coherent is used. Called in process
|
||||
* context.
|
||||
*/
|
||||
struct apple_rtkit_ops {
|
||||
void (*crashed)(void *cookie, const void *crashlog, size_t crashlog_size);
|
||||
void (*recv_message)(void *cookie, u8 endpoint, u64 message);
|
||||
bool (*recv_message_early)(void *cookie, u8 endpoint, u64 message);
|
||||
int (*shmem_setup)(void *cookie, struct apple_rtkit_shmem *bfr);
|
||||
void (*shmem_destroy)(void *cookie, struct apple_rtkit_shmem *bfr);
|
||||
};
|
||||
|
||||
struct apple_rtkit;
|
||||
|
||||
/*
|
||||
* Initializes the internal state required to handle RTKit. This
|
||||
* should usually be called within _probe.
|
||||
*
|
||||
* @dev: Pointer to the device node this coprocessor is associated with
|
||||
* @cookie: opaque cookie passed to all functions defined in rtkit_ops
|
||||
* @mbox_name: mailbox name used to communicate with the co-processor
|
||||
* @mbox_idx: mailbox index to be used if mbox_name is NULL
|
||||
* @ops: pointer to rtkit_ops to be used for this co-processor
|
||||
*/
|
||||
struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie,
|
||||
const char *mbox_name, int mbox_idx,
|
||||
const struct apple_rtkit_ops *ops);
|
||||
|
||||
/*
|
||||
* Non-devm version of devm_apple_rtkit_init. Must be freed with
|
||||
* apple_rtkit_free.
|
||||
*
|
||||
* @dev: Pointer to the device node this coprocessor is associated with
|
||||
* @cookie: opaque cookie passed to all functions defined in rtkit_ops
|
||||
* @mbox_name: mailbox name used to communicate with the co-processor
|
||||
* @mbox_idx: mailbox index to be used if mbox_name is NULL
|
||||
* @ops: pointer to rtkit_ops to be used for this co-processor
|
||||
*/
|
||||
struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie,
|
||||
const char *mbox_name, int mbox_idx,
|
||||
const struct apple_rtkit_ops *ops);
|
||||
|
||||
/*
|
||||
* Free an instance of apple_rtkit.
|
||||
*/
|
||||
void apple_rtkit_free(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Reinitialize internal structures. Must only be called with the co-processor
|
||||
* is held in reset.
|
||||
*/
|
||||
int apple_rtkit_reinit(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Handle RTKit's boot process. Should be called after the CPU of the
|
||||
* co-processor has been started.
|
||||
*/
|
||||
int apple_rtkit_boot(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Quiesce the co-processor.
|
||||
*/
|
||||
int apple_rtkit_quiesce(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Wake the co-processor up from hibernation mode.
|
||||
*/
|
||||
int apple_rtkit_wake(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Shutdown the co-processor
|
||||
*/
|
||||
int apple_rtkit_shutdown(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Put the co-processor into the lowest power state. Note that it usually
|
||||
* is not possible to recover from this state without a full SoC reset.
|
||||
*/
|
||||
|
||||
int apple_rtkit_poweroff(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Put the co-processor into idle mode
|
||||
*/
|
||||
int apple_rtkit_idle(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Checks if RTKit is running and ready to handle messages.
|
||||
*/
|
||||
bool apple_rtkit_is_running(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Checks if RTKit has crashed.
|
||||
*/
|
||||
bool apple_rtkit_is_crashed(struct apple_rtkit *rtk);
|
||||
|
||||
/*
|
||||
* Starts an endpoint. Must be called after boot but before any messages can be
|
||||
* sent or received from that endpoint.
|
||||
*/
|
||||
int apple_rtkit_start_ep(struct apple_rtkit *rtk, u8 endpoint);
|
||||
|
||||
/*
|
||||
* Send a message to the given endpoint.
|
||||
*
|
||||
* @rtk: RTKit reference
|
||||
* @ep: target endpoint
|
||||
* @message: message to be sent
|
||||
* @completeion: will be completed once the message has been submitted
|
||||
* to the hardware FIFO. Can be NULL.
|
||||
* @atomic: if set to true this function can be called from atomic
|
||||
* context.
|
||||
*/
|
||||
int apple_rtkit_send_message(struct apple_rtkit *rtk, u8 ep, u64 message,
|
||||
struct completion *completion, bool atomic);
|
||||
|
||||
/*
|
||||
* Process incoming messages in atomic context.
|
||||
* This only guarantees that messages arrive as far as the recv_message_early
|
||||
* callback; drivers expecting to handle incoming messages synchronously
|
||||
* by calling this function must do it that way.
|
||||
* Will return 1 if some data was processed, 0 if none was, or a
|
||||
* negative error code on failure.
|
||||
*
|
||||
* @rtk: RTKit reference
|
||||
*/
|
||||
int apple_rtkit_poll(struct apple_rtkit *rtk);
|
||||
|
||||
#endif /* _LINUX_APPLE_RTKIT_H_ */
|
||||
@@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/*
|
||||
* Apple SART device driver
|
||||
* Copyright (C) The Asahi Linux Contributors
|
||||
*
|
||||
* Apple SART is a simple address filter for DMA transactions.
|
||||
* Regions of physical memory must be added to the SART's allow
|
||||
* list before any DMA can target these. Unlike a proper
|
||||
* IOMMU no remapping can be done.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_SOC_APPLE_SART_H_
|
||||
#define _LINUX_SOC_APPLE_SART_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct apple_sart;
|
||||
|
||||
/*
|
||||
* Get a reference to the SART attached to dev.
|
||||
*
|
||||
* Looks for the phandle reference in apple,sart and returns a pointer
|
||||
* to the corresponding apple_sart struct to be used with
|
||||
* apple_sart_add_allowed_region and apple_sart_remove_allowed_region.
|
||||
*/
|
||||
struct apple_sart *devm_apple_sart_get(struct device *dev);
|
||||
|
||||
/*
|
||||
* Adds the region [paddr, paddr+size] to the DMA allow list.
|
||||
*
|
||||
* @sart: SART reference
|
||||
* @paddr: Start address of the region to be used for DMA
|
||||
* @size: Size of the region to be used for DMA.
|
||||
*/
|
||||
int apple_sart_add_allowed_region(struct apple_sart *sart, phys_addr_t paddr,
|
||||
size_t size);
|
||||
|
||||
/*
|
||||
* Removes the region [paddr, paddr+size] from the DMA allow list.
|
||||
*
|
||||
* Note that exact same paddr and size used for apple_sart_add_allowed_region
|
||||
* have to be passed.
|
||||
*
|
||||
* @sart: SART reference
|
||||
* @paddr: Start address of the region no longer used for DMA
|
||||
* @size: Size of the region no longer used for DMA.
|
||||
*/
|
||||
int apple_sart_remove_allowed_region(struct apple_sart *sart, phys_addr_t paddr,
|
||||
size_t size);
|
||||
|
||||
#endif /* _LINUX_SOC_APPLE_SART_H_ */
|
||||
@@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/*
|
||||
* Apple Silicon hardware tunable support
|
||||
*
|
||||
* Each tunable is a list with each entry containing a offset into the MMIO
|
||||
* region, a mask of bits to be cleared and a set of bits to be set. These
|
||||
* tunables are passed along by the previous boot stages and vary from device
|
||||
* to device such that they cannot be hardcoded in the individual drivers.
|
||||
*
|
||||
* Copyright (C) The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_SOC_APPLE_TUNABLE_H_
|
||||
#define _LINUX_SOC_APPLE_TUNABLE_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* Struct to store an Apple Silicon hardware tunable.
|
||||
*
|
||||
* Each tunable is a list with each entry containing a offset into the MMIO
|
||||
* region, a mask of bits to be cleared and a set of bits to be set. These
|
||||
* tunables are passed along by the previous boot stages and vary from device
|
||||
* to device such that they cannot be hardcoded in the individual drivers.
|
||||
*
|
||||
* @param sz Number of [offset, mask, value] tuples stored in values.
|
||||
* @param values [offset, mask, value] array.
|
||||
*/
|
||||
struct apple_tunable {
|
||||
size_t sz;
|
||||
struct {
|
||||
u32 offset;
|
||||
u32 mask;
|
||||
u32 value;
|
||||
} values[] __counted_by(sz);
|
||||
};
|
||||
|
||||
/**
|
||||
* Parse an array of hardware tunables from the device tree.
|
||||
*
|
||||
* @dev: Device node used for devm_kzalloc internally.
|
||||
* @np: Device node which contains the tunable array.
|
||||
* @name: Name of the device tree property which contains the tunables.
|
||||
* @res: Resource to which the tunables will be applied, used for bound checking
|
||||
*
|
||||
* @return: devres allocated struct on success or PTR_ERR on failure.
|
||||
*/
|
||||
struct apple_tunable *devm_apple_tunable_parse(struct device *dev,
|
||||
struct device_node *np,
|
||||
const char *name,
|
||||
struct resource *res);
|
||||
|
||||
/**
|
||||
* Apply a previously loaded hardware tunable.
|
||||
*
|
||||
* @param regs: MMIO to which the tunable will be applied.
|
||||
* @param tunable: Pointer to the tunable.
|
||||
*/
|
||||
void apple_tunable_apply(void __iomem *regs, struct apple_tunable *tunable);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __BRCMSTB_SOC_H
|
||||
#define __BRCMSTB_SOC_H
|
||||
|
||||
#include <linux/kconfig.h>
|
||||
|
||||
static inline u32 BRCM_ID(u32 reg)
|
||||
{
|
||||
return reg >> 28 ? reg >> 16 : reg >> 8;
|
||||
}
|
||||
|
||||
static inline u32 BRCM_REV(u32 reg)
|
||||
{
|
||||
return reg & 0xff;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOC_BRCMSTB)
|
||||
|
||||
/*
|
||||
* Helper functions for getting family or product id from the
|
||||
* SoC driver.
|
||||
*/
|
||||
u32 brcmstb_get_family_id(void);
|
||||
u32 brcmstb_get_product_id(void);
|
||||
|
||||
#else
|
||||
static inline u32 brcmstb_get_family_id(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline u32 brcmstb_get_product_id(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __BRCMSTB_SOC_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _SOC_EP93XX_H
|
||||
#define _SOC_EP93XX_H
|
||||
|
||||
struct regmap;
|
||||
struct spinlock_t;
|
||||
|
||||
enum ep93xx_soc_model {
|
||||
EP93XX_9301_SOC,
|
||||
EP93XX_9307_SOC,
|
||||
EP93XX_9312_SOC,
|
||||
};
|
||||
|
||||
#include <linux/auxiliary_bus.h>
|
||||
#include <linux/compiler_types.h>
|
||||
#include <linux/container_of.h>
|
||||
|
||||
#define EP93XX_CHIP_REV_D0 3
|
||||
#define EP93XX_CHIP_REV_D1 4
|
||||
#define EP93XX_CHIP_REV_E0 5
|
||||
#define EP93XX_CHIP_REV_E1 6
|
||||
#define EP93XX_CHIP_REV_E2 7
|
||||
|
||||
struct ep93xx_regmap_adev {
|
||||
struct auxiliary_device adev;
|
||||
struct regmap *map;
|
||||
void __iomem *base;
|
||||
spinlock_t *lock;
|
||||
void (*write)(struct regmap *map, spinlock_t *lock, unsigned int reg,
|
||||
unsigned int val);
|
||||
void (*update_bits)(struct regmap *map, spinlock_t *lock,
|
||||
unsigned int reg, unsigned int mask, unsigned int val);
|
||||
};
|
||||
|
||||
#define to_ep93xx_regmap_adev(_adev) \
|
||||
container_of((_adev), struct ep93xx_regmap_adev, adev)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef LINUX_SOC_DOVE_PMU_H
|
||||
#define LINUX_SOC_DOVE_PMU_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct dove_pmu_domain_initdata {
|
||||
u32 pwr_mask;
|
||||
u32 rst_mask;
|
||||
u32 iso_mask;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
struct dove_pmu_initdata {
|
||||
void __iomem *pmc_base;
|
||||
void __iomem *pmu_base;
|
||||
int irq;
|
||||
int irq_domain_start;
|
||||
const struct dove_pmu_domain_initdata *domains;
|
||||
};
|
||||
|
||||
int dove_init_pmu_legacy(const struct dove_pmu_initdata *);
|
||||
|
||||
int dove_init_pmu(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,120 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* IXP4XX cpu type detection
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_IXP4XX_CPU_H__
|
||||
#define __SOC_IXP4XX_CPU_H__
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/regmap.h>
|
||||
#ifdef CONFIG_ARM
|
||||
#include <asm/cputype.h>
|
||||
#endif
|
||||
|
||||
/* Processor id value in CP15 Register 0 */
|
||||
#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
|
||||
#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
|
||||
|
||||
#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
|
||||
#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
|
||||
|
||||
#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
|
||||
#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
|
||||
|
||||
/* Feature register in the expansion bus controller */
|
||||
#define IXP4XX_EXP_CNFG2 0x2c
|
||||
|
||||
/* "fuse" bits of IXP_EXP_CFG2 */
|
||||
/* All IXP4xx CPUs */
|
||||
#define IXP4XX_FEATURE_RCOMP (1 << 0)
|
||||
#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
|
||||
#define IXP4XX_FEATURE_HASH (1 << 2)
|
||||
#define IXP4XX_FEATURE_AES (1 << 3)
|
||||
#define IXP4XX_FEATURE_DES (1 << 4)
|
||||
#define IXP4XX_FEATURE_HDLC (1 << 5)
|
||||
#define IXP4XX_FEATURE_AAL (1 << 6)
|
||||
#define IXP4XX_FEATURE_HSS (1 << 7)
|
||||
#define IXP4XX_FEATURE_UTOPIA (1 << 8)
|
||||
#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
|
||||
#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
|
||||
#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
|
||||
#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
|
||||
#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
|
||||
#define IXP4XX_FEATURE_PCI (1 << 14)
|
||||
#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
|
||||
#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
|
||||
#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
|
||||
IXP4XX_FEATURE_USB_DEVICE | \
|
||||
IXP4XX_FEATURE_HASH | \
|
||||
IXP4XX_FEATURE_AES | \
|
||||
IXP4XX_FEATURE_DES | \
|
||||
IXP4XX_FEATURE_HDLC | \
|
||||
IXP4XX_FEATURE_AAL | \
|
||||
IXP4XX_FEATURE_HSS | \
|
||||
IXP4XX_FEATURE_UTOPIA | \
|
||||
IXP4XX_FEATURE_NPEB_ETH0 | \
|
||||
IXP4XX_FEATURE_NPEC_ETH | \
|
||||
IXP4XX_FEATURE_RESET_NPEA | \
|
||||
IXP4XX_FEATURE_RESET_NPEB | \
|
||||
IXP4XX_FEATURE_RESET_NPEC | \
|
||||
IXP4XX_FEATURE_PCI | \
|
||||
IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
|
||||
IXP4XX_FEATURE_XSCALE_MAX_FREQ)
|
||||
|
||||
|
||||
/* IXP43x/46x CPUs */
|
||||
#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
|
||||
#define IXP4XX_FEATURE_USB_HOST (1 << 18)
|
||||
#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
|
||||
#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
|
||||
IXP4XX_FEATURE_ECC_TIMESYNC | \
|
||||
IXP4XX_FEATURE_USB_HOST | \
|
||||
IXP4XX_FEATURE_NPEA_ETH)
|
||||
|
||||
/* IXP46x CPU (including IXP455) only */
|
||||
#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
|
||||
#define IXP4XX_FEATURE_RSA (1 << 21)
|
||||
#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
|
||||
IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
|
||||
IXP4XX_FEATURE_RSA)
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP4XX
|
||||
#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
|
||||
IXP42X_PROCESSOR_ID_VALUE)
|
||||
#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
|
||||
IXP42X_PROCESSOR_ID_VALUE)
|
||||
#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
|
||||
IXP43X_PROCESSOR_ID_VALUE)
|
||||
#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
|
||||
IXP46X_PROCESSOR_ID_VALUE)
|
||||
static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
regmap_read(rmap, IXP4XX_EXP_CNFG2, &val);
|
||||
/* For some reason this register is inverted */
|
||||
val = ~val;
|
||||
if (cpu_is_ixp42x_rev_a0())
|
||||
return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
|
||||
IXP4XX_FEATURE_AES);
|
||||
if (cpu_is_ixp42x())
|
||||
return val & IXP42X_FEATURE_MASK;
|
||||
if (cpu_is_ixp43x())
|
||||
return val & IXP43X_FEATURE_MASK;
|
||||
return val & IXP46X_FEATURE_MASK;
|
||||
}
|
||||
#else
|
||||
#define cpu_is_ixp42x_rev_a0() 0
|
||||
#define cpu_is_ixp42x() 0
|
||||
#define cpu_is_ixp43x() 0
|
||||
#define cpu_is_ixp46x() 0
|
||||
static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARCH_CPU_H */
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __IXP4XX_NPE_H
|
||||
#define __IXP4XX_NPE_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
extern const char *npe_names[];
|
||||
|
||||
struct npe_regs {
|
||||
u32 exec_addr, exec_data, exec_status_cmd, exec_count;
|
||||
u32 action_points[4];
|
||||
u32 watchpoint_fifo, watch_count;
|
||||
u32 profile_count;
|
||||
u32 messaging_status, messaging_control;
|
||||
u32 mailbox_status, /*messaging_*/ in_out_fifo;
|
||||
};
|
||||
|
||||
struct npe {
|
||||
struct npe_regs __iomem *regs;
|
||||
struct regmap *rmap;
|
||||
int id;
|
||||
int valid;
|
||||
};
|
||||
|
||||
|
||||
static inline const char *npe_name(struct npe *npe)
|
||||
{
|
||||
return npe_names[npe->id];
|
||||
}
|
||||
|
||||
int npe_running(struct npe *npe);
|
||||
int npe_send_message(struct npe *npe, const void *msg, const char *what);
|
||||
int npe_recv_message(struct npe *npe, void *msg, const char *what);
|
||||
int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
|
||||
int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
|
||||
struct npe *npe_request(unsigned id);
|
||||
void npe_release(struct npe *npe);
|
||||
|
||||
#endif /* __IXP4XX_NPE_H */
|
||||
@@ -0,0 +1,88 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
|
||||
*/
|
||||
|
||||
#ifndef IXP4XX_QMGR_H
|
||||
#define IXP4XX_QMGR_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define DEBUG_QMGR 0
|
||||
|
||||
#define HALF_QUEUES 32
|
||||
#define QUEUES 64
|
||||
#define MAX_QUEUE_LENGTH 4 /* in dwords */
|
||||
|
||||
#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
|
||||
#define QUEUE_STAT1_NEARLY_EMPTY 2
|
||||
#define QUEUE_STAT1_NEARLY_FULL 4
|
||||
#define QUEUE_STAT1_FULL 8
|
||||
#define QUEUE_STAT2_UNDERFLOW 1
|
||||
#define QUEUE_STAT2_OVERFLOW 2
|
||||
|
||||
#define QUEUE_WATERMARK_0_ENTRIES 0
|
||||
#define QUEUE_WATERMARK_1_ENTRY 1
|
||||
#define QUEUE_WATERMARK_2_ENTRIES 2
|
||||
#define QUEUE_WATERMARK_4_ENTRIES 3
|
||||
#define QUEUE_WATERMARK_8_ENTRIES 4
|
||||
#define QUEUE_WATERMARK_16_ENTRIES 5
|
||||
#define QUEUE_WATERMARK_32_ENTRIES 6
|
||||
#define QUEUE_WATERMARK_64_ENTRIES 7
|
||||
|
||||
/* queue interrupt request conditions */
|
||||
#define QUEUE_IRQ_SRC_EMPTY 0
|
||||
#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
|
||||
#define QUEUE_IRQ_SRC_NEARLY_FULL 2
|
||||
#define QUEUE_IRQ_SRC_FULL 3
|
||||
#define QUEUE_IRQ_SRC_NOT_EMPTY 4
|
||||
#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
|
||||
#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
|
||||
#define QUEUE_IRQ_SRC_NOT_FULL 7
|
||||
|
||||
struct qmgr_regs {
|
||||
u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
|
||||
u32 stat1[4]; /* 0x400 - 0x40F */
|
||||
u32 stat2[2]; /* 0x410 - 0x417 */
|
||||
u32 statne_h; /* 0x418 - queue nearly empty */
|
||||
u32 statf_h; /* 0x41C - queue full */
|
||||
u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
|
||||
u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
|
||||
u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
|
||||
u32 reserved[1776];
|
||||
u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
|
||||
};
|
||||
|
||||
void qmgr_put_entry(unsigned int queue, u32 val);
|
||||
u32 qmgr_get_entry(unsigned int queue);
|
||||
int qmgr_stat_empty(unsigned int queue);
|
||||
int qmgr_stat_below_low_watermark(unsigned int queue);
|
||||
int qmgr_stat_full(unsigned int queue);
|
||||
int qmgr_stat_overflow(unsigned int queue);
|
||||
void qmgr_release_queue(unsigned int queue);
|
||||
void qmgr_set_irq(unsigned int queue, int src,
|
||||
void (*handler)(void *pdev), void *pdev);
|
||||
void qmgr_enable_irq(unsigned int queue);
|
||||
void qmgr_disable_irq(unsigned int queue);
|
||||
|
||||
/* request_ and release_queue() must be called from non-IRQ context */
|
||||
|
||||
#if DEBUG_QMGR
|
||||
extern char qmgr_queue_descs[QUEUES][32];
|
||||
|
||||
int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
|
||||
unsigned int nearly_empty_watermark,
|
||||
unsigned int nearly_full_watermark,
|
||||
const char *desc_format, const char* name);
|
||||
#else
|
||||
int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
|
||||
unsigned int nearly_empty_watermark,
|
||||
unsigned int nearly_full_watermark);
|
||||
#define qmgr_request_queue(queue, len, nearly_empty_watermark, \
|
||||
nearly_full_watermark, desc_format, name) \
|
||||
__qmgr_request_queue(queue, len, nearly_empty_watermark, \
|
||||
nearly_full_watermark)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only
|
||||
* Copyright (C) 2020 Marvell.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_OTX2_ASM_H
|
||||
#define __SOC_OTX2_ASM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#if defined(CONFIG_ARM64)
|
||||
/*
|
||||
* otx2_lmt_flush is used for LMT store operation.
|
||||
* On octeontx2 platform CPT instruction enqueue and
|
||||
* NIX packet send are only possible via LMTST
|
||||
* operations and it uses LDEOR instruction targeting
|
||||
* the coprocessor address.
|
||||
*/
|
||||
#define otx2_lmt_flush(ioaddr) \
|
||||
({ \
|
||||
u64 result = 0; \
|
||||
__asm__ volatile(".cpu generic+lse\n" \
|
||||
"ldeor xzr, %x[rf], [%[rs]]" \
|
||||
: [rf]"=r" (result) \
|
||||
: [rs]"r" (ioaddr)); \
|
||||
(result); \
|
||||
})
|
||||
/*
|
||||
* STEORL store to memory with release semantics.
|
||||
* This will avoid using DMB barrier after each LMTST
|
||||
* operation.
|
||||
*/
|
||||
#define cn10k_lmt_flush(val, addr) \
|
||||
({ \
|
||||
__asm__ volatile(".cpu generic+lse\n" \
|
||||
"steorl %x[rf],[%[rs]]" \
|
||||
: [rf] "+r"(val) \
|
||||
: [rs] "r"(addr)); \
|
||||
})
|
||||
|
||||
static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr)
|
||||
{
|
||||
u64 result;
|
||||
|
||||
asm volatile (".cpu generic+lse\n"
|
||||
"ldadda %x[i], %x[r], [%[b]]"
|
||||
: [r] "=r" (result), "+m" (*ptr)
|
||||
: [i] "r" (incr), [b] "r" (ptr)
|
||||
: "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
#else
|
||||
#define otx2_lmt_flush(ioaddr) ({ 0; })
|
||||
#define cn10k_lmt_flush(val, addr) ({ addr = val; })
|
||||
#define otx2_atomic64_fetch_add(incr, ptr) ({ incr; })
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_OTX2_ASM_H */
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only
|
||||
* Copyright (C) 2024 Marvell.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_SILICON_H
|
||||
#define __SOC_SILICON_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#if defined(CONFIG_ARM64)
|
||||
|
||||
#define CN20K_CHIPID 0x20
|
||||
/*
|
||||
* Silicon check for CN20K family
|
||||
*/
|
||||
static inline bool is_cn20k(struct pci_dev *pdev)
|
||||
{
|
||||
return (pdev->subsystem_device & 0xFF) == CN20K_CHIPID;
|
||||
}
|
||||
#else
|
||||
#define is_cn20k(pdev) ((void)(pdev), 0)
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_SILICON_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
* Copyright (c) 2024 Collabora Ltd.
|
||||
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef __MEDIATEK_DVFSRC_H
|
||||
#define __MEDIATEK_DVFSRC_H
|
||||
|
||||
enum mtk_dvfsrc_cmd {
|
||||
MTK_DVFSRC_CMD_BW,
|
||||
MTK_DVFSRC_CMD_HRT_BW,
|
||||
MTK_DVFSRC_CMD_PEAK_BW,
|
||||
MTK_DVFSRC_CMD_OPP,
|
||||
MTK_DVFSRC_CMD_VCORE_LEVEL,
|
||||
MTK_DVFSRC_CMD_VSCP_LEVEL,
|
||||
MTK_DVFSRC_CMD_MAX,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTK_DVFSRC)
|
||||
|
||||
int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data);
|
||||
int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data);
|
||||
|
||||
#else
|
||||
|
||||
static inline int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)
|
||||
{ return -ENODEV; }
|
||||
|
||||
static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data)
|
||||
{ return -ENODEV; }
|
||||
|
||||
#endif /* CONFIG_MTK_DVFSRC */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,457 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __SOC_MEDIATEK_INFRACFG_H
|
||||
#define __SOC_MEDIATEK_INFRACFG_H
|
||||
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
|
||||
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
|
||||
|
||||
#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
|
||||
#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
|
||||
#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
|
||||
#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
|
||||
#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
|
||||
#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
|
||||
#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
|
||||
#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
|
||||
|
||||
#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
|
||||
#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
|
||||
#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
|
||||
|
||||
#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
|
||||
#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
|
||||
#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
|
||||
#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
|
||||
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
|
||||
#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
|
||||
#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
|
||||
#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22)
|
||||
#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28))
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29))
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13)
|
||||
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14)
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19))
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20)
|
||||
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21)
|
||||
|
||||
#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
|
||||
#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
#define MT8192_TOP_AXI_PROT_EN_CLR 0x2a4
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_SET 0x2a8
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_CLR 0x2ac
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_SET 0x2d4
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_CLR 0x2d8
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_STA1 0x2ec
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_SET 0x714
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_CLR 0x718
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_STA1 0x724
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_SET 0xb84
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
|
||||
|
||||
#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23))
|
||||
#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18))
|
||||
#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10)
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21)
|
||||
#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22)
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0)
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3)
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4)
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)
|
||||
#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
|
||||
BIT(10) | BIT(12) | \
|
||||
BIT(14) | BIT(16) | \
|
||||
BIT(24) | BIT(26))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \
|
||||
BIT(15) | BIT(17) | \
|
||||
BIT(25) | BIT(27))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0
|
||||
#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4
|
||||
#define MT8188_TOP_AXI_PROT_EN_STA 0x228
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7)
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \
|
||||
BIT(27))
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8)
|
||||
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
|
||||
#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6)
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4))
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0)
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1)
|
||||
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8
|
||||
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0)
|
||||
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2)
|
||||
|
||||
#define MT8188_SMI_LARB10_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11A_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11C_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB12_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11B_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB15_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0
|
||||
|
||||
#define MT8188_SMI_LARB10_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB11A_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB11C_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB12_RESET BIT(8)
|
||||
#define MT8188_SMI_LARB11B_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB15_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB16B_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB17B_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB16A_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB17A_RESET BIT(4)
|
||||
|
||||
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
|
||||
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
|
||||
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
|
||||
|
||||
/* MFG1 */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
|
||||
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
|
||||
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
|
||||
/* DIS */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
|
||||
#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
|
||||
/* IMG */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
|
||||
/* IPE */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
|
||||
/* CAM */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
|
||||
/* VENC */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
|
||||
/* VDEC */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
|
||||
/* WPE */
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
|
||||
/* CONN_ON */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
|
||||
/* ADSP_TOP */
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
|
||||
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
|
||||
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
#define MT8183_TOP_AXI_PROT_EN_CLR 0x2a4
|
||||
#define MT8183_TOP_AXI_PROT_EN_1_SET 0x2a8
|
||||
#define MT8183_TOP_AXI_PROT_EN_1_CLR 0x2ac
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_SET 0x2c4
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_CLR 0x2c8
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_STA1 0x2e4
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_SET 0x2d4
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_CLR 0x2d8
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_STA1 0x2ec
|
||||
|
||||
#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
|
||||
#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
|
||||
#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
|
||||
#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
|
||||
#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
|
||||
#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
|
||||
BIT(9) | BIT(13))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
|
||||
BIT(12))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
|
||||
BIT(4))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
|
||||
BIT(5))
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
|
||||
#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
|
||||
|
||||
#define MT8183_SMI_COMMON_CLAMP_EN 0x3c0
|
||||
#define MT8183_SMI_COMMON_CLAMP_EN_SET 0x3c4
|
||||
#define MT8183_SMI_COMMON_CLAMP_EN_CLR 0x3c8
|
||||
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
|
||||
#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
|
||||
|
||||
#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
|
||||
#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
|
||||
#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
|
||||
#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
|
||||
#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
|
||||
#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
|
||||
#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
|
||||
#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
|
||||
|
||||
#define MT8167_TOP_AXI_PROT_EN_MM_EMI BIT(1)
|
||||
#define MT8167_TOP_AXI_PROT_EN_MCU_MFG BIT(2)
|
||||
#define MT8167_TOP_AXI_PROT_EN_CONN_EMI BIT(4)
|
||||
#define MT8167_TOP_AXI_PROT_EN_MFG_EMI BIT(5)
|
||||
#define MT8167_TOP_AXI_PROT_EN_CONN_MCU BIT(8)
|
||||
#define MT8167_TOP_AXI_PROT_EN_MCU_CONN BIT(9)
|
||||
#define MT8167_TOP_AXI_PROT_EN_MCU_MM BIT(11)
|
||||
|
||||
#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
|
||||
#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
|
||||
#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
|
||||
|
||||
#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
|
||||
#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
|
||||
#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
|
||||
BIT(28))
|
||||
#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
|
||||
BIT(7) | BIT(8))
|
||||
|
||||
#define MT6735_TOP_AXI_PROT_EN_CONN (BIT(2) | BIT(8))
|
||||
#define MT6735_TOP_AXI_PROT_EN_MD1 (BIT(24) | BIT(25) | \
|
||||
BIT(26) | BIT(27) | \
|
||||
BIT(28))
|
||||
|
||||
#define INFRA_TOPAXI_PROTECTEN 0x0220
|
||||
#define INFRA_TOPAXI_PROTECTSTA1 0x0228
|
||||
#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
|
||||
#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
|
||||
|
||||
#define MT8192_INFRA_CTRL 0x290
|
||||
#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9)
|
||||
|
||||
#define REG_INFRA_MISC 0xf00
|
||||
#define F_DDR_4GB_SUPPORT_EN BIT(13)
|
||||
|
||||
int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
|
||||
bool reg_update);
|
||||
int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
|
||||
bool reg_update);
|
||||
#endif /* __SOC_MEDIATEK_INFRACFG_H */
|
||||
@@ -0,0 +1,609 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MTK_CMDQ_H__
|
||||
#define __MTK_CMDQ_H__
|
||||
|
||||
#include <linux/mailbox_client.h>
|
||||
#include <linux/mailbox/mtk-cmdq-mailbox.h>
|
||||
#include <linux/timer.h>
|
||||
|
||||
#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))
|
||||
#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))
|
||||
|
||||
/*
|
||||
* Every cmdq thread has its own SPRs (Specific Purpose Registers),
|
||||
* so there are 4 * N (threads) SPRs in GCE that shares the same indexes below.
|
||||
*/
|
||||
#define CMDQ_THR_SPR_IDX0 (0)
|
||||
#define CMDQ_THR_SPR_IDX1 (1)
|
||||
#define CMDQ_THR_SPR_IDX2 (2)
|
||||
#define CMDQ_THR_SPR_IDX3 (3)
|
||||
|
||||
#define CMDQ_SUBSYS_INVALID (U8_MAX)
|
||||
|
||||
struct cmdq_pkt;
|
||||
|
||||
enum cmdq_logic_op {
|
||||
CMDQ_LOGIC_ASSIGN = 0,
|
||||
CMDQ_LOGIC_ADD = 1,
|
||||
CMDQ_LOGIC_SUBTRACT = 2,
|
||||
CMDQ_LOGIC_MULTIPLY = 3,
|
||||
CMDQ_LOGIC_XOR = 8,
|
||||
CMDQ_LOGIC_NOT = 9,
|
||||
CMDQ_LOGIC_OR = 10,
|
||||
CMDQ_LOGIC_AND = 11,
|
||||
CMDQ_LOGIC_LEFT_SHIFT = 12,
|
||||
CMDQ_LOGIC_RIGHT_SHIFT = 13,
|
||||
CMDQ_LOGIC_MAX,
|
||||
};
|
||||
|
||||
struct cmdq_operand {
|
||||
/* register type */
|
||||
bool reg;
|
||||
union {
|
||||
/* index */
|
||||
u16 idx;
|
||||
/* value */
|
||||
u16 value;
|
||||
};
|
||||
};
|
||||
|
||||
struct cmdq_client_reg {
|
||||
u8 subsys;
|
||||
phys_addr_t pa_base;
|
||||
u16 offset;
|
||||
u16 size;
|
||||
|
||||
/*
|
||||
* Client only uses these functions for MMIO access,
|
||||
* so doesn't need to handle the mminfra_offset.
|
||||
* The mminfra_offset is used for DRAM access and
|
||||
* is handled internally by CMDQ APIs.
|
||||
*/
|
||||
int (*pkt_write)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,
|
||||
u16 offset, u32 value);
|
||||
int (*pkt_write_mask)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,
|
||||
u16 offset, u32 value, u32 mask);
|
||||
};
|
||||
|
||||
struct cmdq_client {
|
||||
struct mbox_client client;
|
||||
struct mbox_chan *chan;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTK_CMDQ)
|
||||
|
||||
/**
|
||||
* cmdq_dev_get_client_reg() - parse cmdq client reg from the device
|
||||
* node of CMDQ client
|
||||
* @dev: device of CMDQ mailbox client
|
||||
* @client_reg: CMDQ client reg pointer
|
||||
* @idx: the index of desired reg
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*
|
||||
* Help CMDQ client parsing the cmdq client reg
|
||||
* from the device node of CMDQ client.
|
||||
*/
|
||||
int cmdq_dev_get_client_reg(struct device *dev,
|
||||
struct cmdq_client_reg *client_reg, int idx);
|
||||
|
||||
/**
|
||||
* cmdq_mbox_create() - create CMDQ mailbox client and channel
|
||||
* @dev: device of CMDQ mailbox client
|
||||
* @index: index of CMDQ mailbox channel
|
||||
*
|
||||
* Return: CMDQ mailbox client pointer
|
||||
*/
|
||||
struct cmdq_client *cmdq_mbox_create(struct device *dev, int index);
|
||||
|
||||
/**
|
||||
* cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
|
||||
* @client: the CMDQ mailbox client
|
||||
*/
|
||||
void cmdq_mbox_destroy(struct cmdq_client *client);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_create() - create a CMDQ packet
|
||||
* @client: the CMDQ mailbox client
|
||||
* @pkt: the CMDQ packet
|
||||
* @size: required CMDQ buffer size
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_destroy() - destroy the CMDQ packet
|
||||
* @client: the CMDQ mailbox client
|
||||
* @pkt: the CMDQ packet
|
||||
*/
|
||||
void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write() - append write command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_pa() - append write command to the CMDQ packet with pa_base
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: unused parameter
|
||||
* @pa_base: the physical address base of the hardware register
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
|
||||
u32 pa_base, u16 offset, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_subsys() - append write command to the CMDQ packet with subsys
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @pa_base: unused parameter
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u32 pa_base /*unused*/, u16 offset, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
* @mask: the specified target register mask
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_mask_pa() - append write command with mask to the CMDQ packet with pa
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: unused parameter
|
||||
* @pa_base: the physical address base of the hardware register
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
* @mask: the specified target register mask
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
|
||||
u32 pa_base, u16 offset, u32 value, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_mask_subsys() - append write command with mask to the CMDQ packet with subsys
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @pa_base: unused parameter
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
* @mask: the specified target register mask
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u32 pa_base /*unused*/, u16 offset, u32 value, u32 mask);
|
||||
|
||||
/*
|
||||
* cmdq_pkt_read_s() - append read_s command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @high_addr_reg_idx: internal register ID which contains high address of pa
|
||||
* @addr_low: low address of pa
|
||||
* @reg_idx: the CMDQ internal register ID to cache read data
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
|
||||
u16 reg_idx);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_s() - append write_s command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @high_addr_reg_idx: internal register ID which contains high address of pa
|
||||
* @addr_low: low address of pa
|
||||
* @src_reg_idx: the CMDQ internal register ID which cache source value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*
|
||||
* Support write value to physical address without subsys. Use CMDQ_ADDR_HIGH()
|
||||
* to get high address and call cmdq_pkt_assign() to assign value into internal
|
||||
* reg. Also use CMDQ_ADDR_LOW() to get low address for addr_low parameter when
|
||||
* call to this function.
|
||||
*/
|
||||
int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
|
||||
u16 addr_low, u16 src_reg_idx);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_s_mask() - append write_s with mask command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @high_addr_reg_idx: internal register ID which contains high address of pa
|
||||
* @addr_low: low address of pa
|
||||
* @src_reg_idx: the CMDQ internal register ID which cache source value
|
||||
* @mask: the specified target address mask, use U32_MAX if no need
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*
|
||||
* Support write value to physical address without subsys. Use CMDQ_ADDR_HIGH()
|
||||
* to get high address and call cmdq_pkt_assign() to assign value into internal
|
||||
* reg. Also use CMDQ_ADDR_LOW() to get low address for addr_low parameter when
|
||||
* call to this function.
|
||||
*/
|
||||
int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
|
||||
u16 addr_low, u16 src_reg_idx, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_s_value() - append write_s command to the CMDQ packet which
|
||||
* write value to a physical address
|
||||
* @pkt: the CMDQ packet
|
||||
* @high_addr_reg_idx: internal register ID which contains high address of pa
|
||||
* @addr_low: low address of pa
|
||||
* @value: the specified target value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
|
||||
u16 addr_low, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_write_s_mask_value() - append write_s command with mask to the CMDQ
|
||||
* packet which write value to a physical
|
||||
* address
|
||||
* @pkt: the CMDQ packet
|
||||
* @high_addr_reg_idx: internal register ID which contains high address of pa
|
||||
* @addr_low: low address of pa
|
||||
* @value: the specified target value
|
||||
* @mask: the specified target mask
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
|
||||
u16 addr_low, u32 value, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_mem_move() - append memory move command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @src_addr: source address
|
||||
* @dst_addr: destination address
|
||||
*
|
||||
* Appends a CMDQ command to copy the value found in `src_addr` to `dst_addr`.
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @event: the desired event type to wait
|
||||
* @clear: clear event or not after event arrive
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_acquire_event() - append acquire event command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @event: the desired event to be acquired
|
||||
*
|
||||
* User can use cmdq_pkt_acquire_event() as `mutex_lock` and cmdq_pkt_clear_event()
|
||||
* as `mutex_unlock` to protect some `critical section` instructions between them.
|
||||
* cmdq_pkt_acquire_event() would wait for event to be cleared.
|
||||
* After event is cleared by cmdq_pkt_clear_event in other GCE threads,
|
||||
* cmdq_pkt_acquire_event() would set event and keep executing next instruction.
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @event: the desired event to be cleared
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_set_event() - append set event command to the CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @event: the desired event to be set
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
|
||||
* execute an instruction that wait for a specified
|
||||
* hardware register to check for the value w/o mask.
|
||||
* All GCE hardware threads will be blocked by this
|
||||
* instruction.
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_poll_mask() - Append polling command to the CMDQ packet, ask GCE to
|
||||
* execute an instruction that wait for a specified
|
||||
* hardware register to check for the value w/ mask.
|
||||
* All GCE hardware threads will be blocked by this
|
||||
* instruction.
|
||||
* @pkt: the CMDQ packet
|
||||
* @subsys: the CMDQ sub system code
|
||||
* @offset: register offset from CMDQ sub system
|
||||
* @value: the specified target register value
|
||||
* @mask: the specified target register mask
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_logic_command() - Append logic command to the CMDQ packet, ask GCE to
|
||||
* execute an instruction that store the result of logic operation
|
||||
* with left and right operand into result_reg_idx.
|
||||
* @pkt: the CMDQ packet
|
||||
* @result_reg_idx: SPR index that store operation result of left_operand and right_operand
|
||||
* @left_operand: left operand
|
||||
* @s_op: the logic operator enum
|
||||
* @right_operand: right operand
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, u16 result_reg_idx,
|
||||
struct cmdq_operand *left_operand,
|
||||
enum cmdq_logic_op s_op,
|
||||
struct cmdq_operand *right_operand);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask GCE
|
||||
* to execute an instruction that set a constant value into
|
||||
* internal register and use as value, mask or address in
|
||||
* read/write instruction.
|
||||
* @pkt: the CMDQ packet
|
||||
* @reg_idx: the CMDQ internal register ID
|
||||
* @value: the specified value
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_poll_addr() - Append blocking POLL command to CMDQ packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @addr: the hardware register address
|
||||
* @value: the specified target register value
|
||||
* @mask: the specified target register mask
|
||||
*
|
||||
* Appends a polling (POLL) command to the CMDQ packet and asks the GCE
|
||||
* to execute an instruction that checks for the specified `value` (with
|
||||
* or without `mask`) to appear in the specified hardware register `addr`.
|
||||
* All GCE threads will be blocked by this instruction.
|
||||
*
|
||||
* Return: 0 for success or negative error code
|
||||
*/
|
||||
int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_jump_abs() - Append jump command to the CMDQ packet, ask GCE
|
||||
* to execute an instruction that change current thread
|
||||
* PC to a absolute physical address which should
|
||||
* contains more instruction.
|
||||
* @pkt: the CMDQ packet
|
||||
* @addr: absolute physical address of target instruction buffer
|
||||
* @shift_pa: shift bits of physical address in CMDQ instruction. This value
|
||||
* is got by cmdq_get_shift_pa().
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa);
|
||||
|
||||
/* This wrapper has to be removed after all users migrated to jump_abs */
|
||||
static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
|
||||
{
|
||||
return cmdq_pkt_jump_abs(pkt, addr, shift_pa);
|
||||
}
|
||||
|
||||
/**
|
||||
* cmdq_pkt_jump_rel() - Append jump command to the CMDQ packet, ask GCE
|
||||
* to execute an instruction that change current thread
|
||||
* PC to a physical address with relative offset. The
|
||||
* target address should contains more instruction.
|
||||
* @pkt: the CMDQ packet
|
||||
* @offset: relative offset of target instruction buffer from current PC.
|
||||
* @shift_pa: shift bits of physical address in CMDQ instruction. This value
|
||||
* is got by cmdq_get_shift_pa().
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*/
|
||||
int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa);
|
||||
|
||||
/**
|
||||
* cmdq_pkt_eoc() - Append EOC and ask GCE to generate an IRQ at end of execution
|
||||
* @pkt: The CMDQ packet
|
||||
*
|
||||
* Appends an End Of Code (EOC) command to the CMDQ packet and asks the GCE
|
||||
* to generate an interrupt at the end of the execution of all commands in
|
||||
* the pipeline.
|
||||
* The EOC command is usually appended to the end of the pipeline to notify
|
||||
* that all commands are done.
|
||||
*
|
||||
* Return: 0 for success or negative error number
|
||||
*/
|
||||
int cmdq_pkt_eoc(struct cmdq_pkt *pkt);
|
||||
|
||||
#else /* IS_ENABLED(CONFIG_MTK_CMDQ) */
|
||||
|
||||
static inline int cmdq_dev_get_client_reg(struct device *dev,
|
||||
struct cmdq_client_reg *client_reg, int idx)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline struct cmdq_client *cmdq_mbox_create(struct device *dev, int index)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline void cmdq_mbox_destroy(struct cmdq_client *client) { }
|
||||
|
||||
static inline int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) { }
|
||||
|
||||
static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
|
||||
u32 pa_base, u16 offset, u32 value)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u32 pa_base /*unused*/, u16 offset, u32 value)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value, u32 mask)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
|
||||
u32 pa_base, u16 offset, u32 value, u32 mask)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u32 pa_base /*unused*/, u16 offset,
|
||||
u32 value, u32 mask)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
|
||||
u16 addr_low, u16 reg_idx)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
|
||||
u16 addr_low, u16 src_reg_idx)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
|
||||
u16 addr_low, u16 src_reg_idx, u32 mask)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
|
||||
u16 addr_low, u32 value)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
|
||||
u16 addr_low, u32 value, u32 mask)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
|
||||
u16 offset, u32 value, u32 mask)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int cmdq_pkt_eoc(struct cmdq_pkt *pkt)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif /* IS_ENABLED(CONFIG_MTK_CMDQ) */
|
||||
|
||||
#endif /* __MTK_CMDQ_H__ */
|
||||
@@ -0,0 +1,115 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef __MTK_MMSYS_H
|
||||
#define __MTK_MMSYS_H
|
||||
|
||||
#include <linux/mailbox_controller.h>
|
||||
#include <linux/mailbox/mtk-cmdq-mailbox.h>
|
||||
#include <linux/soc/mediatek/mtk-cmdq.h>
|
||||
|
||||
enum mtk_ddp_comp_id;
|
||||
struct device;
|
||||
|
||||
enum mtk_dpi_out_format_con {
|
||||
MTK_DPI_RGB888_SDR_CON,
|
||||
MTK_DPI_RGB888_DDR_CON,
|
||||
MTK_DPI_RGB565_SDR_CON,
|
||||
MTK_DPI_RGB565_DDR_CON
|
||||
};
|
||||
|
||||
enum mtk_ddp_comp_id {
|
||||
DDP_COMPONENT_AAL0,
|
||||
DDP_COMPONENT_AAL1,
|
||||
DDP_COMPONENT_BLS,
|
||||
DDP_COMPONENT_CCORR,
|
||||
DDP_COMPONENT_COLOR0,
|
||||
DDP_COMPONENT_COLOR1,
|
||||
DDP_COMPONENT_DITHER0,
|
||||
DDP_COMPONENT_DITHER1,
|
||||
DDP_COMPONENT_DP_INTF0,
|
||||
DDP_COMPONENT_DP_INTF1,
|
||||
DDP_COMPONENT_DPI0,
|
||||
DDP_COMPONENT_DPI1,
|
||||
DDP_COMPONENT_DSC0,
|
||||
DDP_COMPONENT_DSC1,
|
||||
DDP_COMPONENT_DSI0,
|
||||
DDP_COMPONENT_DSI1,
|
||||
DDP_COMPONENT_DSI2,
|
||||
DDP_COMPONENT_DSI3,
|
||||
DDP_COMPONENT_ETHDR_MIXER,
|
||||
DDP_COMPONENT_GAMMA,
|
||||
DDP_COMPONENT_MDP_RDMA0,
|
||||
DDP_COMPONENT_MDP_RDMA1,
|
||||
DDP_COMPONENT_MDP_RDMA2,
|
||||
DDP_COMPONENT_MDP_RDMA3,
|
||||
DDP_COMPONENT_MDP_RDMA4,
|
||||
DDP_COMPONENT_MDP_RDMA5,
|
||||
DDP_COMPONENT_MDP_RDMA6,
|
||||
DDP_COMPONENT_MDP_RDMA7,
|
||||
DDP_COMPONENT_MERGE0,
|
||||
DDP_COMPONENT_MERGE1,
|
||||
DDP_COMPONENT_MERGE2,
|
||||
DDP_COMPONENT_MERGE3,
|
||||
DDP_COMPONENT_MERGE4,
|
||||
DDP_COMPONENT_MERGE5,
|
||||
DDP_COMPONENT_OD0,
|
||||
DDP_COMPONENT_OD1,
|
||||
DDP_COMPONENT_OVL0,
|
||||
DDP_COMPONENT_OVL_2L0,
|
||||
DDP_COMPONENT_OVL_2L1,
|
||||
DDP_COMPONENT_OVL_2L2,
|
||||
DDP_COMPONENT_OVL1,
|
||||
DDP_COMPONENT_PADDING0,
|
||||
DDP_COMPONENT_PADDING1,
|
||||
DDP_COMPONENT_PADDING2,
|
||||
DDP_COMPONENT_PADDING3,
|
||||
DDP_COMPONENT_PADDING4,
|
||||
DDP_COMPONENT_PADDING5,
|
||||
DDP_COMPONENT_PADDING6,
|
||||
DDP_COMPONENT_PADDING7,
|
||||
DDP_COMPONENT_POSTMASK0,
|
||||
DDP_COMPONENT_PWM0,
|
||||
DDP_COMPONENT_PWM1,
|
||||
DDP_COMPONENT_PWM2,
|
||||
DDP_COMPONENT_RDMA0,
|
||||
DDP_COMPONENT_RDMA1,
|
||||
DDP_COMPONENT_RDMA2,
|
||||
DDP_COMPONENT_RDMA4,
|
||||
DDP_COMPONENT_UFOE,
|
||||
DDP_COMPONENT_WDMA0,
|
||||
DDP_COMPONENT_WDMA1,
|
||||
DDP_COMPONENT_ID_MAX,
|
||||
};
|
||||
|
||||
void mtk_mmsys_ddp_connect(struct device *dev,
|
||||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next);
|
||||
|
||||
void mtk_mmsys_ddp_disconnect(struct device *dev,
|
||||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next);
|
||||
|
||||
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
|
||||
|
||||
void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width,
|
||||
int height, struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
|
||||
struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
|
||||
u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
|
||||
struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,
|
||||
struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,
|
||||
struct cmdq_pkt *cmdq_pkt);
|
||||
|
||||
#endif /* __MTK_MMSYS_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef MTK_MUTEX_H
|
||||
#define MTK_MUTEX_H
|
||||
|
||||
struct regmap;
|
||||
struct device;
|
||||
struct mtk_mutex;
|
||||
|
||||
enum mtk_mutex_mod_index {
|
||||
/* MDP table index */
|
||||
MUTEX_MOD_IDX_MDP_RDMA0,
|
||||
MUTEX_MOD_IDX_MDP_RSZ0,
|
||||
MUTEX_MOD_IDX_MDP_RSZ1,
|
||||
MUTEX_MOD_IDX_MDP_TDSHP0,
|
||||
MUTEX_MOD_IDX_MDP_WROT0,
|
||||
MUTEX_MOD_IDX_MDP_WDMA,
|
||||
MUTEX_MOD_IDX_MDP_AAL0,
|
||||
MUTEX_MOD_IDX_MDP_CCORR0,
|
||||
MUTEX_MOD_IDX_MDP_HDR0,
|
||||
MUTEX_MOD_IDX_MDP_COLOR0,
|
||||
MUTEX_MOD_IDX_MDP_RDMA1,
|
||||
MUTEX_MOD_IDX_MDP_RDMA2,
|
||||
MUTEX_MOD_IDX_MDP_RDMA3,
|
||||
MUTEX_MOD_IDX_MDP_STITCH0,
|
||||
MUTEX_MOD_IDX_MDP_FG0,
|
||||
MUTEX_MOD_IDX_MDP_FG1,
|
||||
MUTEX_MOD_IDX_MDP_FG2,
|
||||
MUTEX_MOD_IDX_MDP_FG3,
|
||||
MUTEX_MOD_IDX_MDP_HDR1,
|
||||
MUTEX_MOD_IDX_MDP_HDR2,
|
||||
MUTEX_MOD_IDX_MDP_HDR3,
|
||||
MUTEX_MOD_IDX_MDP_AAL1,
|
||||
MUTEX_MOD_IDX_MDP_AAL2,
|
||||
MUTEX_MOD_IDX_MDP_AAL3,
|
||||
MUTEX_MOD_IDX_MDP_RSZ2,
|
||||
MUTEX_MOD_IDX_MDP_RSZ3,
|
||||
MUTEX_MOD_IDX_MDP_MERGE2,
|
||||
MUTEX_MOD_IDX_MDP_MERGE3,
|
||||
MUTEX_MOD_IDX_MDP_TDSHP1,
|
||||
MUTEX_MOD_IDX_MDP_TDSHP2,
|
||||
MUTEX_MOD_IDX_MDP_TDSHP3,
|
||||
MUTEX_MOD_IDX_MDP_COLOR1,
|
||||
MUTEX_MOD_IDX_MDP_COLOR2,
|
||||
MUTEX_MOD_IDX_MDP_COLOR3,
|
||||
MUTEX_MOD_IDX_MDP_OVL0,
|
||||
MUTEX_MOD_IDX_MDP_OVL1,
|
||||
MUTEX_MOD_IDX_MDP_PAD0,
|
||||
MUTEX_MOD_IDX_MDP_PAD1,
|
||||
MUTEX_MOD_IDX_MDP_PAD2,
|
||||
MUTEX_MOD_IDX_MDP_PAD3,
|
||||
MUTEX_MOD_IDX_MDP_TCC0,
|
||||
MUTEX_MOD_IDX_MDP_TCC1,
|
||||
MUTEX_MOD_IDX_MDP_WROT1,
|
||||
MUTEX_MOD_IDX_MDP_WROT2,
|
||||
MUTEX_MOD_IDX_MDP_WROT3,
|
||||
|
||||
MUTEX_MOD_IDX_MAX /* ALWAYS keep at the end */
|
||||
};
|
||||
|
||||
enum mtk_mutex_sof_index {
|
||||
MUTEX_SOF_IDX_SINGLE_MODE,
|
||||
|
||||
MUTEX_SOF_IDX_MAX /* ALWAYS keep at the end */
|
||||
};
|
||||
|
||||
struct mtk_mutex *mtk_mutex_get(struct device *dev);
|
||||
int mtk_mutex_prepare(struct mtk_mutex *mutex);
|
||||
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
|
||||
enum mtk_ddp_comp_id id);
|
||||
void mtk_mutex_enable(struct mtk_mutex *mutex);
|
||||
int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
|
||||
void *pkt);
|
||||
void mtk_mutex_disable(struct mtk_mutex *mutex);
|
||||
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
|
||||
enum mtk_ddp_comp_id id);
|
||||
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
|
||||
void mtk_mutex_put(struct mtk_mutex *mutex);
|
||||
void mtk_mutex_acquire(struct mtk_mutex *mutex);
|
||||
void mtk_mutex_release(struct mtk_mutex *mutex);
|
||||
int mtk_mutex_write_mod(struct mtk_mutex *mutex,
|
||||
enum mtk_mutex_mod_index idx,
|
||||
bool clear);
|
||||
int mtk_mutex_write_sof(struct mtk_mutex *mutex,
|
||||
enum mtk_mutex_sof_index idx);
|
||||
|
||||
#endif /* MTK_MUTEX_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 MediaTek Inc.
|
||||
*/
|
||||
#ifndef __MTK_SIP_SVC_H
|
||||
#define __MTK_SIP_SVC_H
|
||||
|
||||
/* Error Code */
|
||||
#define SIP_SVC_E_SUCCESS 0
|
||||
#define SIP_SVC_E_NOT_SUPPORTED -1
|
||||
#define SIP_SVC_E_INVALID_PARAMS -2
|
||||
#define SIP_SVC_E_INVALID_RANGE -3
|
||||
#define SIP_SVC_E_PERMISSION_DENIED -4
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
#define MTK_SIP_SMC_CONVENTION ARM_SMCCC_SMC_64
|
||||
#else
|
||||
#define MTK_SIP_SMC_CONVENTION ARM_SMCCC_SMC_32
|
||||
#endif
|
||||
|
||||
#define MTK_SIP_SMC_CMD(fn_id) \
|
||||
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
|
||||
ARM_SMCCC_OWNER_SIP, fn_id)
|
||||
|
||||
/* DVFSRC SMC calls */
|
||||
#define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506)
|
||||
|
||||
/* IOMMU related SMC call */
|
||||
#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,333 @@
|
||||
#ifndef __MTK_WED_H
|
||||
#define __MTK_WED_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/rcupdate.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
#define MTK_WED_TX_QUEUES 2
|
||||
#define MTK_WED_RX_QUEUES 2
|
||||
#define MTK_WED_RX_PAGE_QUEUES 3
|
||||
|
||||
#define WED_WO_STA_REC 0x6
|
||||
|
||||
struct mtk_wed_hw;
|
||||
struct mtk_wdma_desc;
|
||||
|
||||
enum mtk_wed_wo_cmd {
|
||||
MTK_WED_WO_CMD_WED_CFG,
|
||||
MTK_WED_WO_CMD_WED_RX_STAT,
|
||||
MTK_WED_WO_CMD_RRO_SER,
|
||||
MTK_WED_WO_CMD_DBG_INFO,
|
||||
MTK_WED_WO_CMD_DEV_INFO,
|
||||
MTK_WED_WO_CMD_BSS_INFO,
|
||||
MTK_WED_WO_CMD_STA_REC,
|
||||
MTK_WED_WO_CMD_DEV_INFO_DUMP,
|
||||
MTK_WED_WO_CMD_BSS_INFO_DUMP,
|
||||
MTK_WED_WO_CMD_STA_REC_DUMP,
|
||||
MTK_WED_WO_CMD_BA_INFO_DUMP,
|
||||
MTK_WED_WO_CMD_FBCMD_Q_DUMP,
|
||||
MTK_WED_WO_CMD_FW_LOG_CTRL,
|
||||
MTK_WED_WO_CMD_LOG_FLUSH,
|
||||
MTK_WED_WO_CMD_CHANGE_STATE,
|
||||
MTK_WED_WO_CMD_CPU_STATS_ENABLE,
|
||||
MTK_WED_WO_CMD_CPU_STATS_DUMP,
|
||||
MTK_WED_WO_CMD_EXCEPTION_INIT,
|
||||
MTK_WED_WO_CMD_PROF_CTRL,
|
||||
MTK_WED_WO_CMD_STA_BA_DUMP,
|
||||
MTK_WED_WO_CMD_BA_CTRL_DUMP,
|
||||
MTK_WED_WO_CMD_RXCNT_CTRL,
|
||||
MTK_WED_WO_CMD_RXCNT_INFO,
|
||||
MTK_WED_WO_CMD_SET_CAP,
|
||||
MTK_WED_WO_CMD_CCIF_RING_DUMP,
|
||||
MTK_WED_WO_CMD_WED_END
|
||||
};
|
||||
|
||||
struct mtk_wed_bm_desc {
|
||||
__le32 buf0;
|
||||
__le32 token;
|
||||
} __packed __aligned(4);
|
||||
|
||||
enum mtk_wed_bus_tye {
|
||||
MTK_WED_BUS_PCIE,
|
||||
MTK_WED_BUS_AXI,
|
||||
};
|
||||
|
||||
#define MTK_WED_RING_CONFIGURED BIT(0)
|
||||
struct mtk_wed_ring {
|
||||
struct mtk_wdma_desc *desc;
|
||||
dma_addr_t desc_phys;
|
||||
u32 desc_size;
|
||||
int size;
|
||||
u32 flags;
|
||||
|
||||
u32 reg_base;
|
||||
void __iomem *wpdma;
|
||||
};
|
||||
|
||||
struct mtk_wed_wo_rx_stats {
|
||||
__le16 wlan_idx;
|
||||
__le16 tid;
|
||||
__le32 rx_pkt_cnt;
|
||||
__le32 rx_byte_cnt;
|
||||
__le32 rx_err_cnt;
|
||||
__le32 rx_drop_cnt;
|
||||
};
|
||||
|
||||
struct mtk_wed_buf {
|
||||
void *p;
|
||||
dma_addr_t phy_addr;
|
||||
};
|
||||
|
||||
struct mtk_wed_device {
|
||||
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
|
||||
const struct mtk_wed_ops *ops;
|
||||
struct device *dev;
|
||||
struct mtk_wed_hw *hw;
|
||||
bool init_done, running;
|
||||
int wdma_idx;
|
||||
int irq;
|
||||
u8 version;
|
||||
|
||||
/* used by wlan driver */
|
||||
u32 rev_id;
|
||||
|
||||
struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
|
||||
struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES];
|
||||
struct mtk_wed_ring txfree_ring;
|
||||
struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
|
||||
struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
|
||||
struct mtk_wed_ring rx_rro_ring[MTK_WED_RX_QUEUES];
|
||||
struct mtk_wed_ring rx_page_ring[MTK_WED_RX_PAGE_QUEUES];
|
||||
struct mtk_wed_ring ind_cmd_ring;
|
||||
|
||||
struct {
|
||||
int size;
|
||||
struct mtk_wed_buf *pages;
|
||||
struct mtk_wdma_desc *desc;
|
||||
dma_addr_t desc_phys;
|
||||
} tx_buf_ring;
|
||||
|
||||
struct {
|
||||
int size;
|
||||
struct mtk_wed_bm_desc *desc;
|
||||
dma_addr_t desc_phys;
|
||||
} rx_buf_ring;
|
||||
|
||||
struct {
|
||||
struct mtk_wed_ring ring;
|
||||
dma_addr_t miod_phys;
|
||||
dma_addr_t fdbk_phys;
|
||||
} rro;
|
||||
|
||||
struct {
|
||||
int size;
|
||||
struct mtk_wed_buf *pages;
|
||||
struct mtk_wed_bm_desc *desc;
|
||||
dma_addr_t desc_phys;
|
||||
} hw_rro;
|
||||
|
||||
/* filled by driver: */
|
||||
struct {
|
||||
union {
|
||||
struct platform_device *platform_dev;
|
||||
struct pci_dev *pci_dev;
|
||||
};
|
||||
enum mtk_wed_bus_tye bus_type;
|
||||
void __iomem *base;
|
||||
u32 phy_base;
|
||||
u32 id;
|
||||
|
||||
u32 wpdma_phys;
|
||||
u32 wpdma_int;
|
||||
u32 wpdma_mask;
|
||||
u32 wpdma_tx;
|
||||
u32 wpdma_txfree;
|
||||
u32 wpdma_rx_glo;
|
||||
u32 wpdma_rx[MTK_WED_RX_QUEUES];
|
||||
u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
|
||||
u32 wpdma_rx_pg;
|
||||
|
||||
bool wcid_512;
|
||||
bool hw_rro;
|
||||
bool msi;
|
||||
bool hif2;
|
||||
|
||||
u16 token_start;
|
||||
unsigned int nbuf;
|
||||
unsigned int rx_nbuf;
|
||||
unsigned int rx_npkt;
|
||||
unsigned int rx_size;
|
||||
unsigned int amsdu_max_len;
|
||||
|
||||
u8 tx_tbit[MTK_WED_TX_QUEUES];
|
||||
u8 rx_tbit[MTK_WED_RX_QUEUES];
|
||||
u8 rro_rx_tbit[MTK_WED_RX_QUEUES];
|
||||
u8 rx_pg_tbit[MTK_WED_RX_PAGE_QUEUES];
|
||||
u8 txfree_tbit;
|
||||
u8 amsdu_max_subframes;
|
||||
|
||||
struct {
|
||||
u8 se_group_nums;
|
||||
u16 win_size;
|
||||
u16 particular_sid;
|
||||
u32 ack_sn_addr;
|
||||
dma_addr_t particular_se_phys;
|
||||
dma_addr_t addr_elem_phys[1024];
|
||||
} ind_cmd;
|
||||
|
||||
u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
|
||||
int (*offload_enable)(struct mtk_wed_device *wed);
|
||||
void (*offload_disable)(struct mtk_wed_device *wed);
|
||||
u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size);
|
||||
void (*release_rx_buf)(struct mtk_wed_device *wed);
|
||||
void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
|
||||
struct mtk_wed_wo_rx_stats *stats);
|
||||
int (*reset)(struct mtk_wed_device *wed);
|
||||
void (*reset_complete)(struct mtk_wed_device *wed);
|
||||
} wlan;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mtk_wed_ops {
|
||||
int (*attach)(struct mtk_wed_device *dev) __releases(RCU);
|
||||
int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
|
||||
void __iomem *regs, bool reset);
|
||||
int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
|
||||
void __iomem *regs, bool reset);
|
||||
int (*txfree_ring_setup)(struct mtk_wed_device *dev,
|
||||
void __iomem *regs);
|
||||
int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
|
||||
void *data, int len);
|
||||
void (*detach)(struct mtk_wed_device *dev);
|
||||
void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb,
|
||||
u32 reason, u32 hash);
|
||||
|
||||
void (*stop)(struct mtk_wed_device *dev);
|
||||
void (*start)(struct mtk_wed_device *dev, u32 irq_mask);
|
||||
void (*reset_dma)(struct mtk_wed_device *dev);
|
||||
|
||||
u32 (*reg_read)(struct mtk_wed_device *dev, u32 reg);
|
||||
void (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val);
|
||||
|
||||
u32 (*irq_get)(struct mtk_wed_device *dev, u32 mask);
|
||||
void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);
|
||||
int (*setup_tc)(struct mtk_wed_device *wed, struct net_device *dev,
|
||||
enum tc_setup_type type, void *type_data);
|
||||
void (*start_hw_rro)(struct mtk_wed_device *dev, u32 irq_mask,
|
||||
bool reset);
|
||||
void (*rro_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
|
||||
void __iomem *regs);
|
||||
void (*msdu_pg_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
|
||||
void __iomem *regs);
|
||||
int (*ind_rx_ring_setup)(struct mtk_wed_device *dev,
|
||||
void __iomem *regs);
|
||||
};
|
||||
|
||||
extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
|
||||
|
||||
static inline int
|
||||
mtk_wed_device_attach(struct mtk_wed_device *dev)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
|
||||
rcu_read_lock();
|
||||
dev->ops = rcu_dereference(mtk_soc_wed_ops);
|
||||
if (dev->ops)
|
||||
ret = dev->ops->attach(dev);
|
||||
else
|
||||
rcu_read_unlock();
|
||||
|
||||
if (ret)
|
||||
dev->ops = NULL;
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline bool mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
|
||||
{
|
||||
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
|
||||
if (dev->version == 3)
|
||||
return dev->wlan.hw_rro;
|
||||
|
||||
return dev->version != 1;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline bool mtk_wed_is_amsdu_supported(struct mtk_wed_device *dev)
|
||||
{
|
||||
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
|
||||
return dev->version == 3;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
|
||||
#define mtk_wed_device_active(_dev) !!(_dev)->ops
|
||||
#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
|
||||
#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)
|
||||
#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) \
|
||||
(_dev)->ops->tx_ring_setup(_dev, _ring, _regs, _reset)
|
||||
#define mtk_wed_device_txfree_ring_setup(_dev, _regs) \
|
||||
(_dev)->ops->txfree_ring_setup(_dev, _regs)
|
||||
#define mtk_wed_device_reg_read(_dev, _reg) \
|
||||
(_dev)->ops->reg_read(_dev, _reg)
|
||||
#define mtk_wed_device_reg_write(_dev, _reg, _val) \
|
||||
(_dev)->ops->reg_write(_dev, _reg, _val)
|
||||
#define mtk_wed_device_irq_get(_dev, _mask) \
|
||||
(_dev)->ops->irq_get(_dev, _mask)
|
||||
#define mtk_wed_device_irq_set_mask(_dev, _mask) \
|
||||
(_dev)->ops->irq_set_mask(_dev, _mask)
|
||||
#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
|
||||
(_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset)
|
||||
#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
|
||||
(_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
|
||||
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
|
||||
(_dev)->ops->msg_update(_dev, _id, _msg, _len)
|
||||
#define mtk_wed_device_stop(_dev) (_dev)->ops->stop(_dev)
|
||||
#define mtk_wed_device_dma_reset(_dev) (_dev)->ops->reset_dma(_dev)
|
||||
#define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) \
|
||||
(_dev)->ops->setup_tc(_dev, _netdev, _type, _type_data)
|
||||
#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) \
|
||||
(_dev)->ops->start_hw_rro(_dev, _mask, _reset)
|
||||
#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) \
|
||||
(_dev)->ops->rro_rx_ring_setup(_dev, _ring, _regs)
|
||||
#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) \
|
||||
(_dev)->ops->msdu_pg_rx_ring_setup(_dev, _ring, _regs)
|
||||
#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) \
|
||||
(_dev)->ops->ind_rx_ring_setup(_dev, _regs)
|
||||
|
||||
#else
|
||||
static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#define mtk_wed_device_detach(_dev) do {} while (0)
|
||||
#define mtk_wed_device_start(_dev, _mask) do {} while (0)
|
||||
#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
|
||||
#define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
|
||||
#define mtk_wed_device_reg_read(_dev, _reg) 0
|
||||
#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
|
||||
#define mtk_wed_device_irq_get(_dev, _mask) 0
|
||||
#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
|
||||
#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
|
||||
#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) do {} while (0)
|
||||
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
|
||||
#define mtk_wed_device_stop(_dev) do {} while (0)
|
||||
#define mtk_wed_device_dma_reset(_dev) do {} while (0)
|
||||
#define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) -EOPNOTSUPP
|
||||
#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) do {} while (0)
|
||||
#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) -ENODEV
|
||||
#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) -ENODEV
|
||||
#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) -ENODEV
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,65 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_MACH_CPUTYPE_H
|
||||
#define __ASM_MACH_CPUTYPE_H
|
||||
|
||||
#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
|
||||
#include <asm/cputype.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* CPU Stepping CPU_ID CHIP_ID
|
||||
*
|
||||
* PXA168 S0 0x56158400 0x0000C910
|
||||
* PXA168 A0 0x56158400 0x00A0A168
|
||||
* PXA910 Y1 0x56158400 0x00F2C920
|
||||
* PXA910 A0 0x56158400 0x00F2C910
|
||||
* PXA910 A1 0x56158400 0x00A0C910
|
||||
* PXA920 Y0 0x56158400 0x00F2C920
|
||||
* PXA920 A0 0x56158400 0x00A0C920
|
||||
* PXA920 A1 0x56158400 0x00A1C920
|
||||
* MMP2 Z0 0x560f5811 0x00F00410
|
||||
* MMP2 Z1 0x560f5811 0x00E00410
|
||||
* MMP2 A0 0x560f5811 0x00A0A610
|
||||
* MMP3 A0 0x562f5842 0x00A02128
|
||||
* MMP3 B0 0x562f5842 0x00B02128
|
||||
*/
|
||||
|
||||
extern unsigned int mmp_chip_id;
|
||||
|
||||
#if defined(CONFIG_MACH_MMP2_DT)
|
||||
static inline int cpu_is_mmp2(void)
|
||||
{
|
||||
return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
|
||||
(((mmp_chip_id & 0xfff) == 0x410) ||
|
||||
((mmp_chip_id & 0xfff) == 0x610));
|
||||
}
|
||||
#else
|
||||
#define cpu_is_mmp2() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MMP3_DT
|
||||
static inline int cpu_is_mmp3(void)
|
||||
{
|
||||
return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
|
||||
((mmp_chip_id & 0xffff) == 0x2128);
|
||||
}
|
||||
|
||||
static inline int cpu_is_mmp3_a0(void)
|
||||
{
|
||||
return (cpu_is_mmp3() &&
|
||||
((mmp_chip_id & 0x00ff0000) == 0x00a00000));
|
||||
}
|
||||
|
||||
static inline int cpu_is_mmp3_b0(void)
|
||||
{
|
||||
return (cpu_is_mmp3() &&
|
||||
((mmp_chip_id & 0x00ff0000) == 0x00b00000));
|
||||
}
|
||||
|
||||
#else
|
||||
#define cpu_is_mmp3() (0)
|
||||
#define cpu_is_mmp3_a0() (0)
|
||||
#define cpu_is_mmp3_b0() (0)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_CPUTYPE_H */
|
||||
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2010 NXP Semiconductors
|
||||
*/
|
||||
|
||||
#ifndef __SOC_LPC32XX_MISC_H
|
||||
#define __SOC_LPC32XX_MISC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_LPC32XX
|
||||
extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr);
|
||||
extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode);
|
||||
extern void lpc32xx_loopback_set(resource_size_t mapbase, int state);
|
||||
#else
|
||||
static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
|
||||
{
|
||||
*mapbase = NULL;
|
||||
*dmaaddr = 0;
|
||||
return 0;
|
||||
}
|
||||
static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
|
||||
{
|
||||
}
|
||||
static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_LPC32XX_MISC_H */
|
||||
@@ -0,0 +1,252 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Author: Nicolas Pitre
|
||||
* Created: Jun 15, 2001
|
||||
* Copyright: MontaVista Software Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_PXA_CPU_H
|
||||
#define __SOC_PXA_CPU_H
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
#include <asm/cputype.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* CPU Stepping CPU_ID JTAG_ID
|
||||
*
|
||||
* PXA210 B0 0x69052922 0x2926C013
|
||||
* PXA210 B1 0x69052923 0x3926C013
|
||||
* PXA210 B2 0x69052924 0x4926C013
|
||||
* PXA210 C0 0x69052D25 0x5926C013
|
||||
*
|
||||
* PXA250 A0 0x69052100 0x09264013
|
||||
* PXA250 A1 0x69052101 0x19264013
|
||||
* PXA250 B0 0x69052902 0x29264013
|
||||
* PXA250 B1 0x69052903 0x39264013
|
||||
* PXA250 B2 0x69052904 0x49264013
|
||||
* PXA250 C0 0x69052D05 0x59264013
|
||||
*
|
||||
* PXA255 A0 0x69052D06 0x69264013
|
||||
*
|
||||
* PXA26x A0 0x69052903 0x39264013
|
||||
* PXA26x B0 0x69052D05 0x59264013
|
||||
*
|
||||
* PXA27x A0 0x69054110 0x09265013
|
||||
* PXA27x A1 0x69054111 0x19265013
|
||||
* PXA27x B0 0x69054112 0x29265013
|
||||
* PXA27x B1 0x69054113 0x39265013
|
||||
* PXA27x C0 0x69054114 0x49265013
|
||||
* PXA27x C5 0x69054117 0x79265013
|
||||
*
|
||||
* PXA30x A0 0x69056880 0x0E648013
|
||||
* PXA30x A1 0x69056881 0x1E648013
|
||||
* PXA31x A0 0x69056890 0x0E649013
|
||||
* PXA31x A1 0x69056891 0x1E649013
|
||||
* PXA31x A2 0x69056892 0x2E649013
|
||||
* PXA32x B1 0x69056825 0x5E642013
|
||||
* PXA32x B2 0x69056826 0x6E642013
|
||||
*
|
||||
* PXA930 B0 0x69056835 0x5E643013
|
||||
* PXA930 B1 0x69056837 0x7E643013
|
||||
* PXA930 B2 0x69056838 0x8E643013
|
||||
*
|
||||
* PXA935 A0 0x56056931 0x1E653013
|
||||
* PXA935 B0 0x56056936 0x6E653013
|
||||
* PXA935 B1 0x56056938 0x8E653013
|
||||
*/
|
||||
#ifdef CONFIG_PXA25x
|
||||
#define __cpu_is_pxa210(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) & 0xf3f0; \
|
||||
_id == 0x2120; \
|
||||
})
|
||||
|
||||
#define __cpu_is_pxa250(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) & 0xf3ff; \
|
||||
_id <= 0x2105; \
|
||||
})
|
||||
|
||||
#define __cpu_is_pxa255(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) & 0xffff; \
|
||||
_id == 0x2d06; \
|
||||
})
|
||||
|
||||
#define __cpu_is_pxa25x(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) & 0xf300; \
|
||||
_id == 0x2100; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa210(id) (0)
|
||||
#define __cpu_is_pxa250(id) (0)
|
||||
#define __cpu_is_pxa255(id) (0)
|
||||
#define __cpu_is_pxa25x(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PXA27x
|
||||
#define __cpu_is_pxa27x(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x411; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa27x(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PXA300
|
||||
#define __cpu_is_pxa300(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x688; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa300(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PXA310
|
||||
#define __cpu_is_pxa310(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x689; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa310(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PXA320
|
||||
#define __cpu_is_pxa320(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x603 || _id == 0x682; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa320(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PXA930
|
||||
#define __cpu_is_pxa930(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x683; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa930(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PXA935
|
||||
#define __cpu_is_pxa935(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||
_id == 0x693; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa935(id) (0)
|
||||
#endif
|
||||
|
||||
#define cpu_is_pxa210() \
|
||||
({ \
|
||||
__cpu_is_pxa210(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa250() \
|
||||
({ \
|
||||
__cpu_is_pxa250(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa255() \
|
||||
({ \
|
||||
__cpu_is_pxa255(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa25x() \
|
||||
({ \
|
||||
__cpu_is_pxa25x(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa27x() \
|
||||
({ \
|
||||
__cpu_is_pxa27x(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa300() \
|
||||
({ \
|
||||
__cpu_is_pxa300(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa310() \
|
||||
({ \
|
||||
__cpu_is_pxa310(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa320() \
|
||||
({ \
|
||||
__cpu_is_pxa320(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa930() \
|
||||
({ \
|
||||
__cpu_is_pxa930(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa935() \
|
||||
({ \
|
||||
__cpu_is_pxa935(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* CPUID Core Generation Bit
|
||||
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
|
||||
*/
|
||||
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
|
||||
#define __cpu_is_pxa2xx(id) \
|
||||
({ \
|
||||
unsigned int _id = (id) >> 13 & 0x7; \
|
||||
_id <= 0x2; \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa2xx(id) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PXA3xx
|
||||
#define __cpu_is_pxa3xx(id) \
|
||||
({ \
|
||||
__cpu_is_pxa300(id) \
|
||||
|| __cpu_is_pxa310(id) \
|
||||
|| __cpu_is_pxa320(id) \
|
||||
|| __cpu_is_pxa93x(id); \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa3xx(id) (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
|
||||
#define __cpu_is_pxa93x(id) \
|
||||
({ \
|
||||
__cpu_is_pxa930(id) \
|
||||
|| __cpu_is_pxa935(id); \
|
||||
})
|
||||
#else
|
||||
#define __cpu_is_pxa93x(id) (0)
|
||||
#endif
|
||||
|
||||
#define cpu_is_pxa2xx() \
|
||||
({ \
|
||||
__cpu_is_pxa2xx(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa3xx() \
|
||||
({ \
|
||||
__cpu_is_pxa3xx(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#define cpu_is_pxa93x() \
|
||||
({ \
|
||||
__cpu_is_pxa93x(read_cpuid_id()); \
|
||||
})
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,470 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Common Multi-Function Pin Definitions
|
||||
*
|
||||
* Copyright (C) 2007 Marvell International Ltd.
|
||||
*
|
||||
* 2007-8-21: eric miao <eric.miao@marvell.com>
|
||||
* initial version
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PLAT_MFP_H
|
||||
#define __ASM_PLAT_MFP_H
|
||||
|
||||
#define mfp_to_gpio(m) ((m) % 256)
|
||||
|
||||
/* list of all the configurable MFP pins */
|
||||
enum {
|
||||
MFP_PIN_INVALID = -1,
|
||||
|
||||
MFP_PIN_GPIO0 = 0,
|
||||
MFP_PIN_GPIO1,
|
||||
MFP_PIN_GPIO2,
|
||||
MFP_PIN_GPIO3,
|
||||
MFP_PIN_GPIO4,
|
||||
MFP_PIN_GPIO5,
|
||||
MFP_PIN_GPIO6,
|
||||
MFP_PIN_GPIO7,
|
||||
MFP_PIN_GPIO8,
|
||||
MFP_PIN_GPIO9,
|
||||
MFP_PIN_GPIO10,
|
||||
MFP_PIN_GPIO11,
|
||||
MFP_PIN_GPIO12,
|
||||
MFP_PIN_GPIO13,
|
||||
MFP_PIN_GPIO14,
|
||||
MFP_PIN_GPIO15,
|
||||
MFP_PIN_GPIO16,
|
||||
MFP_PIN_GPIO17,
|
||||
MFP_PIN_GPIO18,
|
||||
MFP_PIN_GPIO19,
|
||||
MFP_PIN_GPIO20,
|
||||
MFP_PIN_GPIO21,
|
||||
MFP_PIN_GPIO22,
|
||||
MFP_PIN_GPIO23,
|
||||
MFP_PIN_GPIO24,
|
||||
MFP_PIN_GPIO25,
|
||||
MFP_PIN_GPIO26,
|
||||
MFP_PIN_GPIO27,
|
||||
MFP_PIN_GPIO28,
|
||||
MFP_PIN_GPIO29,
|
||||
MFP_PIN_GPIO30,
|
||||
MFP_PIN_GPIO31,
|
||||
MFP_PIN_GPIO32,
|
||||
MFP_PIN_GPIO33,
|
||||
MFP_PIN_GPIO34,
|
||||
MFP_PIN_GPIO35,
|
||||
MFP_PIN_GPIO36,
|
||||
MFP_PIN_GPIO37,
|
||||
MFP_PIN_GPIO38,
|
||||
MFP_PIN_GPIO39,
|
||||
MFP_PIN_GPIO40,
|
||||
MFP_PIN_GPIO41,
|
||||
MFP_PIN_GPIO42,
|
||||
MFP_PIN_GPIO43,
|
||||
MFP_PIN_GPIO44,
|
||||
MFP_PIN_GPIO45,
|
||||
MFP_PIN_GPIO46,
|
||||
MFP_PIN_GPIO47,
|
||||
MFP_PIN_GPIO48,
|
||||
MFP_PIN_GPIO49,
|
||||
MFP_PIN_GPIO50,
|
||||
MFP_PIN_GPIO51,
|
||||
MFP_PIN_GPIO52,
|
||||
MFP_PIN_GPIO53,
|
||||
MFP_PIN_GPIO54,
|
||||
MFP_PIN_GPIO55,
|
||||
MFP_PIN_GPIO56,
|
||||
MFP_PIN_GPIO57,
|
||||
MFP_PIN_GPIO58,
|
||||
MFP_PIN_GPIO59,
|
||||
MFP_PIN_GPIO60,
|
||||
MFP_PIN_GPIO61,
|
||||
MFP_PIN_GPIO62,
|
||||
MFP_PIN_GPIO63,
|
||||
MFP_PIN_GPIO64,
|
||||
MFP_PIN_GPIO65,
|
||||
MFP_PIN_GPIO66,
|
||||
MFP_PIN_GPIO67,
|
||||
MFP_PIN_GPIO68,
|
||||
MFP_PIN_GPIO69,
|
||||
MFP_PIN_GPIO70,
|
||||
MFP_PIN_GPIO71,
|
||||
MFP_PIN_GPIO72,
|
||||
MFP_PIN_GPIO73,
|
||||
MFP_PIN_GPIO74,
|
||||
MFP_PIN_GPIO75,
|
||||
MFP_PIN_GPIO76,
|
||||
MFP_PIN_GPIO77,
|
||||
MFP_PIN_GPIO78,
|
||||
MFP_PIN_GPIO79,
|
||||
MFP_PIN_GPIO80,
|
||||
MFP_PIN_GPIO81,
|
||||
MFP_PIN_GPIO82,
|
||||
MFP_PIN_GPIO83,
|
||||
MFP_PIN_GPIO84,
|
||||
MFP_PIN_GPIO85,
|
||||
MFP_PIN_GPIO86,
|
||||
MFP_PIN_GPIO87,
|
||||
MFP_PIN_GPIO88,
|
||||
MFP_PIN_GPIO89,
|
||||
MFP_PIN_GPIO90,
|
||||
MFP_PIN_GPIO91,
|
||||
MFP_PIN_GPIO92,
|
||||
MFP_PIN_GPIO93,
|
||||
MFP_PIN_GPIO94,
|
||||
MFP_PIN_GPIO95,
|
||||
MFP_PIN_GPIO96,
|
||||
MFP_PIN_GPIO97,
|
||||
MFP_PIN_GPIO98,
|
||||
MFP_PIN_GPIO99,
|
||||
MFP_PIN_GPIO100,
|
||||
MFP_PIN_GPIO101,
|
||||
MFP_PIN_GPIO102,
|
||||
MFP_PIN_GPIO103,
|
||||
MFP_PIN_GPIO104,
|
||||
MFP_PIN_GPIO105,
|
||||
MFP_PIN_GPIO106,
|
||||
MFP_PIN_GPIO107,
|
||||
MFP_PIN_GPIO108,
|
||||
MFP_PIN_GPIO109,
|
||||
MFP_PIN_GPIO110,
|
||||
MFP_PIN_GPIO111,
|
||||
MFP_PIN_GPIO112,
|
||||
MFP_PIN_GPIO113,
|
||||
MFP_PIN_GPIO114,
|
||||
MFP_PIN_GPIO115,
|
||||
MFP_PIN_GPIO116,
|
||||
MFP_PIN_GPIO117,
|
||||
MFP_PIN_GPIO118,
|
||||
MFP_PIN_GPIO119,
|
||||
MFP_PIN_GPIO120,
|
||||
MFP_PIN_GPIO121,
|
||||
MFP_PIN_GPIO122,
|
||||
MFP_PIN_GPIO123,
|
||||
MFP_PIN_GPIO124,
|
||||
MFP_PIN_GPIO125,
|
||||
MFP_PIN_GPIO126,
|
||||
MFP_PIN_GPIO127,
|
||||
|
||||
MFP_PIN_GPIO128,
|
||||
MFP_PIN_GPIO129,
|
||||
MFP_PIN_GPIO130,
|
||||
MFP_PIN_GPIO131,
|
||||
MFP_PIN_GPIO132,
|
||||
MFP_PIN_GPIO133,
|
||||
MFP_PIN_GPIO134,
|
||||
MFP_PIN_GPIO135,
|
||||
MFP_PIN_GPIO136,
|
||||
MFP_PIN_GPIO137,
|
||||
MFP_PIN_GPIO138,
|
||||
MFP_PIN_GPIO139,
|
||||
MFP_PIN_GPIO140,
|
||||
MFP_PIN_GPIO141,
|
||||
MFP_PIN_GPIO142,
|
||||
MFP_PIN_GPIO143,
|
||||
MFP_PIN_GPIO144,
|
||||
MFP_PIN_GPIO145,
|
||||
MFP_PIN_GPIO146,
|
||||
MFP_PIN_GPIO147,
|
||||
MFP_PIN_GPIO148,
|
||||
MFP_PIN_GPIO149,
|
||||
MFP_PIN_GPIO150,
|
||||
MFP_PIN_GPIO151,
|
||||
MFP_PIN_GPIO152,
|
||||
MFP_PIN_GPIO153,
|
||||
MFP_PIN_GPIO154,
|
||||
MFP_PIN_GPIO155,
|
||||
MFP_PIN_GPIO156,
|
||||
MFP_PIN_GPIO157,
|
||||
MFP_PIN_GPIO158,
|
||||
MFP_PIN_GPIO159,
|
||||
MFP_PIN_GPIO160,
|
||||
MFP_PIN_GPIO161,
|
||||
MFP_PIN_GPIO162,
|
||||
MFP_PIN_GPIO163,
|
||||
MFP_PIN_GPIO164,
|
||||
MFP_PIN_GPIO165,
|
||||
MFP_PIN_GPIO166,
|
||||
MFP_PIN_GPIO167,
|
||||
MFP_PIN_GPIO168,
|
||||
MFP_PIN_GPIO169,
|
||||
MFP_PIN_GPIO170,
|
||||
MFP_PIN_GPIO171,
|
||||
MFP_PIN_GPIO172,
|
||||
MFP_PIN_GPIO173,
|
||||
MFP_PIN_GPIO174,
|
||||
MFP_PIN_GPIO175,
|
||||
MFP_PIN_GPIO176,
|
||||
MFP_PIN_GPIO177,
|
||||
MFP_PIN_GPIO178,
|
||||
MFP_PIN_GPIO179,
|
||||
MFP_PIN_GPIO180,
|
||||
MFP_PIN_GPIO181,
|
||||
MFP_PIN_GPIO182,
|
||||
MFP_PIN_GPIO183,
|
||||
MFP_PIN_GPIO184,
|
||||
MFP_PIN_GPIO185,
|
||||
MFP_PIN_GPIO186,
|
||||
MFP_PIN_GPIO187,
|
||||
MFP_PIN_GPIO188,
|
||||
MFP_PIN_GPIO189,
|
||||
MFP_PIN_GPIO190,
|
||||
MFP_PIN_GPIO191,
|
||||
|
||||
MFP_PIN_GPIO255 = 255,
|
||||
|
||||
MFP_PIN_GPIO0_2,
|
||||
MFP_PIN_GPIO1_2,
|
||||
MFP_PIN_GPIO2_2,
|
||||
MFP_PIN_GPIO3_2,
|
||||
MFP_PIN_GPIO4_2,
|
||||
MFP_PIN_GPIO5_2,
|
||||
MFP_PIN_GPIO6_2,
|
||||
MFP_PIN_GPIO7_2,
|
||||
MFP_PIN_GPIO8_2,
|
||||
MFP_PIN_GPIO9_2,
|
||||
MFP_PIN_GPIO10_2,
|
||||
MFP_PIN_GPIO11_2,
|
||||
MFP_PIN_GPIO12_2,
|
||||
MFP_PIN_GPIO13_2,
|
||||
MFP_PIN_GPIO14_2,
|
||||
MFP_PIN_GPIO15_2,
|
||||
MFP_PIN_GPIO16_2,
|
||||
MFP_PIN_GPIO17_2,
|
||||
|
||||
MFP_PIN_ULPI_STP,
|
||||
MFP_PIN_ULPI_NXT,
|
||||
MFP_PIN_ULPI_DIR,
|
||||
|
||||
MFP_PIN_nXCVREN,
|
||||
MFP_PIN_DF_CLE_nOE,
|
||||
MFP_PIN_DF_nADV1_ALE,
|
||||
MFP_PIN_DF_SCLK_E,
|
||||
MFP_PIN_DF_SCLK_S,
|
||||
MFP_PIN_nBE0,
|
||||
MFP_PIN_nBE1,
|
||||
MFP_PIN_DF_nADV2_ALE,
|
||||
MFP_PIN_DF_INT_RnB,
|
||||
MFP_PIN_DF_nCS0,
|
||||
MFP_PIN_DF_nCS1,
|
||||
MFP_PIN_nLUA,
|
||||
MFP_PIN_nLLA,
|
||||
MFP_PIN_DF_nWE,
|
||||
MFP_PIN_DF_ALE_nWE,
|
||||
MFP_PIN_DF_nRE_nOE,
|
||||
MFP_PIN_DF_ADDR0,
|
||||
MFP_PIN_DF_ADDR1,
|
||||
MFP_PIN_DF_ADDR2,
|
||||
MFP_PIN_DF_ADDR3,
|
||||
MFP_PIN_DF_IO0,
|
||||
MFP_PIN_DF_IO1,
|
||||
MFP_PIN_DF_IO2,
|
||||
MFP_PIN_DF_IO3,
|
||||
MFP_PIN_DF_IO4,
|
||||
MFP_PIN_DF_IO5,
|
||||
MFP_PIN_DF_IO6,
|
||||
MFP_PIN_DF_IO7,
|
||||
MFP_PIN_DF_IO8,
|
||||
MFP_PIN_DF_IO9,
|
||||
MFP_PIN_DF_IO10,
|
||||
MFP_PIN_DF_IO11,
|
||||
MFP_PIN_DF_IO12,
|
||||
MFP_PIN_DF_IO13,
|
||||
MFP_PIN_DF_IO14,
|
||||
MFP_PIN_DF_IO15,
|
||||
MFP_PIN_DF_nCS0_SM_nCS2,
|
||||
MFP_PIN_DF_nCS1_SM_nCS3,
|
||||
MFP_PIN_SM_nCS0,
|
||||
MFP_PIN_SM_nCS1,
|
||||
MFP_PIN_DF_WEn,
|
||||
MFP_PIN_DF_REn,
|
||||
MFP_PIN_DF_CLE_SM_OEn,
|
||||
MFP_PIN_DF_ALE_SM_WEn,
|
||||
MFP_PIN_DF_RDY0,
|
||||
MFP_PIN_DF_RDY1,
|
||||
|
||||
MFP_PIN_SM_SCLK,
|
||||
MFP_PIN_SM_BE0,
|
||||
MFP_PIN_SM_BE1,
|
||||
MFP_PIN_SM_ADV,
|
||||
MFP_PIN_SM_ADVMUX,
|
||||
MFP_PIN_SM_RDY,
|
||||
|
||||
MFP_PIN_MMC1_DAT7,
|
||||
MFP_PIN_MMC1_DAT6,
|
||||
MFP_PIN_MMC1_DAT5,
|
||||
MFP_PIN_MMC1_DAT4,
|
||||
MFP_PIN_MMC1_DAT3,
|
||||
MFP_PIN_MMC1_DAT2,
|
||||
MFP_PIN_MMC1_DAT1,
|
||||
MFP_PIN_MMC1_DAT0,
|
||||
MFP_PIN_MMC1_CMD,
|
||||
MFP_PIN_MMC1_CLK,
|
||||
MFP_PIN_MMC1_CD,
|
||||
MFP_PIN_MMC1_WP,
|
||||
|
||||
/* additional pins on PXA930 */
|
||||
MFP_PIN_GSIM_UIO,
|
||||
MFP_PIN_GSIM_UCLK,
|
||||
MFP_PIN_GSIM_UDET,
|
||||
MFP_PIN_GSIM_nURST,
|
||||
MFP_PIN_PMIC_INT,
|
||||
MFP_PIN_RDY,
|
||||
|
||||
/* additional pins on MMP2 */
|
||||
MFP_PIN_TWSI1_SCL,
|
||||
MFP_PIN_TWSI1_SDA,
|
||||
MFP_PIN_TWSI4_SCL,
|
||||
MFP_PIN_TWSI4_SDA,
|
||||
MFP_PIN_CLK_REQ,
|
||||
|
||||
MFP_PIN_MAX,
|
||||
};
|
||||
|
||||
/*
|
||||
* a possible MFP configuration is represented by a 32-bit integer
|
||||
*
|
||||
* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
|
||||
* bit 10..12 - Alternate Function Selection
|
||||
* bit 13..15 - Drive Strength
|
||||
* bit 16..18 - Low Power Mode State
|
||||
* bit 19..20 - Low Power Mode Edge Detection
|
||||
* bit 21..22 - Run Mode Pull State
|
||||
*
|
||||
* to facilitate the definition, the following macros are provided
|
||||
*
|
||||
* MFP_CFG_DEFAULT - default MFP configuration value, with
|
||||
* alternate function = 0,
|
||||
* drive strength = fast 3mA (MFP_DS03X)
|
||||
* low power mode = default
|
||||
* edge detection = none
|
||||
*
|
||||
* MFP_CFG - default MFPR value with alternate function
|
||||
* MFP_CFG_DRV - default MFPR value with alternate function and
|
||||
* pin drive strength
|
||||
* MFP_CFG_LPM - default MFPR value with alternate function and
|
||||
* low power mode
|
||||
* MFP_CFG_X - default MFPR value with alternate function,
|
||||
* pin drive strength and low power mode
|
||||
*/
|
||||
|
||||
typedef unsigned long mfp_cfg_t;
|
||||
|
||||
#define MFP_PIN(x) ((x) & 0x3ff)
|
||||
|
||||
#define MFP_AF0 (0x0 << 10)
|
||||
#define MFP_AF1 (0x1 << 10)
|
||||
#define MFP_AF2 (0x2 << 10)
|
||||
#define MFP_AF3 (0x3 << 10)
|
||||
#define MFP_AF4 (0x4 << 10)
|
||||
#define MFP_AF5 (0x5 << 10)
|
||||
#define MFP_AF6 (0x6 << 10)
|
||||
#define MFP_AF7 (0x7 << 10)
|
||||
#define MFP_AF_MASK (0x7 << 10)
|
||||
#define MFP_AF(x) (((x) >> 10) & 0x7)
|
||||
|
||||
#define MFP_DS01X (0x0 << 13)
|
||||
#define MFP_DS02X (0x1 << 13)
|
||||
#define MFP_DS03X (0x2 << 13)
|
||||
#define MFP_DS04X (0x3 << 13)
|
||||
#define MFP_DS06X (0x4 << 13)
|
||||
#define MFP_DS08X (0x5 << 13)
|
||||
#define MFP_DS10X (0x6 << 13)
|
||||
#define MFP_DS13X (0x7 << 13)
|
||||
#define MFP_DS_MASK (0x7 << 13)
|
||||
#define MFP_DS(x) (((x) >> 13) & 0x7)
|
||||
|
||||
#define MFP_LPM_DEFAULT (0x0 << 16)
|
||||
#define MFP_LPM_DRIVE_LOW (0x1 << 16)
|
||||
#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
|
||||
#define MFP_LPM_PULL_LOW (0x3 << 16)
|
||||
#define MFP_LPM_PULL_HIGH (0x4 << 16)
|
||||
#define MFP_LPM_FLOAT (0x5 << 16)
|
||||
#define MFP_LPM_INPUT (0x6 << 16)
|
||||
#define MFP_LPM_STATE_MASK (0x7 << 16)
|
||||
#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
|
||||
|
||||
#define MFP_LPM_EDGE_NONE (0x0 << 19)
|
||||
#define MFP_LPM_EDGE_RISE (0x1 << 19)
|
||||
#define MFP_LPM_EDGE_FALL (0x2 << 19)
|
||||
#define MFP_LPM_EDGE_BOTH (0x3 << 19)
|
||||
#define MFP_LPM_EDGE_MASK (0x3 << 19)
|
||||
#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
|
||||
|
||||
#define MFP_PULL_NONE (0x0 << 21)
|
||||
#define MFP_PULL_LOW (0x1 << 21)
|
||||
#define MFP_PULL_HIGH (0x2 << 21)
|
||||
#define MFP_PULL_BOTH (0x3 << 21)
|
||||
#define MFP_PULL_FLOAT (0x4 << 21)
|
||||
#define MFP_PULL_MASK (0x7 << 21)
|
||||
#define MFP_PULL(x) (((x) >> 21) & 0x7)
|
||||
|
||||
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
|
||||
MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
|
||||
|
||||
#define MFP_CFG(pin, af) \
|
||||
((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
|
||||
(MFP_PIN(MFP_PIN_##pin) | MFP_##af))
|
||||
|
||||
#define MFP_CFG_DRV(pin, af, drv) \
|
||||
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
|
||||
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
|
||||
|
||||
#define MFP_CFG_LPM(pin, af, lpm) \
|
||||
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
|
||||
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
|
||||
|
||||
#define MFP_CFG_X(pin, af, drv, lpm) \
|
||||
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
|
||||
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
|
||||
|
||||
#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
|
||||
/*
|
||||
* each MFP pin will have a MFPR register, since the offset of the
|
||||
* register varies between processors, the processor specific code
|
||||
* should initialize the pin offsets by mfp_init()
|
||||
*
|
||||
* mfp_init_base() - accepts a virtual base for all MFPR registers and
|
||||
* initialize the MFP table to a default state
|
||||
*
|
||||
* mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
|
||||
* represents a range of MFP pins from "start" to "end", with the offset
|
||||
* beginning at "offset", to define a single pin, let "end" = -1.
|
||||
*
|
||||
* use
|
||||
*
|
||||
* MFP_ADDR_X() to define a range of pins
|
||||
* MFP_ADDR() to define a single pin
|
||||
* MFP_ADDR_END to signal the end of pin offset definitions
|
||||
*/
|
||||
struct mfp_addr_map {
|
||||
unsigned int start;
|
||||
unsigned int end;
|
||||
unsigned long offset;
|
||||
};
|
||||
|
||||
#define MFP_ADDR_X(start, end, offset) \
|
||||
{ MFP_PIN_##start, MFP_PIN_##end, offset }
|
||||
|
||||
#define MFP_ADDR(pin, offset) \
|
||||
{ MFP_PIN_##pin, -1, offset }
|
||||
|
||||
#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
|
||||
|
||||
void mfp_init_base(void __iomem *mfpr_base);
|
||||
void mfp_init_addr(struct mfp_addr_map *map);
|
||||
|
||||
/*
|
||||
* mfp_{read, write}() - for direct read/write access to the MFPR register
|
||||
* mfp_config() - for configuring a group of MFPR registers
|
||||
* mfp_config_lpm() - configuring all low power MFPR registers for suspend
|
||||
* mfp_config_run() - configuring all run time MFPR registers after resume
|
||||
*/
|
||||
unsigned long mfp_read(int mfp);
|
||||
void mfp_write(int mfp, unsigned long mfpr_val);
|
||||
void mfp_config(unsigned long *mfp_cfgs, int num);
|
||||
void mfp_config_run(void);
|
||||
void mfp_config_lpm(void);
|
||||
#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
|
||||
|
||||
#endif /* __ASM_PLAT_MFP_H */
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef __PXA_REGS_H
|
||||
#define __PXA_REGS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
void pxa_smemc_set_pcmcia_timing(int sock, u32 mcmem, u32 mcatt, u32 mcio);
|
||||
void pxa_smemc_set_pcmcia_socket(int nr);
|
||||
int pxa2xx_smemc_get_sdram_rows(void);
|
||||
unsigned int pxa3xx_smemc_get_memclkdiv(void);
|
||||
void __iomem *pxa_smemc_get_mdrefr(void);
|
||||
|
||||
/*
|
||||
* Once fully converted to the clock framework, all these functions should be
|
||||
* removed, and replaced with a clk_get(NULL, "core").
|
||||
*/
|
||||
#ifdef CONFIG_PXA25x
|
||||
extern unsigned pxa25x_get_clk_frequency_khz(int);
|
||||
#else
|
||||
#define pxa25x_get_clk_frequency_khz(x) (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PXA27x
|
||||
extern unsigned pxa27x_get_clk_frequency_khz(int);
|
||||
#else
|
||||
#define pxa27x_get_clk_frequency_khz(x) (0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,197 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef __QCOM_APR_H_
|
||||
#define __QCOM_APR_H_
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <dt-bindings/soc/qcom,apr.h>
|
||||
#include <dt-bindings/soc/qcom,gpr.h>
|
||||
|
||||
extern const struct bus_type aprbus;
|
||||
|
||||
#define APR_HDR_LEN(hdr_len) ((hdr_len)/4)
|
||||
|
||||
/*
|
||||
* HEADER field
|
||||
* version:0:3
|
||||
* header_size : 4:7
|
||||
* message_type : 8:9
|
||||
* reserved: 10:15
|
||||
*/
|
||||
#define APR_HDR_FIELD(msg_type, hdr_len, ver)\
|
||||
(((msg_type & 0x3) << 8) | ((hdr_len & 0xF) << 4) | (ver & 0xF))
|
||||
|
||||
#define APR_HDR_SIZE sizeof(struct apr_hdr)
|
||||
#define APR_SEQ_CMD_HDR_FIELD APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, \
|
||||
APR_HDR_LEN(APR_HDR_SIZE), \
|
||||
APR_PKT_VER)
|
||||
/* Version */
|
||||
#define APR_PKT_VER 0x0
|
||||
|
||||
/* Command and Response Types */
|
||||
#define APR_MSG_TYPE_EVENT 0x0
|
||||
#define APR_MSG_TYPE_CMD_RSP 0x1
|
||||
#define APR_MSG_TYPE_SEQ_CMD 0x2
|
||||
#define APR_MSG_TYPE_NSEQ_CMD 0x3
|
||||
#define APR_MSG_TYPE_MAX 0x04
|
||||
|
||||
/* APR Basic Response Message */
|
||||
#define APR_BASIC_RSP_RESULT 0x000110E8
|
||||
#define APR_RSP_ACCEPTED 0x000100BE
|
||||
|
||||
struct aprv2_ibasic_rsp_result_t {
|
||||
uint32_t opcode;
|
||||
uint32_t status;
|
||||
};
|
||||
|
||||
/* hdr field Ver [0:3], Size [4:7], Message type [8:10] */
|
||||
#define APR_HDR_FIELD_VER(h) (h & 0x000F)
|
||||
#define APR_HDR_FIELD_SIZE(h) ((h & 0x00F0) >> 4)
|
||||
#define APR_HDR_FIELD_SIZE_BYTES(h) (((h & 0x00F0) >> 4) * 4)
|
||||
#define APR_HDR_FIELD_MT(h) ((h & 0x0300) >> 8)
|
||||
|
||||
struct apr_hdr {
|
||||
uint16_t hdr_field;
|
||||
uint16_t pkt_size;
|
||||
uint8_t src_svc;
|
||||
uint8_t src_domain;
|
||||
uint16_t src_port;
|
||||
uint8_t dest_svc;
|
||||
uint8_t dest_domain;
|
||||
uint16_t dest_port;
|
||||
uint32_t token;
|
||||
uint32_t opcode;
|
||||
} __packed;
|
||||
|
||||
struct apr_pkt {
|
||||
struct apr_hdr hdr;
|
||||
uint8_t payload[];
|
||||
};
|
||||
|
||||
struct apr_resp_pkt {
|
||||
struct apr_hdr hdr;
|
||||
void *payload;
|
||||
int payload_size;
|
||||
};
|
||||
|
||||
struct gpr_hdr {
|
||||
uint32_t version:4;
|
||||
uint32_t hdr_size:4;
|
||||
uint32_t pkt_size:24;
|
||||
uint32_t dest_domain:8;
|
||||
uint32_t src_domain:8;
|
||||
uint32_t reserved:16;
|
||||
uint32_t src_port;
|
||||
uint32_t dest_port;
|
||||
uint32_t token;
|
||||
uint32_t opcode;
|
||||
} __packed;
|
||||
|
||||
struct gpr_pkt {
|
||||
struct gpr_hdr hdr;
|
||||
uint32_t payload[];
|
||||
};
|
||||
|
||||
struct gpr_resp_pkt {
|
||||
struct gpr_hdr hdr;
|
||||
void *payload;
|
||||
int payload_size;
|
||||
};
|
||||
|
||||
#define GPR_HDR_SIZE sizeof(struct gpr_hdr)
|
||||
#define GPR_PKT_VER 0x0
|
||||
#define GPR_PKT_HEADER_WORD_SIZE ((sizeof(struct gpr_pkt) + 3) >> 2)
|
||||
#define GPR_PKT_HEADER_BYTE_SIZE (GPR_PKT_HEADER_WORD_SIZE << 2)
|
||||
|
||||
#define GPR_BASIC_RSP_RESULT 0x02001005
|
||||
|
||||
struct gpr_ibasic_rsp_result_t {
|
||||
uint32_t opcode;
|
||||
uint32_t status;
|
||||
};
|
||||
|
||||
#define GPR_BASIC_EVT_ACCEPTED 0x02001006
|
||||
|
||||
struct gpr_ibasic_rsp_accepted_t {
|
||||
uint32_t opcode;
|
||||
};
|
||||
|
||||
/* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */
|
||||
#define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF)
|
||||
#define APR_SVC_MINOR_VERSION(v) (v & 0xFF)
|
||||
|
||||
typedef int (*gpr_port_cb) (const struct gpr_resp_pkt *d, void *priv, int op);
|
||||
struct packet_router;
|
||||
struct pkt_router_svc {
|
||||
struct device *dev;
|
||||
gpr_port_cb callback;
|
||||
struct packet_router *pr;
|
||||
spinlock_t lock;
|
||||
int id;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
typedef struct pkt_router_svc gpr_port_t;
|
||||
|
||||
struct apr_device {
|
||||
struct device dev;
|
||||
uint16_t svc_id;
|
||||
uint16_t domain_id;
|
||||
uint32_t version;
|
||||
char name[APR_NAME_SIZE];
|
||||
const char *service_path;
|
||||
struct pkt_router_svc svc;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
typedef struct apr_device gpr_device_t;
|
||||
|
||||
#define to_apr_device(d) container_of(d, struct apr_device, dev)
|
||||
#define svc_to_apr_device(d) container_of(d, struct apr_device, svc)
|
||||
|
||||
struct apr_driver {
|
||||
int (*probe)(struct apr_device *sl);
|
||||
void (*remove)(struct apr_device *sl);
|
||||
int (*callback)(struct apr_device *a,
|
||||
const struct apr_resp_pkt *d);
|
||||
gpr_port_cb gpr_callback;
|
||||
struct device_driver driver;
|
||||
const struct apr_device_id *id_table;
|
||||
};
|
||||
|
||||
typedef struct apr_driver gpr_driver_t;
|
||||
#define to_apr_driver(d) container_of_const(d, struct apr_driver, driver)
|
||||
|
||||
/*
|
||||
* use a macro to avoid include chaining to get THIS_MODULE
|
||||
*/
|
||||
#define apr_driver_register(drv) __apr_driver_register(drv, THIS_MODULE)
|
||||
|
||||
int __apr_driver_register(struct apr_driver *drv, struct module *owner);
|
||||
void apr_driver_unregister(struct apr_driver *drv);
|
||||
|
||||
/**
|
||||
* module_apr_driver() - Helper macro for registering a aprbus driver
|
||||
* @__apr_driver: apr_driver struct
|
||||
*
|
||||
* Helper macro for aprbus drivers which do not do anything special in
|
||||
* module init/exit. This eliminates a lot of boilerplate. Each module
|
||||
* may only use this macro once, and calling it replaces module_init()
|
||||
* and module_exit()
|
||||
*/
|
||||
#define module_apr_driver(__apr_driver) \
|
||||
module_driver(__apr_driver, apr_driver_register, \
|
||||
apr_driver_unregister)
|
||||
#define module_gpr_driver(__gpr_driver) module_apr_driver(__gpr_driver)
|
||||
|
||||
int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt);
|
||||
|
||||
gpr_port_t *gpr_alloc_port(gpr_device_t *gdev, struct device *dev,
|
||||
gpr_port_cb cb, void *priv);
|
||||
void gpr_free_port(gpr_port_t *port);
|
||||
int gpr_send_port_pkt(gpr_port_t *port, const struct gpr_pkt *pkt);
|
||||
int gpr_send_pkt(gpr_device_t *gdev, const struct gpr_pkt *pkt);
|
||||
|
||||
#endif /* __QCOM_APR_H_ */
|
||||
@@ -0,0 +1,539 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_QCOM_GENI_SE
|
||||
#define _LINUX_QCOM_GENI_SE
|
||||
|
||||
#include <linux/interconnect.h>
|
||||
|
||||
/**
|
||||
* enum geni_se_xfer_mode: Transfer modes supported by Serial Engines
|
||||
*
|
||||
* @GENI_SE_INVALID: Invalid mode
|
||||
* @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
|
||||
* by programmed IO method
|
||||
* @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred
|
||||
* with SE by DMAengine internal to SE
|
||||
* @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine
|
||||
* configured by a firmware residing on a GSI engine. This DMA name is
|
||||
* interchangeably used as GSI or GPI which seem to imply the same DMAengine
|
||||
*/
|
||||
|
||||
enum geni_se_xfer_mode {
|
||||
GENI_SE_INVALID,
|
||||
GENI_SE_FIFO,
|
||||
GENI_SE_DMA,
|
||||
GENI_GPI_DMA,
|
||||
};
|
||||
|
||||
/* Protocols supported by GENI Serial Engines */
|
||||
enum geni_se_protocol_type {
|
||||
GENI_SE_NONE,
|
||||
GENI_SE_SPI,
|
||||
GENI_SE_UART,
|
||||
GENI_SE_I2C,
|
||||
GENI_SE_I3C,
|
||||
GENI_SE_SPI_SLAVE,
|
||||
GENI_SE_INVALID_PROTO = 255,
|
||||
};
|
||||
|
||||
struct geni_wrapper;
|
||||
struct clk;
|
||||
|
||||
enum geni_icc_path_index {
|
||||
GENI_TO_CORE,
|
||||
CPU_TO_GENI,
|
||||
GENI_TO_DDR
|
||||
};
|
||||
|
||||
struct geni_icc_path {
|
||||
struct icc_path *path;
|
||||
unsigned int avg_bw;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct geni_se - GENI Serial Engine
|
||||
* @base: Base Address of the Serial Engine's register block
|
||||
* @dev: Pointer to the Serial Engine device
|
||||
* @wrapper: Pointer to the parent QUP Wrapper core
|
||||
* @clk: Handle to the core serial engine clock
|
||||
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
|
||||
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
|
||||
* @icc_paths: Array of ICC paths for SE
|
||||
*/
|
||||
struct geni_se {
|
||||
void __iomem *base;
|
||||
struct device *dev;
|
||||
struct geni_wrapper *wrapper;
|
||||
struct clk *clk;
|
||||
unsigned int num_clk_levels;
|
||||
unsigned long *clk_perf_tbl;
|
||||
struct geni_icc_path icc_paths[3];
|
||||
};
|
||||
|
||||
/* Common SE registers */
|
||||
#define GENI_FORCE_DEFAULT_REG 0x20
|
||||
#define GENI_OUTPUT_CTRL 0x24
|
||||
#define SE_GENI_STATUS 0x40
|
||||
#define GENI_SER_M_CLK_CFG 0x48
|
||||
#define GENI_SER_S_CLK_CFG 0x4c
|
||||
#define GENI_IF_DISABLE_RO 0x64
|
||||
#define GENI_FW_REVISION_RO 0x68
|
||||
#define SE_GENI_CLK_SEL 0x7c
|
||||
#define SE_GENI_CFG_SEQ_START 0x84
|
||||
#define SE_GENI_DMA_MODE_EN 0x258
|
||||
#define SE_GENI_M_CMD0 0x600
|
||||
#define SE_GENI_M_CMD_CTRL_REG 0x604
|
||||
#define SE_GENI_M_IRQ_STATUS 0x610
|
||||
#define SE_GENI_M_IRQ_EN 0x614
|
||||
#define SE_GENI_M_IRQ_CLEAR 0x618
|
||||
#define SE_GENI_M_IRQ_EN_SET 0x61c
|
||||
#define SE_GENI_M_IRQ_EN_CLEAR 0x620
|
||||
#define SE_GENI_S_CMD0 0x630
|
||||
#define SE_GENI_S_CMD_CTRL_REG 0x634
|
||||
#define SE_GENI_S_IRQ_STATUS 0x640
|
||||
#define SE_GENI_S_IRQ_EN 0x644
|
||||
#define SE_GENI_S_IRQ_CLEAR 0x648
|
||||
#define SE_GENI_S_IRQ_EN_SET 0x64c
|
||||
#define SE_GENI_S_IRQ_EN_CLEAR 0x650
|
||||
#define SE_GENI_TX_FIFOn 0x700
|
||||
#define SE_GENI_RX_FIFOn 0x780
|
||||
#define SE_GENI_TX_FIFO_STATUS 0x800
|
||||
#define SE_GENI_RX_FIFO_STATUS 0x804
|
||||
#define SE_GENI_TX_WATERMARK_REG 0x80c
|
||||
#define SE_GENI_RX_WATERMARK_REG 0x810
|
||||
#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
|
||||
#define SE_GENI_IOS 0x908
|
||||
#define SE_GENI_M_GP_LENGTH 0x910
|
||||
#define SE_GENI_S_GP_LENGTH 0x914
|
||||
#define SE_DMA_TX_IRQ_STAT 0xc40
|
||||
#define SE_DMA_TX_IRQ_CLR 0xc44
|
||||
#define SE_DMA_TX_FSM_RST 0xc58
|
||||
#define SE_DMA_RX_IRQ_STAT 0xd40
|
||||
#define SE_DMA_RX_IRQ_CLR 0xd44
|
||||
#define SE_DMA_RX_LEN_IN 0xd54
|
||||
#define SE_DMA_RX_FSM_RST 0xd58
|
||||
#define SE_HW_PARAM_0 0xe24
|
||||
#define SE_HW_PARAM_1 0xe28
|
||||
|
||||
/* GENI_FORCE_DEFAULT_REG fields */
|
||||
#define FORCE_DEFAULT BIT(0)
|
||||
|
||||
/* GENI_OUTPUT_CTRL fields */
|
||||
#define GENI_IO_MUX_0_EN BIT(0)
|
||||
|
||||
/* GENI_STATUS fields */
|
||||
#define M_GENI_CMD_ACTIVE BIT(0)
|
||||
#define S_GENI_CMD_ACTIVE BIT(12)
|
||||
|
||||
/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
|
||||
#define SER_CLK_EN BIT(0)
|
||||
#define CLK_DIV_MSK GENMASK(15, 4)
|
||||
#define CLK_DIV_SHFT 4
|
||||
|
||||
/* GENI_IF_DISABLE_RO fields */
|
||||
#define FIFO_IF_DISABLE (BIT(0))
|
||||
|
||||
/* GENI_FW_REVISION_RO fields */
|
||||
#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
|
||||
#define FW_REV_PROTOCOL_SHFT 8
|
||||
|
||||
/* GENI_CLK_SEL fields */
|
||||
#define CLK_SEL_MSK GENMASK(2, 0)
|
||||
|
||||
/* SE_GENI_CFG_SEQ_START fields */
|
||||
#define START_TRIGGER BIT(0)
|
||||
|
||||
/* SE_GENI_DMA_MODE_EN */
|
||||
#define GENI_DMA_MODE_EN BIT(0)
|
||||
|
||||
/* GENI_M_CMD0 fields */
|
||||
#define M_OPCODE_MSK GENMASK(31, 27)
|
||||
#define M_OPCODE_SHFT 27
|
||||
#define M_PARAMS_MSK GENMASK(26, 0)
|
||||
|
||||
/* GENI_M_CMD_CTRL_REG */
|
||||
#define M_GENI_CMD_CANCEL BIT(2)
|
||||
#define M_GENI_CMD_ABORT BIT(1)
|
||||
#define M_GENI_DISABLE BIT(0)
|
||||
|
||||
/* GENI_S_CMD0 fields */
|
||||
#define S_OPCODE_MSK GENMASK(31, 27)
|
||||
#define S_OPCODE_SHFT 27
|
||||
#define S_PARAMS_MSK GENMASK(26, 0)
|
||||
|
||||
/* GENI_S_CMD_CTRL_REG */
|
||||
#define S_GENI_CMD_CANCEL BIT(2)
|
||||
#define S_GENI_CMD_ABORT BIT(1)
|
||||
#define S_GENI_DISABLE BIT(0)
|
||||
|
||||
/* GENI_M_IRQ_EN fields */
|
||||
#define M_CMD_DONE_EN BIT(0)
|
||||
#define M_CMD_OVERRUN_EN BIT(1)
|
||||
#define M_ILLEGAL_CMD_EN BIT(2)
|
||||
#define M_CMD_FAILURE_EN BIT(3)
|
||||
#define M_CMD_CANCEL_EN BIT(4)
|
||||
#define M_CMD_ABORT_EN BIT(5)
|
||||
#define M_TIMESTAMP_EN BIT(6)
|
||||
#define M_RX_IRQ_EN BIT(7)
|
||||
#define M_GP_SYNC_IRQ_0_EN BIT(8)
|
||||
#define M_GP_IRQ_0_EN BIT(9)
|
||||
#define M_GP_IRQ_1_EN BIT(10)
|
||||
#define M_GP_IRQ_2_EN BIT(11)
|
||||
#define M_GP_IRQ_3_EN BIT(12)
|
||||
#define M_GP_IRQ_4_EN BIT(13)
|
||||
#define M_GP_IRQ_5_EN BIT(14)
|
||||
#define M_TX_FIFO_NOT_EMPTY_EN BIT(21)
|
||||
#define M_IO_DATA_DEASSERT_EN BIT(22)
|
||||
#define M_IO_DATA_ASSERT_EN BIT(23)
|
||||
#define M_RX_FIFO_RD_ERR_EN BIT(24)
|
||||
#define M_RX_FIFO_WR_ERR_EN BIT(25)
|
||||
#define M_RX_FIFO_WATERMARK_EN BIT(26)
|
||||
#define M_RX_FIFO_LAST_EN BIT(27)
|
||||
#define M_TX_FIFO_RD_ERR_EN BIT(28)
|
||||
#define M_TX_FIFO_WR_ERR_EN BIT(29)
|
||||
#define M_TX_FIFO_WATERMARK_EN BIT(30)
|
||||
#define M_SEC_IRQ_EN BIT(31)
|
||||
#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
|
||||
M_IO_DATA_DEASSERT_EN | \
|
||||
M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
|
||||
M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
|
||||
M_TX_FIFO_WR_ERR_EN)
|
||||
|
||||
/* GENI_S_IRQ_EN fields */
|
||||
#define S_CMD_DONE_EN BIT(0)
|
||||
#define S_CMD_OVERRUN_EN BIT(1)
|
||||
#define S_ILLEGAL_CMD_EN BIT(2)
|
||||
#define S_CMD_FAILURE_EN BIT(3)
|
||||
#define S_CMD_CANCEL_EN BIT(4)
|
||||
#define S_CMD_ABORT_EN BIT(5)
|
||||
#define S_GP_SYNC_IRQ_0_EN BIT(8)
|
||||
#define S_GP_IRQ_0_EN BIT(9)
|
||||
#define S_GP_IRQ_1_EN BIT(10)
|
||||
#define S_GP_IRQ_2_EN BIT(11)
|
||||
#define S_GP_IRQ_3_EN BIT(12)
|
||||
#define S_GP_IRQ_4_EN BIT(13)
|
||||
#define S_GP_IRQ_5_EN BIT(14)
|
||||
#define S_IO_DATA_DEASSERT_EN BIT(22)
|
||||
#define S_IO_DATA_ASSERT_EN BIT(23)
|
||||
#define S_RX_FIFO_RD_ERR_EN BIT(24)
|
||||
#define S_RX_FIFO_WR_ERR_EN BIT(25)
|
||||
#define S_RX_FIFO_WATERMARK_EN BIT(26)
|
||||
#define S_RX_FIFO_LAST_EN BIT(27)
|
||||
#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
|
||||
S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
|
||||
|
||||
/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
|
||||
#define WATERMARK_MSK GENMASK(5, 0)
|
||||
|
||||
/* GENI_TX_FIFO_STATUS fields */
|
||||
#define TX_FIFO_WC GENMASK(27, 0)
|
||||
|
||||
/* GENI_RX_FIFO_STATUS fields */
|
||||
#define RX_LAST BIT(31)
|
||||
#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
|
||||
#define RX_LAST_BYTE_VALID_SHFT 28
|
||||
#define RX_FIFO_WC_MSK GENMASK(24, 0)
|
||||
|
||||
/* SE_GENI_IOS fields */
|
||||
#define IO2_DATA_IN BIT(1)
|
||||
#define RX_DATA_IN BIT(0)
|
||||
|
||||
/* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */
|
||||
#define GP_LENGTH GENMASK(31, 0)
|
||||
|
||||
/* SE_DMA_TX_IRQ_STAT Register fields */
|
||||
#define TX_DMA_DONE BIT(0)
|
||||
#define TX_EOT BIT(1)
|
||||
#define TX_SBE BIT(2)
|
||||
#define TX_RESET_DONE BIT(3)
|
||||
|
||||
/* SE_DMA_RX_IRQ_STAT Register fields */
|
||||
#define RX_DMA_DONE BIT(0)
|
||||
#define RX_EOT BIT(1)
|
||||
#define RX_SBE BIT(2)
|
||||
#define RX_RESET_DONE BIT(3)
|
||||
#define RX_FLUSH_DONE BIT(4)
|
||||
#define RX_DMA_PARITY_ERR BIT(5)
|
||||
#define RX_DMA_BREAK GENMASK(8, 7)
|
||||
#define RX_GENI_GP_IRQ GENMASK(10, 5)
|
||||
#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
|
||||
#define RX_GENI_CANCEL_IRQ BIT(14)
|
||||
|
||||
/* SE_HW_PARAM_0 fields */
|
||||
#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
|
||||
#define TX_FIFO_WIDTH_SHFT 24
|
||||
/*
|
||||
* For QUP HW Version >= 3.10 Tx fifo depth support is increased
|
||||
* to 256bytes and corresponding bits are 16 to 23
|
||||
*/
|
||||
#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
|
||||
#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
|
||||
#define TX_FIFO_DEPTH_SHFT 16
|
||||
|
||||
/* SE_HW_PARAM_1 fields */
|
||||
#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
|
||||
#define RX_FIFO_WIDTH_SHFT 24
|
||||
/*
|
||||
* For QUP HW Version >= 3.10 Rx fifo depth support is increased
|
||||
* to 256bytes and corresponding bits are 16 to 23
|
||||
*/
|
||||
#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)
|
||||
#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
|
||||
#define RX_FIFO_DEPTH_SHFT 16
|
||||
|
||||
#define HW_VER_MAJOR_MASK GENMASK(31, 28)
|
||||
#define HW_VER_MAJOR_SHFT 28
|
||||
#define HW_VER_MINOR_MASK GENMASK(27, 16)
|
||||
#define HW_VER_MINOR_SHFT 16
|
||||
#define HW_VER_STEP_MASK GENMASK(15, 0)
|
||||
|
||||
#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
|
||||
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
|
||||
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
|
||||
|
||||
/* QUP SE VERSION value for major number 2 and minor number 5 */
|
||||
#define QUP_SE_VERSION_2_5 0x20050000
|
||||
|
||||
/*
|
||||
* Define bandwidth thresholds that cause the underlying Core 2X interconnect
|
||||
* clock to run at the named frequency. These baseline values are recommended
|
||||
* by the hardware team, and are not dynamically scaled with GENI bandwidth
|
||||
* beyond basic on/off.
|
||||
*/
|
||||
#define CORE_2X_19_2_MHZ 960
|
||||
#define CORE_2X_50_MHZ 2500
|
||||
#define CORE_2X_100_MHZ 5000
|
||||
#define CORE_2X_150_MHZ 7500
|
||||
#define CORE_2X_200_MHZ 10000
|
||||
#define CORE_2X_236_MHZ 16383
|
||||
|
||||
#define GENI_DEFAULT_BW Bps_to_icc(1000)
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
|
||||
|
||||
u32 geni_se_get_qup_hw_version(struct geni_se *se);
|
||||
|
||||
/**
|
||||
* geni_se_read_proto() - Read the protocol configured for a serial engine
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* Return: Protocol value as configured in the serial engine.
|
||||
*/
|
||||
static inline u32 geni_se_read_proto(struct geni_se *se)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
|
||||
|
||||
return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_setup_m_cmd() - Setup the primary sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
* @cmd: Command/Operation to setup in the primary sequencer.
|
||||
* @params: Parameter for the sequencer command.
|
||||
*
|
||||
* This function is used to configure the primary sequencer with the
|
||||
* command and its associated parameters.
|
||||
*/
|
||||
static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
|
||||
{
|
||||
u32 m_cmd;
|
||||
|
||||
m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
|
||||
writel(m_cmd, se->base + SE_GENI_M_CMD0);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_setup_s_cmd() - Setup the secondary sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
* @cmd: Command/Operation to setup in the secondary sequencer.
|
||||
* @params: Parameter for the sequencer command.
|
||||
*
|
||||
* This function is used to configure the secondary sequencer with the
|
||||
* command and its associated parameters.
|
||||
*/
|
||||
static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
|
||||
{
|
||||
u32 s_cmd;
|
||||
|
||||
s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
|
||||
s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
|
||||
s_cmd |= (cmd << S_OPCODE_SHFT);
|
||||
s_cmd |= (params & S_PARAMS_MSK);
|
||||
writel(s_cmd, se->base + SE_GENI_S_CMD0);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_cancel_m_cmd() - Cancel the command configured in the primary
|
||||
* sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to cancel the currently configured command in the
|
||||
* primary sequencer.
|
||||
*/
|
||||
static inline void geni_se_cancel_m_cmd(struct geni_se *se)
|
||||
{
|
||||
writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
|
||||
* sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to cancel the currently configured command in the
|
||||
* secondary sequencer.
|
||||
*/
|
||||
static inline void geni_se_cancel_s_cmd(struct geni_se *se)
|
||||
{
|
||||
writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to force abort the currently configured command in the
|
||||
* primary sequencer.
|
||||
*/
|
||||
static inline void geni_se_abort_m_cmd(struct geni_se *se)
|
||||
{
|
||||
writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_abort_s_cmd() - Abort the command configured in the secondary
|
||||
* sequencer
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to force abort the currently configured command in the
|
||||
* secondary sequencer.
|
||||
*/
|
||||
static inline void geni_se_abort_s_cmd(struct geni_se *se)
|
||||
{
|
||||
writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
|
||||
* based on QUP HW version
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to get the depth i.e. number of elements in the
|
||||
* TX fifo of the serial engine.
|
||||
*
|
||||
* Return: TX fifo depth in units of FIFO words.
|
||||
*/
|
||||
static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
|
||||
{
|
||||
u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask;
|
||||
|
||||
hw_version = geni_se_get_qup_hw_version(se);
|
||||
hw_major = GENI_SE_VERSION_MAJOR(hw_version);
|
||||
hw_minor = GENI_SE_VERSION_MINOR(hw_version);
|
||||
|
||||
if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
|
||||
tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES;
|
||||
else
|
||||
tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK;
|
||||
|
||||
val = readl_relaxed(se->base + SE_HW_PARAM_0);
|
||||
|
||||
return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to get the width i.e. word size per element in the
|
||||
* TX fifo of the serial engine.
|
||||
*
|
||||
* Return: TX fifo width in bits
|
||||
*/
|
||||
static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(se->base + SE_HW_PARAM_0);
|
||||
|
||||
return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
|
||||
* based on QUP HW version
|
||||
* @se: Pointer to the concerned serial engine.
|
||||
*
|
||||
* This function is used to get the depth i.e. number of elements in the
|
||||
* RX fifo of the serial engine.
|
||||
*
|
||||
* Return: RX fifo depth in units of FIFO words
|
||||
*/
|
||||
static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
|
||||
{
|
||||
u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask;
|
||||
|
||||
hw_version = geni_se_get_qup_hw_version(se);
|
||||
hw_major = GENI_SE_VERSION_MAJOR(hw_version);
|
||||
hw_minor = GENI_SE_VERSION_MINOR(hw_version);
|
||||
|
||||
if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3)
|
||||
rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES;
|
||||
else
|
||||
rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK;
|
||||
|
||||
val = readl_relaxed(se->base + SE_HW_PARAM_1);
|
||||
|
||||
return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT;
|
||||
}
|
||||
|
||||
void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
|
||||
|
||||
void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
|
||||
|
||||
void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
|
||||
bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
|
||||
|
||||
int geni_se_resources_off(struct geni_se *se);
|
||||
|
||||
int geni_se_resources_on(struct geni_se *se);
|
||||
|
||||
int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
|
||||
|
||||
int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
|
||||
unsigned int *index, unsigned long *res_freq,
|
||||
bool exact);
|
||||
|
||||
void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len);
|
||||
|
||||
int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
|
||||
dma_addr_t *iova);
|
||||
|
||||
void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len);
|
||||
|
||||
int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
|
||||
dma_addr_t *iova);
|
||||
|
||||
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
|
||||
|
||||
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
|
||||
|
||||
int geni_icc_get(struct geni_se *se, const char *icc_ddr);
|
||||
|
||||
int geni_icc_set_bw(struct geni_se *se);
|
||||
void geni_icc_set_tag(struct geni_se *se, u32 tag);
|
||||
|
||||
int geni_icc_enable(struct geni_se *se);
|
||||
|
||||
int geni_icc_disable(struct geni_se *se);
|
||||
|
||||
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __QCOM_IRQ_H
|
||||
#define __QCOM_IRQ_H
|
||||
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#define GPIO_NO_WAKE_IRQ ~0U
|
||||
|
||||
/*
|
||||
* QCOM specific IRQ domain flags that distinguishes the handling of wakeup
|
||||
* capable interrupts by different interrupt controllers.
|
||||
*
|
||||
* IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the
|
||||
* interrupt configuration is done at PDC
|
||||
* IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM
|
||||
*/
|
||||
#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
|
||||
#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)
|
||||
|
||||
/**
|
||||
* irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
|
||||
* configuration
|
||||
* @d: irq domain
|
||||
*
|
||||
* This QCOM specific irq domain call returns if the interrupt controller
|
||||
* requires the interrupt be masked at the child interrupt controller.
|
||||
*/
|
||||
static inline bool irq_domain_qcom_handle_wakeup(const struct irq_domain *d)
|
||||
{
|
||||
return (d->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,246 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#ifndef __LLCC_QCOM__
|
||||
#define __LLCC_QCOM__
|
||||
|
||||
#define LLCC_CPUSS 1
|
||||
#define LLCC_VIDSC0 2
|
||||
#define LLCC_VIDSC1 3
|
||||
#define LLCC_ROTATOR 4
|
||||
#define LLCC_VOICE 5
|
||||
#define LLCC_AUDIO 6
|
||||
#define LLCC_MDMHPGRW 7
|
||||
#define LLCC_MDM 8
|
||||
#define LLCC_MODHW 9
|
||||
#define LLCC_CMPT 10
|
||||
#define LLCC_GPUHTW 11
|
||||
#define LLCC_GPU 12
|
||||
#define LLCC_MMUHWT 13
|
||||
#define LLCC_CMPTDMA 15
|
||||
#define LLCC_DISP 16
|
||||
#define LLCC_VIDFW 17
|
||||
#define LLCC_CAMFW 18
|
||||
#define LLCC_MDMHPFX 20
|
||||
#define LLCC_MDMPNG 21
|
||||
#define LLCC_AUDHW 22
|
||||
#define LLCC_NPU 23
|
||||
#define LLCC_WLHW 24
|
||||
#define LLCC_PIMEM 25
|
||||
#define LLCC_ECC 26
|
||||
#define LLCC_CVP 28
|
||||
#define LLCC_MODPE 29
|
||||
#define LLCC_APTCM 30
|
||||
#define LLCC_WRCACHE 31
|
||||
#define LLCC_CVPFW 32
|
||||
#define LLCC_CPUSS1 33
|
||||
#define LLCC_CAMEXP0 34
|
||||
#define LLCC_CPUMTE 35
|
||||
#define LLCC_CPUHWT 36
|
||||
#define LLCC_MDMCLAD2 37
|
||||
#define LLCC_CAMEXP1 38
|
||||
#define LLCC_CMPTHCP 39
|
||||
#define LLCC_LCPDARE 40
|
||||
#define LLCC_AENPU 45
|
||||
#define LLCC_ISLAND1 46
|
||||
#define LLCC_ISLAND2 47
|
||||
#define LLCC_ISLAND3 48
|
||||
#define LLCC_ISLAND4 49
|
||||
#define LLCC_CAMEXP2 50
|
||||
#define LLCC_CAMEXP3 51
|
||||
#define LLCC_CAMEXP4 52
|
||||
#define LLCC_DISP_WB 53
|
||||
#define LLCC_DISP_1 54
|
||||
#define LLCC_VIEYE 57
|
||||
#define LLCC_VIDPTH 58
|
||||
#define LLCC_GPUMV 59
|
||||
#define LLCC_EVA_LEFT 60
|
||||
#define LLCC_EVA_RIGHT 61
|
||||
#define LLCC_EVAGAIN 62
|
||||
#define LLCC_VIPTH 63
|
||||
#define LLCC_VIDVSP 64
|
||||
#define LLCC_DISP_LEFT 65
|
||||
#define LLCC_DISP_RIGHT 66
|
||||
#define LLCC_EVCS_LEFT 67
|
||||
#define LLCC_EVCS_RIGHT 68
|
||||
#define LLCC_SPAD 69
|
||||
#define LLCC_VIDDEC 70
|
||||
#define LLCC_CAMOFE 71
|
||||
#define LLCC_CAMRTIP 72
|
||||
#define LLCC_CAMSRTIP 73
|
||||
#define LLCC_CAMRTRF 74
|
||||
#define LLCC_CAMSRTRF 75
|
||||
#define LLCC_OOBM_NS 81
|
||||
#define LLCC_OOBM_S 82
|
||||
#define LLCC_VIDEO_APV 83
|
||||
#define LLCC_COMPUTE1 87
|
||||
#define LLCC_CPUSS_OPP 88
|
||||
#define LLCC_CPUSSMPAM 89
|
||||
#define LLCC_VIDSC_VSP1 91
|
||||
#define LLCC_CAM_IPE_STROV 92
|
||||
#define LLCC_CAM_OFE_STROV 93
|
||||
#define LLCC_CPUSS_HEU 94
|
||||
#define LLCC_PCIE_TCU 97
|
||||
#define LLCC_MDM_PNG_FIXED 100
|
||||
|
||||
/**
|
||||
* struct llcc_slice_desc - Cache slice descriptor
|
||||
* @slice_id: llcc slice id
|
||||
* @slice_size: Size allocated for the llcc slice
|
||||
* @refcount: Atomic counter to track activate/deactivate calls
|
||||
*/
|
||||
struct llcc_slice_desc {
|
||||
u32 slice_id;
|
||||
size_t slice_size;
|
||||
refcount_t refcount;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct llcc_edac_reg_data - llcc edac registers data for each error type
|
||||
* @name: Name of the error
|
||||
* @reg_cnt: Number of registers
|
||||
* @count_mask: Mask value to get the error count
|
||||
* @ways_mask: Mask value to get the error ways
|
||||
* @count_shift: Shift value to get the error count
|
||||
* @ways_shift: Shift value to get the error ways
|
||||
*/
|
||||
struct llcc_edac_reg_data {
|
||||
char *name;
|
||||
u32 reg_cnt;
|
||||
u32 count_mask;
|
||||
u32 ways_mask;
|
||||
u8 count_shift;
|
||||
u8 ways_shift;
|
||||
};
|
||||
|
||||
struct llcc_edac_reg_offset {
|
||||
/* LLCC TRP registers */
|
||||
u32 trp_ecc_error_status0;
|
||||
u32 trp_ecc_error_status1;
|
||||
u32 trp_ecc_sb_err_syn0;
|
||||
u32 trp_ecc_db_err_syn0;
|
||||
u32 trp_ecc_error_cntr_clear;
|
||||
u32 trp_interrupt_0_status;
|
||||
u32 trp_interrupt_0_clear;
|
||||
u32 trp_interrupt_0_enable;
|
||||
|
||||
/* LLCC Common registers */
|
||||
u32 cmn_status0;
|
||||
u32 cmn_interrupt_0_enable;
|
||||
u32 cmn_interrupt_2_enable;
|
||||
|
||||
/* LLCC DRP registers */
|
||||
u32 drp_ecc_error_cfg;
|
||||
u32 drp_ecc_error_cntr_clear;
|
||||
u32 drp_interrupt_status;
|
||||
u32 drp_interrupt_clear;
|
||||
u32 drp_interrupt_enable;
|
||||
u32 drp_ecc_error_status0;
|
||||
u32 drp_ecc_error_status1;
|
||||
u32 drp_ecc_sb_err_syn0;
|
||||
u32 drp_ecc_db_err_syn0;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct llcc_drv_data - Data associated with the llcc driver
|
||||
* @regmaps: regmaps associated with the llcc device
|
||||
* @bcast_regmap: regmap associated with llcc broadcast OR offset
|
||||
* @bcast_and_regmap: regmap associated with llcc broadcast AND offset
|
||||
* @cfg: pointer to the data structure for slice configuration
|
||||
* @edac_reg_offset: Offset of the LLCC EDAC registers
|
||||
* @lock: mutex associated with each slice
|
||||
* @cfg_size: size of the config data table
|
||||
* @num_banks: Number of llcc banks
|
||||
* @ecc_irq: interrupt for llcc cache error detection and reporting
|
||||
* @ecc_irq_configured: 'True' if firmware has already configured the irq propagation
|
||||
* @desc: Array pointer of pre-allocated LLCC slice descriptors
|
||||
* @version: Indicates the LLCC version
|
||||
*/
|
||||
struct llcc_drv_data {
|
||||
struct regmap **regmaps;
|
||||
struct regmap *bcast_regmap;
|
||||
struct regmap *bcast_and_regmap;
|
||||
const struct llcc_slice_config *cfg;
|
||||
const struct llcc_edac_reg_offset *edac_reg_offset;
|
||||
struct mutex lock;
|
||||
u32 cfg_size;
|
||||
u32 num_banks;
|
||||
int ecc_irq;
|
||||
bool ecc_irq_configured;
|
||||
u32 version;
|
||||
struct llcc_slice_desc *desc;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_LLCC)
|
||||
/**
|
||||
* llcc_slice_getd - get llcc slice descriptor
|
||||
* @uid: usecase_id of the client
|
||||
*/
|
||||
struct llcc_slice_desc *llcc_slice_getd(u32 uid);
|
||||
|
||||
/**
|
||||
* llcc_slice_putd - llcc slice descritpor
|
||||
* @desc: Pointer to llcc slice descriptor
|
||||
*/
|
||||
void llcc_slice_putd(struct llcc_slice_desc *desc);
|
||||
|
||||
/**
|
||||
* llcc_get_slice_id - get slice id
|
||||
* @desc: Pointer to llcc slice descriptor
|
||||
*/
|
||||
int llcc_get_slice_id(struct llcc_slice_desc *desc);
|
||||
|
||||
/**
|
||||
* llcc_get_slice_size - llcc slice size
|
||||
* @desc: Pointer to llcc slice descriptor
|
||||
*/
|
||||
size_t llcc_get_slice_size(struct llcc_slice_desc *desc);
|
||||
|
||||
/**
|
||||
* llcc_slice_activate - Activate the llcc slice
|
||||
* @desc: Pointer to llcc slice descriptor
|
||||
*/
|
||||
int llcc_slice_activate(struct llcc_slice_desc *desc);
|
||||
|
||||
/**
|
||||
* llcc_slice_deactivate - Deactivate the llcc slice
|
||||
* @desc: Pointer to llcc slice descriptor
|
||||
*/
|
||||
int llcc_slice_deactivate(struct llcc_slice_desc *desc);
|
||||
|
||||
#else
|
||||
static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void llcc_slice_putd(struct llcc_slice_desc *desc)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
static inline int llcc_get_slice_id(struct llcc_slice_desc *desc)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int llcc_slice_activate(struct llcc_slice_desc *desc)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,73 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __QCOM_MDT_LOADER_H__
|
||||
#define __QCOM_MDT_LOADER_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define QCOM_MDT_TYPE_MASK (7 << 24)
|
||||
#define QCOM_MDT_TYPE_HASH (2 << 24)
|
||||
#define QCOM_MDT_RELOCATABLE BIT(27)
|
||||
|
||||
struct device;
|
||||
struct firmware;
|
||||
struct qcom_scm_pas_context;
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
|
||||
|
||||
ssize_t qcom_mdt_get_size(const struct firmware *fw);
|
||||
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
phys_addr_t *reloc_base);
|
||||
|
||||
int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
|
||||
const char *firmware, void *mem_region, phys_addr_t *reloc_base);
|
||||
|
||||
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
phys_addr_t *reloc_base);
|
||||
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
|
||||
const char *fw_name, struct device *dev);
|
||||
|
||||
#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
|
||||
|
||||
static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id,
|
||||
void *mem_region, phys_addr_t mem_phys,
|
||||
size_t mem_size, phys_addr_t *reloc_base)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx,
|
||||
const struct firmware *fw, const char *firmware,
|
||||
void *mem_region, phys_addr_t *reloc_base)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_load_no_init(struct device *dev,
|
||||
const struct firmware *fw,
|
||||
const char *fw_name, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
phys_addr_t *reloc_base)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
|
||||
size_t *data_len, const char *fw_name,
|
||||
struct device *dev)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
#endif /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __QCOM_PDR_HELPER__
|
||||
#define __QCOM_PDR_HELPER__
|
||||
|
||||
#include <linux/soc/qcom/qmi.h>
|
||||
|
||||
#define SERVREG_NAME_LENGTH 64
|
||||
#define SERVREG_PFR_LENGTH 256
|
||||
|
||||
struct pdr_service;
|
||||
struct pdr_handle;
|
||||
|
||||
enum servreg_service_state {
|
||||
SERVREG_LOCATOR_ERR = 0x1,
|
||||
SERVREG_SERVICE_STATE_DOWN = 0x0FFFFFFF,
|
||||
SERVREG_SERVICE_STATE_UP = 0x1FFFFFFF,
|
||||
SERVREG_SERVICE_STATE_EARLY_DOWN = 0x2FFFFFFF,
|
||||
SERVREG_SERVICE_STATE_UNINIT = 0x7FFFFFFF,
|
||||
};
|
||||
|
||||
struct pdr_handle *pdr_handle_alloc(void (*status)(int state,
|
||||
char *service_path,
|
||||
void *priv), void *priv);
|
||||
struct pdr_service *pdr_add_lookup(struct pdr_handle *pdr,
|
||||
const char *service_name,
|
||||
const char *service_path);
|
||||
int pdr_restart_pd(struct pdr_handle *pdr, struct pdr_service *pds);
|
||||
void pdr_handle_release(struct pdr_handle *pdr);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022, Linaro Ltd
|
||||
*/
|
||||
#ifndef __SOC_QCOM_PMIC_GLINK_H__
|
||||
#define __SOC_QCOM_PMIC_GLINK_H__
|
||||
|
||||
struct pmic_glink;
|
||||
struct pmic_glink_client;
|
||||
|
||||
#define PMIC_GLINK_OWNER_BATTMGR 32778
|
||||
#define PMIC_GLINK_OWNER_USBC 32779
|
||||
#define PMIC_GLINK_OWNER_USBC_PAN 32780
|
||||
|
||||
#define PMIC_GLINK_REQ_RESP 1
|
||||
#define PMIC_GLINK_NOTIFY 2
|
||||
|
||||
struct pmic_glink_hdr {
|
||||
__le32 owner;
|
||||
__le32 type;
|
||||
__le32 opcode;
|
||||
};
|
||||
|
||||
int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len);
|
||||
|
||||
struct pmic_glink_client *devm_pmic_glink_client_alloc(struct device *dev,
|
||||
unsigned int id,
|
||||
void (*cb)(const void *, size_t, void *),
|
||||
void (*pdr)(void *, int),
|
||||
void *priv);
|
||||
void pmic_glink_client_register(struct pmic_glink_client *client);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _QCOM_PBS_H
|
||||
#define _QCOM_PBS_H
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device_node;
|
||||
struct pbs_dev;
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_PBS)
|
||||
int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap);
|
||||
struct pbs_dev *get_pbs_client_device(struct device *client_dev);
|
||||
#else
|
||||
static inline int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline struct pbs_dev *get_pbs_client_device(struct device *client_dev)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __QCOM_AOSS_H__
|
||||
#define __QCOM_AOSS_H__
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
struct qmp;
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_AOSS_QMP)
|
||||
|
||||
int qmp_send(struct qmp *qmp, const char *fmt, ...);
|
||||
struct qmp *qmp_get(struct device *dev);
|
||||
void qmp_put(struct qmp *qmp);
|
||||
|
||||
#else
|
||||
|
||||
static inline int qmp_send(struct qmp *qmp, const char *fmt, ...)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline struct qmp *qmp_get(struct device *dev)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static inline void qmp_put(struct qmp *qmp)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,284 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017, Linaro Ltd.
|
||||
*/
|
||||
#ifndef __QMI_HELPERS_H__
|
||||
#define __QMI_HELPERS_H__
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/idr.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/qrtr.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
struct socket;
|
||||
|
||||
/**
|
||||
* struct qmi_header - wireformat header of QMI messages
|
||||
* @type: type of message
|
||||
* @txn_id: transaction id
|
||||
* @msg_id: message id
|
||||
* @msg_len: length of message payload following header
|
||||
*/
|
||||
struct qmi_header {
|
||||
u8 type;
|
||||
__le16 txn_id;
|
||||
__le16 msg_id;
|
||||
__le16 msg_len;
|
||||
} __packed;
|
||||
|
||||
#define QMI_REQUEST 0
|
||||
#define QMI_RESPONSE 2
|
||||
#define QMI_INDICATION 4
|
||||
|
||||
#define QMI_COMMON_TLV_TYPE 0
|
||||
|
||||
enum qmi_elem_type {
|
||||
QMI_EOTI,
|
||||
QMI_OPT_FLAG,
|
||||
QMI_DATA_LEN,
|
||||
QMI_UNSIGNED_1_BYTE,
|
||||
QMI_UNSIGNED_2_BYTE,
|
||||
QMI_UNSIGNED_4_BYTE,
|
||||
QMI_UNSIGNED_8_BYTE,
|
||||
QMI_SIGNED_2_BYTE_ENUM,
|
||||
QMI_SIGNED_4_BYTE_ENUM,
|
||||
QMI_STRUCT,
|
||||
QMI_STRING,
|
||||
};
|
||||
|
||||
enum qmi_array_type {
|
||||
NO_ARRAY,
|
||||
STATIC_ARRAY,
|
||||
VAR_LEN_ARRAY,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qmi_elem_info - describes how to encode a single QMI element
|
||||
* @data_type: Data type of this element.
|
||||
* @elem_len: Array length of this element, if an array.
|
||||
* @elem_size: Size of a single instance of this data type.
|
||||
* @array_type: Array type of this element.
|
||||
* @tlv_type: QMI message specific type to identify which element
|
||||
* is present in an incoming message.
|
||||
* @offset: Specifies the offset of the first instance of this
|
||||
* element in the data structure.
|
||||
* @ei_array: Null-terminated array of @qmi_elem_info to describe nested
|
||||
* structures.
|
||||
*/
|
||||
struct qmi_elem_info {
|
||||
enum qmi_elem_type data_type;
|
||||
u32 elem_len;
|
||||
u32 elem_size;
|
||||
enum qmi_array_type array_type;
|
||||
u8 tlv_type;
|
||||
u32 offset;
|
||||
const struct qmi_elem_info *ei_array;
|
||||
};
|
||||
|
||||
#define QMI_RESULT_SUCCESS_V01 0
|
||||
#define QMI_RESULT_FAILURE_V01 1
|
||||
|
||||
#define QMI_ERR_NONE_V01 0
|
||||
#define QMI_ERR_MALFORMED_MSG_V01 1
|
||||
#define QMI_ERR_NO_MEMORY_V01 2
|
||||
#define QMI_ERR_INTERNAL_V01 3
|
||||
#define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 5
|
||||
#define QMI_ERR_INVALID_ID_V01 41
|
||||
#define QMI_ERR_ENCODING_V01 58
|
||||
#define QMI_ERR_DISABLED_V01 69
|
||||
#define QMI_ERR_INCOMPATIBLE_STATE_V01 90
|
||||
#define QMI_ERR_NOT_SUPPORTED_V01 94
|
||||
|
||||
/*
|
||||
* Enumerate the IDs of the QMI services
|
||||
*/
|
||||
#define QMI_SERVICE_ID_TEST 0x0f /* 15 */
|
||||
#define QMI_SERVICE_ID_SSCTL 0x2b /* 43 */
|
||||
#define QMI_SERVICE_ID_IPA 0x31 /* 49 */
|
||||
#define QMI_SERVICE_ID_SERVREG_LOC 0x40 /* 64 */
|
||||
#define QMI_SERVICE_ID_SERVREG_NOTIF 0x42 /* 66 */
|
||||
#define QMI_SERVICE_ID_WLFW 0x45 /* 69 */
|
||||
#define QMI_SERVICE_ID_SLIMBUS 0x301 /* 769 */
|
||||
#define QMI_SERVICE_ID_USB_AUDIO_STREAM 0x41d /* 1053 */
|
||||
|
||||
/**
|
||||
* struct qmi_response_type_v01 - common response header (decoded)
|
||||
* @result: result of the transaction
|
||||
* @error: error value, when @result is QMI_RESULT_FAILURE_V01
|
||||
*/
|
||||
struct qmi_response_type_v01 {
|
||||
u16 result;
|
||||
u16 error;
|
||||
};
|
||||
|
||||
extern const struct qmi_elem_info qmi_response_type_v01_ei[];
|
||||
|
||||
/**
|
||||
* struct qmi_service - context to track lookup-results
|
||||
* @service: service type
|
||||
* @version: version of the @service
|
||||
* @instance: instance id of the @service
|
||||
* @node: node of the service
|
||||
* @port: port of the service
|
||||
* @priv: handle for client's use
|
||||
* @list_node: list_head for house keeping
|
||||
*/
|
||||
struct qmi_service {
|
||||
unsigned int service;
|
||||
unsigned int version;
|
||||
unsigned int instance;
|
||||
|
||||
unsigned int node;
|
||||
unsigned int port;
|
||||
|
||||
void *priv;
|
||||
struct list_head list_node;
|
||||
};
|
||||
|
||||
struct qmi_handle;
|
||||
|
||||
/**
|
||||
* struct qmi_ops - callbacks for qmi_handle
|
||||
* @new_server: inform client of a new_server lookup-result, returning
|
||||
* successfully from this call causes the library to call
|
||||
* @del_server as the service is removed from the
|
||||
* lookup-result. @priv of the qmi_service can be used by
|
||||
* the client
|
||||
* @del_server: inform client of a del_server lookup-result
|
||||
* @net_reset: inform client that the name service was restarted and
|
||||
* that and any state needs to be released
|
||||
* @msg_handler: invoked for incoming messages, allows a client to
|
||||
* override the usual QMI message handler
|
||||
* @bye: inform a client that all clients from a node are gone
|
||||
* @del_client: inform a client that a particular client is gone
|
||||
*/
|
||||
struct qmi_ops {
|
||||
int (*new_server)(struct qmi_handle *qmi, struct qmi_service *svc);
|
||||
void (*del_server)(struct qmi_handle *qmi, struct qmi_service *svc);
|
||||
void (*net_reset)(struct qmi_handle *qmi);
|
||||
void (*msg_handler)(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
|
||||
const void *data, size_t count);
|
||||
void (*bye)(struct qmi_handle *qmi, unsigned int node);
|
||||
void (*del_client)(struct qmi_handle *qmi,
|
||||
unsigned int node, unsigned int port);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qmi_txn - transaction context
|
||||
* @qmi: QMI handle this transaction is associated with
|
||||
* @id: transaction id
|
||||
* @lock: for synchronization between handler and waiter of messages
|
||||
* @completion: completion object as the transaction receives a response
|
||||
* @result: result code for the completed transaction
|
||||
* @ei: description of the QMI encoded response (optional)
|
||||
* @dest: destination buffer to decode message into (optional)
|
||||
*/
|
||||
struct qmi_txn {
|
||||
struct qmi_handle *qmi;
|
||||
|
||||
u16 id;
|
||||
|
||||
struct mutex lock;
|
||||
struct completion completion;
|
||||
int result;
|
||||
|
||||
const struct qmi_elem_info *ei;
|
||||
void *dest;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qmi_msg_handler - description of QMI message handler
|
||||
* @type: type of message
|
||||
* @msg_id: message id
|
||||
* @ei: description of the QMI encoded message
|
||||
* @decoded_size: size of the decoded object
|
||||
* @fn: function to invoke as the message is decoded
|
||||
*/
|
||||
struct qmi_msg_handler {
|
||||
unsigned int type;
|
||||
unsigned int msg_id;
|
||||
|
||||
const struct qmi_elem_info *ei;
|
||||
|
||||
size_t decoded_size;
|
||||
void (*fn)(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
|
||||
struct qmi_txn *txn, const void *decoded);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qmi_handle - QMI context
|
||||
* @sock: socket handle
|
||||
* @sock_lock: synchronization of @sock modifications
|
||||
* @sq: sockaddr of @sock
|
||||
* @work: work for handling incoming messages
|
||||
* @wq: workqueue to post @work on
|
||||
* @recv_buf: scratch buffer for handling incoming messages
|
||||
* @recv_buf_size: size of @recv_buf
|
||||
* @lookups: list of registered lookup requests
|
||||
* @lookup_results: list of lookup-results advertised to the client
|
||||
* @services: list of registered services (by this client)
|
||||
* @ops: reference to callbacks
|
||||
* @txns: outstanding transactions
|
||||
* @txn_lock: lock for modifications of @txns
|
||||
* @handlers: list of handlers for incoming messages
|
||||
*/
|
||||
struct qmi_handle {
|
||||
struct socket *sock;
|
||||
struct mutex sock_lock;
|
||||
|
||||
struct sockaddr_qrtr sq;
|
||||
|
||||
struct work_struct work;
|
||||
struct workqueue_struct *wq;
|
||||
|
||||
void *recv_buf;
|
||||
size_t recv_buf_size;
|
||||
|
||||
struct list_head lookups;
|
||||
struct list_head lookup_results;
|
||||
struct list_head services;
|
||||
|
||||
struct qmi_ops ops;
|
||||
|
||||
struct idr txns;
|
||||
struct mutex txn_lock;
|
||||
|
||||
const struct qmi_msg_handler *handlers;
|
||||
};
|
||||
|
||||
int qmi_add_lookup(struct qmi_handle *qmi, unsigned int service,
|
||||
unsigned int version, unsigned int instance);
|
||||
int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
|
||||
unsigned int version, unsigned int instance);
|
||||
|
||||
int qmi_handle_init(struct qmi_handle *qmi, size_t max_msg_len,
|
||||
const struct qmi_ops *ops,
|
||||
const struct qmi_msg_handler *handlers);
|
||||
void qmi_handle_release(struct qmi_handle *qmi);
|
||||
|
||||
ssize_t qmi_send_request(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
|
||||
struct qmi_txn *txn, int msg_id, size_t len,
|
||||
const struct qmi_elem_info *ei, const void *c_struct);
|
||||
ssize_t qmi_send_response(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
|
||||
struct qmi_txn *txn, int msg_id, size_t len,
|
||||
const struct qmi_elem_info *ei, const void *c_struct);
|
||||
ssize_t qmi_send_indication(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
|
||||
int msg_id, size_t len, const struct qmi_elem_info *ei,
|
||||
const void *c_struct);
|
||||
|
||||
void *qmi_encode_message(int type, unsigned int msg_id, size_t *len,
|
||||
unsigned int txn_id, const struct qmi_elem_info *ei,
|
||||
const void *c_struct);
|
||||
|
||||
int qmi_decode_message(const void *buf, size_t len,
|
||||
const struct qmi_elem_info *ei, void *c_struct);
|
||||
|
||||
int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn,
|
||||
const struct qmi_elem_info *ei, void *c_struct);
|
||||
int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout);
|
||||
void qmi_txn_cancel(struct qmi_txn *txn);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,68 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __QCOM_SMD_RPM_H__
|
||||
#define __QCOM_SMD_RPM_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct qcom_smd_rpm;
|
||||
|
||||
#define QCOM_SMD_RPM_ACTIVE_STATE 0
|
||||
#define QCOM_SMD_RPM_SLEEP_STATE 1
|
||||
#define QCOM_SMD_RPM_STATE_NUM 2
|
||||
|
||||
/*
|
||||
* Constants used for addressing resources in the RPM.
|
||||
*/
|
||||
#define QCOM_SMD_RPM_BBYB 0x62796262
|
||||
#define QCOM_SMD_RPM_BOBB 0x62626f62
|
||||
#define QCOM_SMD_RPM_BOOST 0x61747362
|
||||
#define QCOM_SMD_RPM_BUS_CLK 0x316b6c63
|
||||
#define QCOM_SMD_RPM_BUS_MASTER 0x73616d62
|
||||
#define QCOM_SMD_RPM_BUS_SLAVE 0x766c7362
|
||||
#define QCOM_SMD_RPM_CLK_BUF_A 0x616B6C63
|
||||
#define QCOM_SMD_RPM_LDOA 0x616f646c
|
||||
#define QCOM_SMD_RPM_LDOB 0x626F646C
|
||||
#define QCOM_SMD_RPM_LDOE 0x656f646c
|
||||
#define QCOM_SMD_RPM_RWCX 0x78637772
|
||||
#define QCOM_SMD_RPM_RWMX 0x786d7772
|
||||
#define QCOM_SMD_RPM_RWLC 0x636c7772
|
||||
#define QCOM_SMD_RPM_RWLM 0x6d6c7772
|
||||
#define QCOM_SMD_RPM_MEM_CLK 0x326b6c63
|
||||
#define QCOM_SMD_RPM_MISC_CLK 0x306b6c63
|
||||
#define QCOM_SMD_RPM_NCPA 0x6170636E
|
||||
#define QCOM_SMD_RPM_NCPB 0x6270636E
|
||||
#define QCOM_SMD_RPM_OCMEM_PWR 0x706d636f
|
||||
#define QCOM_SMD_RPM_QPIC_CLK 0x63697071
|
||||
#define QCOM_SMD_RPM_QUP_CLK 0x707571
|
||||
#define QCOM_SMD_RPM_SMPA 0x61706d73
|
||||
#define QCOM_SMD_RPM_SMPB 0x62706d73
|
||||
#define QCOM_SMD_RPM_SMPE 0x65706d73
|
||||
#define QCOM_SMD_RPM_SPDM 0x63707362
|
||||
#define QCOM_SMD_RPM_VSA 0x00617376
|
||||
#define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d
|
||||
#define QCOM_SMD_RPM_IPA_CLK 0x617069
|
||||
#define QCOM_SMD_RPM_CE_CLK 0x6563
|
||||
#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
|
||||
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
|
||||
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
|
||||
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
|
||||
|
||||
#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
|
||||
#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
|
||||
#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
|
||||
#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
|
||||
#define QCOM_RPM_SMD_KEY_STATE 0x54415453
|
||||
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
|
||||
|
||||
struct clk_smd_rpm_req {
|
||||
__le32 key;
|
||||
__le32 nbytes;
|
||||
__le32 value;
|
||||
};
|
||||
|
||||
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
|
||||
int state,
|
||||
u32 resource_type, u32 resource_id,
|
||||
void *buf, size_t count);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __QCOM_SMEM_H__
|
||||
#define __QCOM_SMEM_H__
|
||||
|
||||
#define QCOM_SMEM_HOST_ANY -1
|
||||
|
||||
bool qcom_smem_is_available(void);
|
||||
int qcom_smem_alloc(unsigned host, unsigned item, size_t size);
|
||||
void *qcom_smem_get(unsigned host, unsigned item, size_t *size);
|
||||
|
||||
int qcom_smem_get_free_space(unsigned host);
|
||||
|
||||
phys_addr_t qcom_smem_virt_to_phys(void *p);
|
||||
|
||||
int qcom_smem_get_soc_id(u32 *id);
|
||||
int qcom_smem_get_feature_code(u32 *code);
|
||||
|
||||
int qcom_smem_bust_hwspin_lock_by_host(unsigned int host);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __QCOM_SMEM_STATE__
|
||||
#define __QCOM_SMEM_STATE__
|
||||
|
||||
#include <linux/err.h>
|
||||
|
||||
struct device_node;
|
||||
struct qcom_smem_state;
|
||||
|
||||
struct qcom_smem_state_ops {
|
||||
int (*update_bits)(void *, u32, u32);
|
||||
};
|
||||
|
||||
#ifdef CONFIG_QCOM_SMEM_STATE
|
||||
|
||||
struct qcom_smem_state *qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
|
||||
struct qcom_smem_state *devm_qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
|
||||
void qcom_smem_state_put(struct qcom_smem_state *);
|
||||
|
||||
int qcom_smem_state_update_bits(struct qcom_smem_state *state, u32 mask, u32 value);
|
||||
|
||||
struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node, const struct qcom_smem_state_ops *ops, void *data);
|
||||
void qcom_smem_state_unregister(struct qcom_smem_state *state);
|
||||
|
||||
#else
|
||||
|
||||
static inline struct qcom_smem_state *qcom_smem_state_get(struct device *dev,
|
||||
const char *con_id, unsigned *bit)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline struct qcom_smem_state *devm_qcom_smem_state_get(struct device *dev,
|
||||
const char *con_id,
|
||||
unsigned *bit)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline void qcom_smem_state_put(struct qcom_smem_state *state)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int qcom_smem_state_update_bits(struct qcom_smem_state *state,
|
||||
u32 mask, u32 value)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node,
|
||||
const struct qcom_smem_state_ops *ops, void *data)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline void qcom_smem_state_unregister(struct qcom_smem_state *state)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,115 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef __QCOM_SOCINFO_H__
|
||||
#define __QCOM_SOCINFO_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* SMEM item id, used to acquire handles to respective
|
||||
* SMEM region.
|
||||
*/
|
||||
#define SMEM_HW_SW_BUILD_ID 137
|
||||
|
||||
#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
|
||||
#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
|
||||
|
||||
/*
|
||||
* SoC version type with major number in the upper 16 bits and minor
|
||||
* number in the lower 16 bits.
|
||||
*/
|
||||
#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
|
||||
#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
|
||||
#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
|
||||
|
||||
/* Socinfo SMEM item structure */
|
||||
struct socinfo {
|
||||
__le32 fmt;
|
||||
__le32 id;
|
||||
__le32 ver;
|
||||
char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
|
||||
/* Version 2 */
|
||||
__le32 raw_id;
|
||||
__le32 raw_ver;
|
||||
/* Version 3 */
|
||||
__le32 hw_plat;
|
||||
/* Version 4 */
|
||||
__le32 plat_ver;
|
||||
/* Version 5 */
|
||||
__le32 accessory_chip;
|
||||
/* Version 6 */
|
||||
__le32 hw_plat_subtype;
|
||||
/* Version 7 */
|
||||
__le32 pmic_model;
|
||||
__le32 pmic_die_rev;
|
||||
/* Version 8 */
|
||||
__le32 pmic_model_1;
|
||||
__le32 pmic_die_rev_1;
|
||||
__le32 pmic_model_2;
|
||||
__le32 pmic_die_rev_2;
|
||||
/* Version 9 */
|
||||
__le32 foundry_id;
|
||||
/* Version 10 */
|
||||
__le32 serial_num;
|
||||
/* Version 11 */
|
||||
__le32 num_pmics;
|
||||
__le32 pmic_array_offset;
|
||||
/* Version 12 */
|
||||
__le32 chip_family;
|
||||
__le32 raw_device_family;
|
||||
__le32 raw_device_num;
|
||||
/* Version 13 */
|
||||
__le32 nproduct_id;
|
||||
char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
|
||||
/* Version 14 */
|
||||
__le32 num_clusters;
|
||||
__le32 ncluster_array_offset;
|
||||
__le32 num_subset_parts;
|
||||
__le32 nsubset_parts_array_offset;
|
||||
/* Version 15 */
|
||||
__le32 nmodem_supported;
|
||||
/* Version 16 */
|
||||
__le32 feature_code;
|
||||
__le32 pcode;
|
||||
__le32 npartnamemap_offset;
|
||||
__le32 nnum_partname_mapping;
|
||||
/* Version 17 */
|
||||
__le32 oem_variant;
|
||||
/* Version 18 */
|
||||
__le32 num_kvps;
|
||||
__le32 kvps_offset;
|
||||
/* Version 19 */
|
||||
__le32 num_func_clusters;
|
||||
__le32 boot_cluster;
|
||||
__le32 boot_core;
|
||||
/* Version 20 */
|
||||
__le32 raw_package_type;
|
||||
/* Version 21, 22, 23 */
|
||||
__le32 reserve1[4];
|
||||
};
|
||||
|
||||
/* Internal feature codes */
|
||||
enum qcom_socinfo_feature_code {
|
||||
/* External feature codes */
|
||||
SOCINFO_FC_UNKNOWN = 0x0,
|
||||
SOCINFO_FC_AA,
|
||||
SOCINFO_FC_AB,
|
||||
SOCINFO_FC_AC,
|
||||
SOCINFO_FC_AD,
|
||||
SOCINFO_FC_AE,
|
||||
SOCINFO_FC_AF,
|
||||
SOCINFO_FC_AG,
|
||||
SOCINFO_FC_AH,
|
||||
};
|
||||
|
||||
/* Internal feature codes */
|
||||
/* Valid values: 0 <= n <= 0xf */
|
||||
#define SOCINFO_FC_Yn(n) (0xf1 + (n))
|
||||
#define SOCINFO_FC_INT_MAX SOCINFO_FC_Yn(0xf)
|
||||
|
||||
/* Product codes */
|
||||
#define SOCINFO_PC_UNKNOWN 0
|
||||
#define SOCINFO_PCn(n) ((n) + 1)
|
||||
#define SOCINFO_PC_RESERVE (BIT(31) - 1)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,102 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef __QCOM_UBWC_H__
|
||||
#define __QCOM_UBWC_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct qcom_ubwc_cfg_data {
|
||||
u32 ubwc_enc_version;
|
||||
/* Can be read from MDSS_BASE + 0x58 */
|
||||
u32 ubwc_dec_version;
|
||||
|
||||
/**
|
||||
* @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
|
||||
*
|
||||
* UBWC 1.0 always enables all three levels.
|
||||
* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
|
||||
* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
|
||||
*/
|
||||
u32 ubwc_swizzle;
|
||||
#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
|
||||
#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
|
||||
#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
|
||||
|
||||
/**
|
||||
* @highest_bank_bit: Highest Bank Bit
|
||||
*
|
||||
* The Highest Bank Bit value represents the bit of the highest
|
||||
* DDR bank. This should ideally use DRAM type detection.
|
||||
*/
|
||||
int highest_bank_bit;
|
||||
bool ubwc_bank_spread;
|
||||
|
||||
/**
|
||||
* @macrotile_mode: Macrotile Mode
|
||||
*
|
||||
* Whether to use 4-channel macrotiling mode or the newer
|
||||
* 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
|
||||
* 4-channel and 1 is 8-channel.
|
||||
*/
|
||||
bool macrotile_mode;
|
||||
};
|
||||
|
||||
#define UBWC_1_0 0x10000000
|
||||
#define UBWC_2_0 0x20000000
|
||||
#define UBWC_3_0 0x30000000
|
||||
#define UBWC_4_0 0x40000000
|
||||
#define UBWC_4_3 0x40030000
|
||||
#define UBWC_5_0 0x50000000
|
||||
#define UBWC_6_0 0x60000000
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG)
|
||||
const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
|
||||
#else
|
||||
static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
|
||||
{
|
||||
return ERR_PTR(-EOPNOTSUPP);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
|
||||
{
|
||||
bool ret = cfg->ubwc_enc_version == UBWC_1_0;
|
||||
|
||||
if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
|
||||
pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the best guess, based on the MDSS driver, which worked so far.
|
||||
*/
|
||||
static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg)
|
||||
{
|
||||
return cfg->ubwc_enc_version == UBWC_1_0 &&
|
||||
(cfg->ubwc_dec_version == UBWC_2_0 ||
|
||||
cfg->ubwc_dec_version == UBWC_3_0);
|
||||
}
|
||||
|
||||
static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg)
|
||||
{
|
||||
return cfg->macrotile_mode;
|
||||
}
|
||||
|
||||
static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg)
|
||||
{
|
||||
return cfg->ubwc_bank_spread;
|
||||
}
|
||||
|
||||
static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
|
||||
{
|
||||
return cfg->ubwc_swizzle;
|
||||
}
|
||||
|
||||
#endif /* __QCOM_UBWC_H__ */
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __WCNSS_CTRL_H__
|
||||
#define __WCNSS_CTRL_H__
|
||||
|
||||
#include <linux/rpmsg.h>
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_WCNSS_CTRL)
|
||||
|
||||
struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss, const char *name,
|
||||
rpmsg_rx_cb_t cb, void *priv);
|
||||
|
||||
#else
|
||||
|
||||
static struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss,
|
||||
const char *name,
|
||||
rpmsg_rx_cb_t cb,
|
||||
void *priv)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return ERR_PTR(-ENXIO);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__
|
||||
#define __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__
|
||||
|
||||
#ifdef CONFIG_CLK_R9A06G032
|
||||
int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val);
|
||||
#else
|
||||
static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; }
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__ */
|
||||
@@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SOC_RENESAS_RCAR_RST_H__
|
||||
#define __LINUX_SOC_RENESAS_RCAR_RST_H__
|
||||
|
||||
#ifdef CONFIG_RST_RCAR
|
||||
int rcar_rst_read_mode_pins(u32 *mode);
|
||||
int rcar_rst_set_rproc_boot_addr(u64 boot_addr);
|
||||
#else
|
||||
static inline int rcar_rst_read_mode_pins(u32 *mode) { return -ENODEV; }
|
||||
static inline int rcar_rst_set_rproc_boot_addr(u64 boot_addr) { return -ENODEV; }
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_SOC_RENESAS_RCAR_RST_H__ */
|
||||
@@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_SOC_RENESAS_RCAR_SYSC_H__
|
||||
#define __LINUX_SOC_RENESAS_RCAR_SYSC_H__
|
||||
|
||||
int rcar_sysc_power_down_cpu(unsigned int cpu);
|
||||
int rcar_sysc_power_up_cpu(unsigned int cpu);
|
||||
|
||||
#endif /* __LINUX_SOC_RENESAS_RCAR_SYSC_H__ */
|
||||
@@ -0,0 +1,50 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Exynos - CHIPID support
|
||||
*/
|
||||
#ifndef __LINUX_SOC_EXYNOS_CHIPID_H
|
||||
#define __LINUX_SOC_EXYNOS_CHIPID_H
|
||||
|
||||
#define EXYNOS_CHIPID_REG_PRO_ID 0x00
|
||||
#define EXYNOS_REV_PART_MASK 0xf
|
||||
#define EXYNOS_REV_PART_SHIFT 4
|
||||
#define EXYNOS_MASK 0xfffff000
|
||||
|
||||
#define EXYNOS_CHIPID_REG_PKG_ID 0x04
|
||||
/* Bit field definitions for EXYNOS_CHIPID_REG_PKG_ID register */
|
||||
#define EXYNOS5422_IDS_OFFSET 24
|
||||
#define EXYNOS5422_IDS_MASK 0xff
|
||||
#define EXYNOS5422_USESG_OFFSET 3
|
||||
#define EXYNOS5422_USESG_MASK 0x01
|
||||
#define EXYNOS5422_SG_OFFSET 0
|
||||
#define EXYNOS5422_SG_MASK 0x07
|
||||
#define EXYNOS5422_TABLE_OFFSET 8
|
||||
#define EXYNOS5422_TABLE_MASK 0x03
|
||||
#define EXYNOS5422_SG_A_OFFSET 17
|
||||
#define EXYNOS5422_SG_A_MASK 0x0f
|
||||
#define EXYNOS5422_SG_B_OFFSET 21
|
||||
#define EXYNOS5422_SG_B_MASK 0x03
|
||||
#define EXYNOS5422_SG_BSIGN_OFFSET 23
|
||||
#define EXYNOS5422_SG_BSIGN_MASK 0x01
|
||||
#define EXYNOS5422_BIN2_OFFSET 12
|
||||
#define EXYNOS5422_BIN2_MASK 0x01
|
||||
|
||||
#define EXYNOS_CHIPID_REG_LOT_ID 0x14
|
||||
|
||||
#define EXYNOS_CHIPID_REG_AUX_INFO 0x1c
|
||||
/* Bit field definitions for EXYNOS_CHIPID_REG_AUX_INFO register */
|
||||
#define EXYNOS5422_TMCB_OFFSET 0
|
||||
#define EXYNOS5422_TMCB_MASK 0x7f
|
||||
#define EXYNOS5422_ARM_UP_OFFSET 8
|
||||
#define EXYNOS5422_ARM_UP_MASK 0x03
|
||||
#define EXYNOS5422_ARM_DN_OFFSET 10
|
||||
#define EXYNOS5422_ARM_DN_MASK 0x03
|
||||
#define EXYNOS5422_KFC_UP_OFFSET 12
|
||||
#define EXYNOS5422_KFC_UP_MASK 0x03
|
||||
#define EXYNOS5422_KFC_DN_OFFSET 14
|
||||
#define EXYNOS5422_KFC_DN_MASK 0x03
|
||||
|
||||
#endif /*__LINUX_SOC_EXYNOS_CHIPID_H */
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header for Exynos PMU Driver support
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SOC_EXYNOS_PMU_H
|
||||
#define __LINUX_SOC_EXYNOS_PMU_H
|
||||
|
||||
struct regmap;
|
||||
struct device_node;
|
||||
|
||||
enum sys_powerdown {
|
||||
SYS_AFTR,
|
||||
SYS_LPA,
|
||||
SYS_SLEEP,
|
||||
NUM_SYS_POWERDOWN,
|
||||
};
|
||||
|
||||
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
|
||||
#ifdef CONFIG_EXYNOS_PMU
|
||||
struct regmap *exynos_get_pmu_regmap(void);
|
||||
struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
|
||||
const char *propname);
|
||||
#else
|
||||
static inline struct regmap *exynos_get_pmu_regmap(void)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static inline struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
|
||||
const char *propname)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_SOC_EXYNOS_PMU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
* Tomasz Figa <t.figa@samsung.com>
|
||||
* Copyright (c) 2004 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Written by Ben Dooks, <ben@simtec.co.uk>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_SOC_SAMSUNG_S3C_PM_H
|
||||
#define __LINUX_SOC_SAMSUNG_S3C_PM_H __FILE__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* PM debug functions */
|
||||
|
||||
#define S3C_PMDBG(fmt...) pr_debug(fmt)
|
||||
|
||||
static inline void s3c_pm_save_uarts(bool is_s3c24xx) { }
|
||||
static inline void s3c_pm_restore_uarts(bool is_s3c24xx) { }
|
||||
|
||||
/* suspend memory checking */
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_PM_CHECK
|
||||
extern void s3c_pm_check_prepare(void);
|
||||
extern void s3c_pm_check_restore(void);
|
||||
extern void s3c_pm_check_cleanup(void);
|
||||
extern void s3c_pm_check_store(void);
|
||||
#else
|
||||
#define s3c_pm_check_prepare() do { } while (0)
|
||||
#define s3c_pm_check_restore() do { } while (0)
|
||||
#define s3c_pm_check_cleanup() do { } while (0)
|
||||
#define s3c_pm_check_store() do { } while (0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Allwinner SoCs SRAM Controller Driver
|
||||
*
|
||||
* Copyright (C) 2015 Maxime Ripard
|
||||
*
|
||||
* Author: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _SUNXI_SRAM_H_
|
||||
#define _SUNXI_SRAM_H_
|
||||
|
||||
int sunxi_sram_claim(struct device *dev);
|
||||
void sunxi_sram_release(struct device *dev);
|
||||
|
||||
#endif /* _SUNXI_SRAM_H_ */
|
||||
@@ -0,0 +1,270 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* K3 Ring Accelerator (RA) subsystem interface
|
||||
*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TI_K3_RINGACC_API_H_
|
||||
#define __SOC_TI_K3_RINGACC_API_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device_node;
|
||||
|
||||
/**
|
||||
* enum k3_ring_mode - &struct k3_ring_cfg mode
|
||||
*
|
||||
* RA ring operational modes
|
||||
*
|
||||
* @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
|
||||
* @K3_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires
|
||||
* that all accesses to the queue must go through this IP so that all
|
||||
* accesses to the memory are controlled and ordered. This IP then
|
||||
* controls the entire state of the queue, and SW has no directly control,
|
||||
* such as through doorbells and cannot access the storage memory directly.
|
||||
* This is particularly useful when more than one SW or HW entity can be
|
||||
* the producer and/or consumer at the same time
|
||||
* @K3_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus
|
||||
* stores credentials with each message, requiring the element size to be
|
||||
* doubled to fit the credentials. Any exposed memory should be protected
|
||||
* by a firewall from unwanted access
|
||||
*/
|
||||
enum k3_ring_mode {
|
||||
K3_RINGACC_RING_MODE_RING = 0,
|
||||
K3_RINGACC_RING_MODE_MESSAGE,
|
||||
K3_RINGACC_RING_MODE_CREDENTIALS,
|
||||
K3_RINGACC_RING_MODE_INVALID
|
||||
};
|
||||
|
||||
/**
|
||||
* enum k3_ring_size - &struct k3_ring_cfg elm_size
|
||||
*
|
||||
* RA ring element's sizes in bytes.
|
||||
*/
|
||||
enum k3_ring_size {
|
||||
K3_RINGACC_RING_ELSIZE_4 = 0,
|
||||
K3_RINGACC_RING_ELSIZE_8,
|
||||
K3_RINGACC_RING_ELSIZE_16,
|
||||
K3_RINGACC_RING_ELSIZE_32,
|
||||
K3_RINGACC_RING_ELSIZE_64,
|
||||
K3_RINGACC_RING_ELSIZE_128,
|
||||
K3_RINGACC_RING_ELSIZE_256,
|
||||
K3_RINGACC_RING_ELSIZE_INVALID
|
||||
};
|
||||
|
||||
struct k3_ringacc;
|
||||
struct k3_ring;
|
||||
|
||||
/**
|
||||
* enum k3_ring_cfg - RA ring configuration structure
|
||||
*
|
||||
* @size: Ring size, number of elements
|
||||
* @elm_size: Ring element size
|
||||
* @mode: Ring operational mode
|
||||
* @flags: Ring configuration flags. Possible values:
|
||||
* @K3_RINGACC_RING_SHARED: when set allows to request the same ring
|
||||
* few times. It's usable when the same ring is used as Free Host PD ring
|
||||
* for different flows, for example.
|
||||
* Note: Locking should be done by consumer if required
|
||||
* @dma_dev: Master device which is using and accessing to the ring
|
||||
* memory when the mode is K3_RINGACC_RING_MODE_RING. Memory allocations
|
||||
* should be done using this device.
|
||||
* @asel: Address Space Select value for physical addresses
|
||||
*/
|
||||
struct k3_ring_cfg {
|
||||
u32 size;
|
||||
enum k3_ring_size elm_size;
|
||||
enum k3_ring_mode mode;
|
||||
#define K3_RINGACC_RING_SHARED BIT(1)
|
||||
u32 flags;
|
||||
|
||||
struct device *dma_dev;
|
||||
u32 asel;
|
||||
};
|
||||
|
||||
#define K3_RINGACC_RING_ID_ANY (-1)
|
||||
|
||||
/**
|
||||
* of_k3_ringacc_get_by_phandle - find a RA by phandle property
|
||||
* @np: device node
|
||||
* @propname: property name containing phandle on RA node
|
||||
*
|
||||
* Returns pointer on the RA - struct k3_ringacc
|
||||
* or -ENODEV if not found,
|
||||
* or -EPROBE_DEFER if not yet registered
|
||||
*/
|
||||
struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np,
|
||||
const char *property);
|
||||
|
||||
#define K3_RINGACC_RING_USE_PROXY BIT(1)
|
||||
|
||||
/**
|
||||
* k3_ringacc_request_ring - request ring from ringacc
|
||||
* @ringacc: pointer on ringacc
|
||||
* @id: ring id or K3_RINGACC_RING_ID_ANY for any general purpose ring
|
||||
* @flags:
|
||||
* @K3_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
|
||||
* used to access ring memory. Sopported only for rings in
|
||||
* Message/Credentials/Queue mode.
|
||||
*
|
||||
* Returns pointer on the Ring - struct k3_ring
|
||||
* or NULL in case of failure.
|
||||
*/
|
||||
struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc,
|
||||
int id, u32 flags);
|
||||
|
||||
int k3_ringacc_request_rings_pair(struct k3_ringacc *ringacc,
|
||||
int fwd_id, int compl_id,
|
||||
struct k3_ring **fwd_ring,
|
||||
struct k3_ring **compl_ring);
|
||||
/**
|
||||
* k3_ringacc_ring_reset - ring reset
|
||||
* @ring: pointer on Ring
|
||||
*
|
||||
* Resets ring internal state ((hw)occ, (hw)idx).
|
||||
*/
|
||||
void k3_ringacc_ring_reset(struct k3_ring *ring);
|
||||
/**
|
||||
* k3_ringacc_ring_reset - ring reset for DMA rings
|
||||
* @ring: pointer on Ring
|
||||
*
|
||||
* Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings
|
||||
* which are read by K3 UDMA, like TX or Free Host PD rings.
|
||||
*/
|
||||
void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_free - ring free
|
||||
* @ring: pointer on Ring
|
||||
*
|
||||
* Resets ring and free all alocated resources.
|
||||
*/
|
||||
int k3_ringacc_ring_free(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_get_ring_id - Get the Ring ID
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns the Ring ID
|
||||
*/
|
||||
u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_get_ring_irq_num - Get the irq number for the ring
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns the interrupt number which can be used to request the interrupt
|
||||
*/
|
||||
int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_cfg - ring configure
|
||||
* @ring: pointer on ring
|
||||
* @cfg: Ring configuration parameters (see &struct k3_ring_cfg)
|
||||
*
|
||||
* Configures ring, including ring memory allocation.
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_get_size - get ring size
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns ring size in number of elements.
|
||||
*/
|
||||
u32 k3_ringacc_ring_get_size(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_get_free - get free elements
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns number of free elements in the ring.
|
||||
*/
|
||||
u32 k3_ringacc_ring_get_free(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_get_occ - get ring occupancy
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns total number of valid entries on the ring
|
||||
*/
|
||||
u32 k3_ringacc_ring_get_occ(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_is_full - checks if ring is full
|
||||
* @ring: pointer on ring
|
||||
*
|
||||
* Returns true if the ring is full
|
||||
*/
|
||||
u32 k3_ringacc_ring_is_full(struct k3_ring *ring);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_push - push element to the ring tail
|
||||
* @ring: pointer on ring
|
||||
* @elem: pointer on ring element buffer
|
||||
*
|
||||
* Push one ring element to the ring tail. Size of the ring element is
|
||||
* determined by ring configuration &struct k3_ring_cfg elm_size.
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
int k3_ringacc_ring_push(struct k3_ring *ring, void *elem);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_pop - pop element from the ring head
|
||||
* @ring: pointer on ring
|
||||
* @elem: pointer on ring element buffer
|
||||
*
|
||||
* Push one ring element from the ring head. Size of the ring element is
|
||||
* determined by ring configuration &struct k3_ring_cfg elm_size..
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
*/
|
||||
int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_push_head - push element to the ring head
|
||||
* @ring: pointer on ring
|
||||
* @elem: pointer on ring element buffer
|
||||
*
|
||||
* Push one ring element to the ring head. Size of the ring element is
|
||||
* determined by ring configuration &struct k3_ring_cfg elm_size.
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
|
||||
*/
|
||||
int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem);
|
||||
|
||||
/**
|
||||
* k3_ringacc_ring_pop_tail - pop element from the ring tail
|
||||
* @ring: pointer on ring
|
||||
* @elem: pointer on ring element buffer
|
||||
*
|
||||
* Push one ring element from the ring tail. Size of the ring element is
|
||||
* determined by ring configuration &struct k3_ring_cfg elm_size.
|
||||
*
|
||||
* Returns 0 on success, errno otherwise.
|
||||
* Not Supported by ring modes: K3_RINGACC_RING_MODE_RING
|
||||
*/
|
||||
int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem);
|
||||
|
||||
u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring);
|
||||
|
||||
/* DMA ring support */
|
||||
struct ti_sci_handle;
|
||||
|
||||
/**
|
||||
* struct struct k3_ringacc_init_data - Initialization data for DMA rings
|
||||
*/
|
||||
struct k3_ringacc_init_data {
|
||||
const struct ti_sci_handle *tisci;
|
||||
u32 tisci_dev_id;
|
||||
u32 num_rings;
|
||||
};
|
||||
|
||||
struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
|
||||
struct k3_ringacc_init_data *data);
|
||||
|
||||
#endif /* __SOC_TI_K3_RINGACC_API_H_ */
|
||||
@@ -0,0 +1,185 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated
|
||||
* Authors: Sandeep Nair <sandeep_n@ti.com
|
||||
* Cyril Chemparathy <cyril@ti.com
|
||||
Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
|
||||
#define __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
/*
|
||||
* PKTDMA descriptor manipulation macros for host packet descriptor
|
||||
*/
|
||||
#define MASK(x) (BIT(x) - 1)
|
||||
#define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22)
|
||||
#define KNAV_DMA_DESC_PKT_LEN_SHIFT 0
|
||||
#define KNAV_DMA_DESC_PS_INFO_IN_SOP BIT(22)
|
||||
#define KNAV_DMA_DESC_PS_INFO_IN_DESC 0
|
||||
#define KNAV_DMA_DESC_TAG_MASK MASK(8)
|
||||
#define KNAV_DMA_DESC_SAG_HI_SHIFT 24
|
||||
#define KNAV_DMA_DESC_STAG_LO_SHIFT 16
|
||||
#define KNAV_DMA_DESC_DTAG_HI_SHIFT 8
|
||||
#define KNAV_DMA_DESC_DTAG_LO_SHIFT 0
|
||||
#define KNAV_DMA_DESC_HAS_EPIB BIT(31)
|
||||
#define KNAV_DMA_DESC_NO_EPIB 0
|
||||
#define KNAV_DMA_DESC_PSLEN_SHIFT 24
|
||||
#define KNAV_DMA_DESC_PSLEN_MASK MASK(6)
|
||||
#define KNAV_DMA_DESC_ERR_FLAG_SHIFT 20
|
||||
#define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4)
|
||||
#define KNAV_DMA_DESC_PSFLAG_SHIFT 16
|
||||
#define KNAV_DMA_DESC_PSFLAG_MASK MASK(4)
|
||||
#define KNAV_DMA_DESC_RETQ_SHIFT 0
|
||||
#define KNAV_DMA_DESC_RETQ_MASK MASK(14)
|
||||
#define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22)
|
||||
#define KNAV_DMA_DESC_EFLAGS_MASK MASK(4)
|
||||
#define KNAV_DMA_DESC_EFLAGS_SHIFT 20
|
||||
|
||||
#define KNAV_DMA_NUM_EPIB_WORDS 4
|
||||
#define KNAV_DMA_NUM_PS_WORDS 16
|
||||
#define KNAV_DMA_NUM_SW_DATA_WORDS 4
|
||||
#define KNAV_DMA_FDQ_PER_CHAN 4
|
||||
|
||||
/* Tx channel scheduling priority */
|
||||
enum knav_dma_tx_priority {
|
||||
DMA_PRIO_HIGH = 0,
|
||||
DMA_PRIO_MED_H,
|
||||
DMA_PRIO_MED_L,
|
||||
DMA_PRIO_LOW
|
||||
};
|
||||
|
||||
/* Rx channel error handling mode during buffer starvation */
|
||||
enum knav_dma_rx_err_mode {
|
||||
DMA_DROP = 0,
|
||||
DMA_RETRY
|
||||
};
|
||||
|
||||
/* Rx flow size threshold configuration */
|
||||
enum knav_dma_rx_thresholds {
|
||||
DMA_THRESH_NONE = 0,
|
||||
DMA_THRESH_0 = 1,
|
||||
DMA_THRESH_0_1 = 3,
|
||||
DMA_THRESH_0_1_2 = 7
|
||||
};
|
||||
|
||||
/* Descriptor type */
|
||||
enum knav_dma_desc_type {
|
||||
DMA_DESC_HOST = 0,
|
||||
DMA_DESC_MONOLITHIC = 2
|
||||
};
|
||||
|
||||
/**
|
||||
* struct knav_dma_tx_cfg: Tx channel configuration
|
||||
* @filt_einfo: Filter extended packet info
|
||||
* @filt_pswords: Filter PS words present
|
||||
* @knav_dma_tx_priority: Tx channel scheduling priority
|
||||
*/
|
||||
struct knav_dma_tx_cfg {
|
||||
bool filt_einfo;
|
||||
bool filt_pswords;
|
||||
enum knav_dma_tx_priority priority;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct knav_dma_rx_cfg: Rx flow configuration
|
||||
* @einfo_present: Extended packet info present
|
||||
* @psinfo_present: PS words present
|
||||
* @knav_dma_rx_err_mode: Error during buffer starvation
|
||||
* @knav_dma_desc_type: Host or Monolithic desc
|
||||
* @psinfo_at_sop: PS word located at start of packet
|
||||
* @sop_offset: Start of packet offset
|
||||
* @dst_q: Destination queue for a given flow
|
||||
* @thresh: Rx flow size threshold
|
||||
* @fdq[]: Free desc Queue array
|
||||
* @sz_thresh0: RX packet size threshold 0
|
||||
* @sz_thresh1: RX packet size threshold 1
|
||||
* @sz_thresh2: RX packet size threshold 2
|
||||
*/
|
||||
struct knav_dma_rx_cfg {
|
||||
bool einfo_present;
|
||||
bool psinfo_present;
|
||||
enum knav_dma_rx_err_mode err_mode;
|
||||
enum knav_dma_desc_type desc_type;
|
||||
bool psinfo_at_sop;
|
||||
unsigned int sop_offset;
|
||||
unsigned int dst_q;
|
||||
enum knav_dma_rx_thresholds thresh;
|
||||
unsigned int fdq[KNAV_DMA_FDQ_PER_CHAN];
|
||||
unsigned int sz_thresh0;
|
||||
unsigned int sz_thresh1;
|
||||
unsigned int sz_thresh2;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct knav_dma_cfg: Pktdma channel configuration
|
||||
* @sl_cfg: Slave configuration
|
||||
* @tx: Tx channel configuration
|
||||
* @rx: Rx flow configuration
|
||||
*/
|
||||
struct knav_dma_cfg {
|
||||
enum dma_transfer_direction direction;
|
||||
union {
|
||||
struct knav_dma_tx_cfg tx;
|
||||
struct knav_dma_rx_cfg rx;
|
||||
} u;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct knav_dma_desc: Host packet descriptor layout
|
||||
* @desc_info: Descriptor information like id, type, length
|
||||
* @tag_info: Flow tag info written in during RX
|
||||
* @packet_info: Queue Manager, policy, flags etc
|
||||
* @buff_len: Buffer length in bytes
|
||||
* @buff: Buffer pointer
|
||||
* @next_desc: For chaining the descriptors
|
||||
* @orig_len: length since 'buff_len' can be overwritten
|
||||
* @orig_buff: buff pointer since 'buff' can be overwritten
|
||||
* @epib: Extended packet info block
|
||||
* @psdata: Protocol specific
|
||||
* @sw_data: Software private data not touched by h/w
|
||||
*/
|
||||
struct knav_dma_desc {
|
||||
__le32 desc_info;
|
||||
__le32 tag_info;
|
||||
__le32 packet_info;
|
||||
__le32 buff_len;
|
||||
__le32 buff;
|
||||
__le32 next_desc;
|
||||
__le32 orig_len;
|
||||
__le32 orig_buff;
|
||||
__le32 epib[KNAV_DMA_NUM_EPIB_WORDS];
|
||||
__le32 psdata[KNAV_DMA_NUM_PS_WORDS];
|
||||
u32 sw_data[KNAV_DMA_NUM_SW_DATA_WORDS];
|
||||
} ____cacheline_aligned;
|
||||
|
||||
#if IS_ENABLED(CONFIG_KEYSTONE_NAVIGATOR_DMA)
|
||||
void *knav_dma_open_channel(struct device *dev, const char *name,
|
||||
struct knav_dma_cfg *config);
|
||||
void knav_dma_close_channel(void *channel);
|
||||
int knav_dma_get_flow(void *channel);
|
||||
bool knav_dma_device_ready(void);
|
||||
#else
|
||||
static inline void *knav_dma_open_channel(struct device *dev, const char *name,
|
||||
struct knav_dma_cfg *config)
|
||||
{
|
||||
return (void *) NULL;
|
||||
}
|
||||
static inline void knav_dma_close_channel(void *channel)
|
||||
{}
|
||||
|
||||
static inline int knav_dma_get_flow(void *channel)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline bool knav_dma_device_ready(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__ */
|
||||
@@ -0,0 +1,83 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Keystone Navigator Queue Management Sub-System header
|
||||
*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
|
||||
* Author: Sandeep Nair <sandeep_n@ti.com>
|
||||
* Cyril Chemparathy <cyril@ti.com>
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TI_KNAV_QMSS_H__
|
||||
#define __SOC_TI_KNAV_QMSS_H__
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/fcntl.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
/* queue types */
|
||||
#define KNAV_QUEUE_QPEND ((unsigned)-2) /* interruptible qpend queue */
|
||||
#define KNAV_QUEUE_ACC ((unsigned)-3) /* Accumulated queue */
|
||||
#define KNAV_QUEUE_GP ((unsigned)-4) /* General purpose queue */
|
||||
|
||||
/* queue flags */
|
||||
#define KNAV_QUEUE_SHARED 0x0001 /* Queue can be shared */
|
||||
|
||||
/**
|
||||
* enum knav_queue_ctrl_cmd - queue operations.
|
||||
* @KNAV_QUEUE_GET_ID: Get the ID number for an open queue
|
||||
* @KNAV_QUEUE_FLUSH: forcibly empty a queue if possible
|
||||
* @KNAV_QUEUE_SET_NOTIFIER: Set a notifier callback to a queue handle.
|
||||
* @KNAV_QUEUE_ENABLE_NOTIFY: Enable notifier callback for a queue handle.
|
||||
* @KNAV_QUEUE_DISABLE_NOTIFY: Disable notifier callback for a queue handle.
|
||||
* @KNAV_QUEUE_GET_COUNT: Get number of queues.
|
||||
*/
|
||||
enum knav_queue_ctrl_cmd {
|
||||
KNAV_QUEUE_GET_ID,
|
||||
KNAV_QUEUE_FLUSH,
|
||||
KNAV_QUEUE_SET_NOTIFIER,
|
||||
KNAV_QUEUE_ENABLE_NOTIFY,
|
||||
KNAV_QUEUE_DISABLE_NOTIFY,
|
||||
KNAV_QUEUE_GET_COUNT
|
||||
};
|
||||
|
||||
/* Queue notifier callback prototype */
|
||||
typedef void (*knav_queue_notify_fn)(void *arg);
|
||||
|
||||
/**
|
||||
* struct knav_queue_notify_config: Notifier configuration
|
||||
* @fn: Notifier function
|
||||
* @fn_arg: Notifier function arguments
|
||||
*/
|
||||
struct knav_queue_notify_config {
|
||||
knav_queue_notify_fn fn;
|
||||
void *fn_arg;
|
||||
};
|
||||
|
||||
void *knav_queue_open(const char *name, unsigned id,
|
||||
unsigned flags);
|
||||
void knav_queue_close(void *qhandle);
|
||||
int knav_queue_device_control(void *qhandle,
|
||||
enum knav_queue_ctrl_cmd cmd,
|
||||
unsigned long arg);
|
||||
dma_addr_t knav_queue_pop(void *qhandle, unsigned *size);
|
||||
int knav_queue_push(void *qhandle, dma_addr_t dma,
|
||||
unsigned size, unsigned flags);
|
||||
|
||||
void *knav_pool_create(const char *name,
|
||||
int num_desc, int region_id);
|
||||
void knav_pool_destroy(void *ph);
|
||||
int knav_pool_count(void *ph);
|
||||
void *knav_pool_desc_get(void *ph);
|
||||
void knav_pool_desc_put(void *ph, void *desc);
|
||||
int knav_pool_desc_map(void *ph, void *desc, unsigned size,
|
||||
dma_addr_t *dma, unsigned *dma_sz);
|
||||
void *knav_pool_desc_unmap(void *ph, dma_addr_t dma, unsigned dma_sz);
|
||||
dma_addr_t knav_pool_desc_virt_to_dma(void *ph, void *virt);
|
||||
void *knav_pool_desc_dma_to_virt(void *ph, dma_addr_t dma);
|
||||
bool knav_qmss_device_ready(void);
|
||||
|
||||
#endif /* __SOC_TI_KNAV_QMSS_H__ */
|
||||
@@ -0,0 +1,143 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef __ASM_ARCH_OMAP_IO_H
|
||||
#define __ASM_ARCH_OMAP_IO_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1
|
||||
/*
|
||||
* NOTE: Please use ioremap + __raw_read/write where possible instead of these
|
||||
*/
|
||||
extern u8 omap_readb(u32 pa);
|
||||
extern u16 omap_readw(u32 pa);
|
||||
extern u32 omap_readl(u32 pa);
|
||||
extern void omap_writeb(u8 v, u32 pa);
|
||||
extern void omap_writew(u16 v, u32 pa);
|
||||
extern void omap_writel(u32 v, u32 pa);
|
||||
#elif defined(CONFIG_COMPILE_TEST)
|
||||
static inline u8 omap_readb(u32 pa) { return 0; }
|
||||
static inline u16 omap_readw(u32 pa) { return 0; }
|
||||
static inline u32 omap_readl(u32 pa) { return 0; }
|
||||
static inline void omap_writeb(u8 v, u32 pa) { }
|
||||
static inline void omap_writew(u16 v, u32 pa) { }
|
||||
static inline void omap_writel(u32 v, u32 pa) { }
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* System control registers
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define MOD_CONF_CTRL_0 0xfffe1080
|
||||
#define MOD_CONF_CTRL_1 0xfffe1110
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* UPLD
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
#define ULPD_REG_BASE (0xfffe0800)
|
||||
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
|
||||
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
|
||||
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
|
||||
# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
|
||||
# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
|
||||
#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
|
||||
# define SOFT_UDC_REQ (1 << 4)
|
||||
# define SOFT_USB_CLK_REQ (1 << 3)
|
||||
# define SOFT_DPLL_REQ (1 << 0)
|
||||
#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
|
||||
#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
|
||||
#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
|
||||
#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
|
||||
#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
|
||||
# define DIS_MMC2_DPLL_REQ (1 << 11)
|
||||
# define DIS_MMC1_DPLL_REQ (1 << 10)
|
||||
# define DIS_UART3_DPLL_REQ (1 << 9)
|
||||
# define DIS_UART2_DPLL_REQ (1 << 8)
|
||||
# define DIS_UART1_DPLL_REQ (1 << 7)
|
||||
# define DIS_USB_HOST_DPLL_REQ (1 << 6)
|
||||
#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
|
||||
#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Clocks
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CLKGEN_REG_BASE (0xfffece00)
|
||||
#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
|
||||
#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
|
||||
#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
|
||||
#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
|
||||
#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
|
||||
#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
|
||||
#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
|
||||
#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
|
||||
|
||||
#define CK_RATEF 1
|
||||
#define CK_IDLEF 2
|
||||
#define CK_ENABLEF 4
|
||||
#define CK_SELECTF 8
|
||||
#define SETARM_IDLE_SHIFT
|
||||
|
||||
/* DPLL control registers */
|
||||
#define DPLL_CTL (0xfffecf00)
|
||||
|
||||
/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
|
||||
#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
|
||||
#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
|
||||
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
|
||||
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
|
||||
#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Pulse-Width Light
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP_PWL_BASE 0xfffb5800
|
||||
#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
|
||||
#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Pin multiplexing registers
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define FUNC_MUX_CTRL_0 0xfffe1000
|
||||
#define FUNC_MUX_CTRL_1 0xfffe1004
|
||||
#define FUNC_MUX_CTRL_2 0xfffe1008
|
||||
#define COMP_MODE_CTRL_0 0xfffe100c
|
||||
#define FUNC_MUX_CTRL_3 0xfffe1010
|
||||
#define FUNC_MUX_CTRL_4 0xfffe1014
|
||||
#define FUNC_MUX_CTRL_5 0xfffe1018
|
||||
#define FUNC_MUX_CTRL_6 0xfffe101C
|
||||
#define FUNC_MUX_CTRL_7 0xfffe1020
|
||||
#define FUNC_MUX_CTRL_8 0xfffe1024
|
||||
#define FUNC_MUX_CTRL_9 0xfffe1028
|
||||
#define FUNC_MUX_CTRL_A 0xfffe102C
|
||||
#define FUNC_MUX_CTRL_B 0xfffe1030
|
||||
#define FUNC_MUX_CTRL_C 0xfffe1034
|
||||
#define FUNC_MUX_CTRL_D 0xfffe1038
|
||||
#define PULL_DWN_CTRL_0 0xfffe1040
|
||||
#define PULL_DWN_CTRL_1 0xfffe1044
|
||||
#define PULL_DWN_CTRL_2 0xfffe1048
|
||||
#define PULL_DWN_CTRL_3 0xfffe104c
|
||||
#define PULL_DWN_CTRL_4 0xfffe10ac
|
||||
|
||||
/* OMAP-1610 specific multiplexing registers */
|
||||
#define FUNC_MUX_CTRL_E 0xfffe1090
|
||||
#define FUNC_MUX_CTRL_F 0xfffe1094
|
||||
#define FUNC_MUX_CTRL_10 0xfffe1098
|
||||
#define FUNC_MUX_CTRL_11 0xfffe109c
|
||||
#define FUNC_MUX_CTRL_12 0xfffe10a0
|
||||
#define PU_PD_SEL_0 0xfffe10b4
|
||||
#define PU_PD_SEL_1 0xfffe10b8
|
||||
#define PU_PD_SEL_2 0xfffe10bc
|
||||
#define PU_PD_SEL_3 0xfffe10c0
|
||||
#define PU_PD_SEL_4 0xfffe10c4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,311 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
#ifndef __SOC_TI_OMAP1_MUX_H
|
||||
#define __SOC_TI_OMAP1_MUX_H
|
||||
/*
|
||||
* This should not really be a global header, it reflects the
|
||||
* traditional way that omap1 does pin muxing without the
|
||||
* pinctrl subsystem.
|
||||
*/
|
||||
|
||||
enum omap7xx_index {
|
||||
/* OMAP 730 keyboard */
|
||||
E2_7XX_KBR0,
|
||||
J7_7XX_KBR1,
|
||||
E1_7XX_KBR2,
|
||||
F3_7XX_KBR3,
|
||||
D2_7XX_KBR4,
|
||||
C2_7XX_KBC0,
|
||||
D3_7XX_KBC1,
|
||||
E4_7XX_KBC2,
|
||||
F4_7XX_KBC3,
|
||||
E3_7XX_KBC4,
|
||||
|
||||
/* USB */
|
||||
AA17_7XX_USB_DM,
|
||||
W16_7XX_USB_PU_EN,
|
||||
W17_7XX_USB_VBUSI,
|
||||
W18_7XX_USB_DMCK_OUT,
|
||||
W19_7XX_USB_DCRST,
|
||||
|
||||
/* MMC */
|
||||
MMC_7XX_CMD,
|
||||
MMC_7XX_CLK,
|
||||
MMC_7XX_DAT0,
|
||||
|
||||
/* I2C */
|
||||
I2C_7XX_SCL,
|
||||
I2C_7XX_SDA,
|
||||
|
||||
/* SPI */
|
||||
SPI_7XX_1,
|
||||
SPI_7XX_2,
|
||||
SPI_7XX_3,
|
||||
SPI_7XX_4,
|
||||
SPI_7XX_5,
|
||||
SPI_7XX_6,
|
||||
|
||||
/* UART */
|
||||
UART_7XX_1,
|
||||
UART_7XX_2,
|
||||
};
|
||||
|
||||
enum omap1xxx_index {
|
||||
/* UART1 (BT_UART_GATING)*/
|
||||
UART1_TX = 0,
|
||||
UART1_RTS,
|
||||
|
||||
/* UART2 (COM_UART_GATING)*/
|
||||
UART2_TX,
|
||||
UART2_RX,
|
||||
UART2_CTS,
|
||||
UART2_RTS,
|
||||
|
||||
/* UART3 (GIGA_UART_GATING) */
|
||||
UART3_TX,
|
||||
UART3_RX,
|
||||
UART3_CTS,
|
||||
UART3_RTS,
|
||||
UART3_CLKREQ,
|
||||
UART3_BCLK, /* 12MHz clock out */
|
||||
Y15_1610_UART3_RTS,
|
||||
|
||||
/* PWT & PWL */
|
||||
PWT,
|
||||
PWL,
|
||||
|
||||
/* USB master generic */
|
||||
R18_USB_VBUS,
|
||||
R18_1510_USB_GPIO0,
|
||||
W4_USB_PUEN,
|
||||
W4_USB_CLKO,
|
||||
W4_USB_HIGHZ,
|
||||
W4_GPIO58,
|
||||
|
||||
/* USB1 master */
|
||||
USB1_SUSP,
|
||||
USB1_SEO,
|
||||
W13_1610_USB1_SE0,
|
||||
USB1_TXEN,
|
||||
USB1_TXD,
|
||||
USB1_VP,
|
||||
USB1_VM,
|
||||
USB1_RCV,
|
||||
USB1_SPEED,
|
||||
R13_1610_USB1_SPEED,
|
||||
R13_1710_USB1_SE0,
|
||||
|
||||
/* USB2 master */
|
||||
USB2_SUSP,
|
||||
USB2_VP,
|
||||
USB2_TXEN,
|
||||
USB2_VM,
|
||||
USB2_RCV,
|
||||
USB2_SEO,
|
||||
USB2_TXD,
|
||||
|
||||
/* OMAP-1510 GPIO */
|
||||
R18_1510_GPIO0,
|
||||
R19_1510_GPIO1,
|
||||
M14_1510_GPIO2,
|
||||
|
||||
/* OMAP1610 GPIO */
|
||||
P18_1610_GPIO3,
|
||||
Y15_1610_GPIO17,
|
||||
|
||||
/* OMAP-1710 GPIO */
|
||||
R18_1710_GPIO0,
|
||||
V2_1710_GPIO10,
|
||||
N21_1710_GPIO14,
|
||||
W15_1710_GPIO40,
|
||||
|
||||
/* MPUIO */
|
||||
MPUIO2,
|
||||
N15_1610_MPUIO2,
|
||||
MPUIO4,
|
||||
MPUIO5,
|
||||
T20_1610_MPUIO5,
|
||||
W11_1610_MPUIO6,
|
||||
V10_1610_MPUIO7,
|
||||
W11_1610_MPUIO9,
|
||||
V10_1610_MPUIO10,
|
||||
W10_1610_MPUIO11,
|
||||
E20_1610_MPUIO13,
|
||||
U20_1610_MPUIO14,
|
||||
E19_1610_MPUIO15,
|
||||
|
||||
/* MCBSP2 */
|
||||
MCBSP2_CLKR,
|
||||
MCBSP2_CLKX,
|
||||
MCBSP2_DR,
|
||||
MCBSP2_DX,
|
||||
MCBSP2_FSR,
|
||||
MCBSP2_FSX,
|
||||
|
||||
/* MCBSP3 */
|
||||
MCBSP3_CLKX,
|
||||
|
||||
/* Misc ballouts */
|
||||
BALLOUT_V8_ARMIO3,
|
||||
N20_HDQ,
|
||||
|
||||
/* OMAP-1610 MMC2 */
|
||||
W8_1610_MMC2_DAT0,
|
||||
V8_1610_MMC2_DAT1,
|
||||
W15_1610_MMC2_DAT2,
|
||||
R10_1610_MMC2_DAT3,
|
||||
Y10_1610_MMC2_CLK,
|
||||
Y8_1610_MMC2_CMD,
|
||||
V9_1610_MMC2_CMDDIR,
|
||||
V5_1610_MMC2_DATDIR0,
|
||||
W19_1610_MMC2_DATDIR1,
|
||||
R18_1610_MMC2_CLKIN,
|
||||
|
||||
/* OMAP-1610 External Trace Interface */
|
||||
M19_1610_ETM_PSTAT0,
|
||||
L15_1610_ETM_PSTAT1,
|
||||
L18_1610_ETM_PSTAT2,
|
||||
L19_1610_ETM_D0,
|
||||
J19_1610_ETM_D6,
|
||||
J18_1610_ETM_D7,
|
||||
|
||||
/* OMAP16XX GPIO */
|
||||
P20_1610_GPIO4,
|
||||
V9_1610_GPIO7,
|
||||
W8_1610_GPIO9,
|
||||
N20_1610_GPIO11,
|
||||
N19_1610_GPIO13,
|
||||
P10_1610_GPIO22,
|
||||
V5_1610_GPIO24,
|
||||
AA20_1610_GPIO_41,
|
||||
W19_1610_GPIO48,
|
||||
M7_1610_GPIO62,
|
||||
V14_16XX_GPIO37,
|
||||
R9_16XX_GPIO18,
|
||||
L14_16XX_GPIO49,
|
||||
|
||||
/* OMAP-1610 uWire */
|
||||
V19_1610_UWIRE_SCLK,
|
||||
U18_1610_UWIRE_SDI,
|
||||
W21_1610_UWIRE_SDO,
|
||||
N14_1610_UWIRE_CS0,
|
||||
P15_1610_UWIRE_CS3,
|
||||
N15_1610_UWIRE_CS1,
|
||||
|
||||
/* OMAP-1610 SPI */
|
||||
U19_1610_SPIF_SCK,
|
||||
U18_1610_SPIF_DIN,
|
||||
P20_1610_SPIF_DIN,
|
||||
W21_1610_SPIF_DOUT,
|
||||
R18_1610_SPIF_DOUT,
|
||||
N14_1610_SPIF_CS0,
|
||||
N15_1610_SPIF_CS1,
|
||||
T19_1610_SPIF_CS2,
|
||||
P15_1610_SPIF_CS3,
|
||||
|
||||
/* OMAP-1610 Flash */
|
||||
L3_1610_FLASH_CS2B_OE,
|
||||
M8_1610_FLASH_CS2B_WE,
|
||||
|
||||
/* First MMC */
|
||||
MMC_CMD,
|
||||
MMC_DAT1,
|
||||
MMC_DAT2,
|
||||
MMC_DAT0,
|
||||
MMC_CLK,
|
||||
MMC_DAT3,
|
||||
|
||||
/* OMAP-1710 MMC CMDDIR and DATDIR0 */
|
||||
M15_1710_MMC_CLKI,
|
||||
P19_1710_MMC_CMDDIR,
|
||||
P20_1710_MMC_DATDIR0,
|
||||
|
||||
/* OMAP-1610 USB0 alternate pin configuration */
|
||||
W9_USB0_TXEN,
|
||||
AA9_USB0_VP,
|
||||
Y5_USB0_RCV,
|
||||
R9_USB0_VM,
|
||||
V6_USB0_TXD,
|
||||
W5_USB0_SE0,
|
||||
V9_USB0_SPEED,
|
||||
V9_USB0_SUSP,
|
||||
|
||||
/* USB2 */
|
||||
W9_USB2_TXEN,
|
||||
AA9_USB2_VP,
|
||||
Y5_USB2_RCV,
|
||||
R9_USB2_VM,
|
||||
V6_USB2_TXD,
|
||||
W5_USB2_SE0,
|
||||
|
||||
/* 16XX UART */
|
||||
R13_1610_UART1_TX,
|
||||
V14_16XX_UART1_RX,
|
||||
R14_1610_UART1_CTS,
|
||||
AA15_1610_UART1_RTS,
|
||||
R9_16XX_UART2_RX,
|
||||
L14_16XX_UART3_RX,
|
||||
|
||||
/* I2C OMAP-1610 */
|
||||
I2C_SCL,
|
||||
I2C_SDA,
|
||||
|
||||
/* Keypad */
|
||||
F18_1610_KBC0,
|
||||
D20_1610_KBC1,
|
||||
D19_1610_KBC2,
|
||||
E18_1610_KBC3,
|
||||
C21_1610_KBC4,
|
||||
G18_1610_KBR0,
|
||||
F19_1610_KBR1,
|
||||
H14_1610_KBR2,
|
||||
E20_1610_KBR3,
|
||||
E19_1610_KBR4,
|
||||
N19_1610_KBR5,
|
||||
|
||||
/* Power management */
|
||||
T20_1610_LOW_PWR,
|
||||
|
||||
/* MCLK Settings */
|
||||
V5_1710_MCLK_ON,
|
||||
V5_1710_MCLK_OFF,
|
||||
R10_1610_MCLK_ON,
|
||||
R10_1610_MCLK_OFF,
|
||||
|
||||
/* CompactFlash controller */
|
||||
P11_1610_CF_CD2,
|
||||
R11_1610_CF_IOIS16,
|
||||
V10_1610_CF_IREQ,
|
||||
W10_1610_CF_RESET,
|
||||
W11_1610_CF_CD1,
|
||||
|
||||
/* parallel camera */
|
||||
J15_1610_CAM_LCLK,
|
||||
J18_1610_CAM_D7,
|
||||
J19_1610_CAM_D6,
|
||||
J14_1610_CAM_D5,
|
||||
K18_1610_CAM_D4,
|
||||
K19_1610_CAM_D3,
|
||||
K15_1610_CAM_D2,
|
||||
K14_1610_CAM_D1,
|
||||
L19_1610_CAM_D0,
|
||||
L18_1610_CAM_VS,
|
||||
L15_1610_CAM_HS,
|
||||
M19_1610_CAM_RSTZ,
|
||||
Y15_1610_CAM_OUTCLK,
|
||||
|
||||
/* serial camera */
|
||||
H19_1610_CAM_EXCLK,
|
||||
Y12_1610_CCP_CLKP,
|
||||
W13_1610_CCP_CLKM,
|
||||
W14_1610_CCP_DATAP,
|
||||
Y14_1610_CCP_DATAM,
|
||||
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
extern int omap_cfg_reg(unsigned long reg_cfg);
|
||||
#else
|
||||
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,163 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* OMAP cpu type detection
|
||||
*
|
||||
* Copyright (C) 2004, 2008 Nokia Corporation
|
||||
*
|
||||
* Copyright (C) 2009-11 Texas Instruments.
|
||||
*
|
||||
* Written by Tony Lindgren <tony.lindgren@nokia.com>
|
||||
*
|
||||
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_OMAP_CPU_H
|
||||
#define __ASM_ARCH_OMAP_CPU_H
|
||||
|
||||
/*
|
||||
* Test if multicore OMAP support is needed
|
||||
*/
|
||||
#undef MULTI_OMAP1
|
||||
#undef OMAP_NAME
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
# ifdef OMAP_NAME
|
||||
# undef MULTI_OMAP1
|
||||
# define MULTI_OMAP1
|
||||
# else
|
||||
# define OMAP_NAME omap1510
|
||||
# endif
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
# ifdef OMAP_NAME
|
||||
# undef MULTI_OMAP1
|
||||
# define MULTI_OMAP1
|
||||
# else
|
||||
# define OMAP_NAME omap16xx
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* omap_rev bits:
|
||||
* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
|
||||
* CPU revision (See _REV_ defined in cpu.h) [15:08]
|
||||
* CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
|
||||
*/
|
||||
unsigned int omap_rev(void);
|
||||
|
||||
/*
|
||||
* Get the CPU revision for OMAP devices
|
||||
*/
|
||||
#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
|
||||
|
||||
/*
|
||||
* Macros to group OMAP into cpu classes.
|
||||
* These can be used in most places.
|
||||
* cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
|
||||
* cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
|
||||
*/
|
||||
#define GET_OMAP_CLASS (omap_rev() & 0xff)
|
||||
|
||||
#define IS_OMAP_CLASS(class, id) \
|
||||
static inline int is_omap ##class (void) \
|
||||
{ \
|
||||
return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
|
||||
}
|
||||
|
||||
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
|
||||
|
||||
#define IS_OMAP_SUBCLASS(subclass, id) \
|
||||
static inline int is_omap ##subclass (void) \
|
||||
{ \
|
||||
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
|
||||
}
|
||||
|
||||
IS_OMAP_CLASS(15xx, 0x15)
|
||||
IS_OMAP_CLASS(16xx, 0x16)
|
||||
|
||||
#define cpu_is_omap15xx() 0
|
||||
#define cpu_is_omap16xx() 0
|
||||
|
||||
#if defined(MULTI_OMAP1)
|
||||
# if defined(CONFIG_ARCH_OMAP15XX)
|
||||
# undef cpu_is_omap15xx
|
||||
# define cpu_is_omap15xx() is_omap15xx()
|
||||
# endif
|
||||
# if defined(CONFIG_ARCH_OMAP16XX)
|
||||
# undef cpu_is_omap16xx
|
||||
# define cpu_is_omap16xx() is_omap16xx()
|
||||
# endif
|
||||
#else
|
||||
# if defined(CONFIG_ARCH_OMAP15XX)
|
||||
# undef cpu_is_omap15xx
|
||||
# define cpu_is_omap15xx() 1
|
||||
# endif
|
||||
# if defined(CONFIG_ARCH_OMAP16XX)
|
||||
# undef cpu_is_omap16xx
|
||||
# define cpu_is_omap16xx() 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros to detect individual cpu types.
|
||||
* These are only rarely needed.
|
||||
* cpu_is_omap310(): True for OMAP310
|
||||
* cpu_is_omap1510(): True for OMAP1510
|
||||
* cpu_is_omap1610(): True for OMAP1610
|
||||
* cpu_is_omap1611(): True for OMAP1611
|
||||
* cpu_is_omap5912(): True for OMAP5912
|
||||
* cpu_is_omap1621(): True for OMAP1621
|
||||
* cpu_is_omap1710(): True for OMAP1710
|
||||
*/
|
||||
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
|
||||
|
||||
#define IS_OMAP_TYPE(type, id) \
|
||||
static inline int is_omap ##type (void) \
|
||||
{ \
|
||||
return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
|
||||
}
|
||||
|
||||
IS_OMAP_TYPE(310, 0x0310)
|
||||
IS_OMAP_TYPE(1510, 0x1510)
|
||||
IS_OMAP_TYPE(1610, 0x1610)
|
||||
IS_OMAP_TYPE(1611, 0x1611)
|
||||
IS_OMAP_TYPE(5912, 0x1611)
|
||||
IS_OMAP_TYPE(1621, 0x1621)
|
||||
IS_OMAP_TYPE(1710, 0x1710)
|
||||
|
||||
#define cpu_is_omap310() 0
|
||||
#define cpu_is_omap1510() 0
|
||||
#define cpu_is_omap1610() 0
|
||||
#define cpu_is_omap5912() 0
|
||||
#define cpu_is_omap1611() 0
|
||||
#define cpu_is_omap1621() 0
|
||||
#define cpu_is_omap1710() 0
|
||||
|
||||
#define cpu_class_is_omap1() 1
|
||||
|
||||
/*
|
||||
* Whether we have MULTI_OMAP1 or not, we still need to distinguish
|
||||
* between 310 vs. 1510 and 1611B/5912 vs. 1710.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP15XX)
|
||||
# undef cpu_is_omap310
|
||||
# undef cpu_is_omap1510
|
||||
# define cpu_is_omap310() is_omap310()
|
||||
# define cpu_is_omap1510() is_omap1510()
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP16XX)
|
||||
# undef cpu_is_omap1610
|
||||
# undef cpu_is_omap1611
|
||||
# undef cpu_is_omap5912
|
||||
# undef cpu_is_omap1621
|
||||
# undef cpu_is_omap1710
|
||||
# define cpu_is_omap1610() is_omap1610()
|
||||
# define cpu_is_omap1611() is_omap1611()
|
||||
# define cpu_is_omap5912() is_omap5912()
|
||||
# define cpu_is_omap1621() is_omap1621()
|
||||
# define cpu_is_omap1710() is_omap1710()
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,116 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __SOC_TI_OMAP1_USB
|
||||
#define __SOC_TI_OMAP1_USB
|
||||
/*
|
||||
* Constants in this file are used all over the place, in platform
|
||||
* code, as well as the udc, phy and ohci drivers.
|
||||
* This is not a great design, but unlikely to get fixed after
|
||||
* such a long time. Don't do this elsewhere.
|
||||
*/
|
||||
|
||||
#define OMAP1_OTG_BASE 0xfffb0400
|
||||
#define OMAP1_UDC_BASE 0xfffb4000
|
||||
|
||||
#define OMAP2_UDC_BASE 0x4805e200
|
||||
#define OMAP2_OTG_BASE 0x4805e300
|
||||
#define OTG_BASE OMAP1_OTG_BASE
|
||||
#define UDC_BASE OMAP1_UDC_BASE
|
||||
|
||||
/*
|
||||
* OTG and transceiver registers, for OMAPs starting with ARM926
|
||||
*/
|
||||
#define OTG_REV (OTG_BASE + 0x00)
|
||||
#define OTG_SYSCON_1 (OTG_BASE + 0x04)
|
||||
# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
|
||||
# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
|
||||
# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
|
||||
# define OTG_IDLE_EN (1 << 15)
|
||||
# define HST_IDLE_EN (1 << 14)
|
||||
# define DEV_IDLE_EN (1 << 13)
|
||||
# define OTG_RESET_DONE (1 << 2)
|
||||
# define OTG_SOFT_RESET (1 << 1)
|
||||
#define OTG_SYSCON_2 (OTG_BASE + 0x08)
|
||||
# define OTG_EN (1 << 31)
|
||||
# define USBX_SYNCHRO (1 << 30)
|
||||
# define OTG_MST16 (1 << 29)
|
||||
# define SRP_GPDATA (1 << 28)
|
||||
# define SRP_GPDVBUS (1 << 27)
|
||||
# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
|
||||
# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
|
||||
# define B_ASE_BRST(w) (((w)>>16)&0x07)
|
||||
# define SRP_DPW (1 << 14)
|
||||
# define SRP_DATA (1 << 13)
|
||||
# define SRP_VBUS (1 << 12)
|
||||
# define OTG_PADEN (1 << 10)
|
||||
# define HMC_PADEN (1 << 9)
|
||||
# define UHOST_EN (1 << 8)
|
||||
# define HMC_TLLSPEED (1 << 7)
|
||||
# define HMC_TLLATTACH (1 << 6)
|
||||
# define OTG_HMC(w) (((w)>>0)&0x3f)
|
||||
#define OTG_CTRL (OTG_BASE + 0x0c)
|
||||
# define OTG_USB2_EN (1 << 29)
|
||||
# define OTG_USB2_DP (1 << 28)
|
||||
# define OTG_USB2_DM (1 << 27)
|
||||
# define OTG_USB1_EN (1 << 26)
|
||||
# define OTG_USB1_DP (1 << 25)
|
||||
# define OTG_USB1_DM (1 << 24)
|
||||
# define OTG_USB0_EN (1 << 23)
|
||||
# define OTG_USB0_DP (1 << 22)
|
||||
# define OTG_USB0_DM (1 << 21)
|
||||
# define OTG_ASESSVLD (1 << 20)
|
||||
# define OTG_BSESSEND (1 << 19)
|
||||
# define OTG_BSESSVLD (1 << 18)
|
||||
# define OTG_VBUSVLD (1 << 17)
|
||||
# define OTG_ID (1 << 16)
|
||||
# define OTG_DRIVER_SEL (1 << 15)
|
||||
# define OTG_A_SETB_HNPEN (1 << 12)
|
||||
# define OTG_A_BUSREQ (1 << 11)
|
||||
# define OTG_B_HNPEN (1 << 9)
|
||||
# define OTG_B_BUSREQ (1 << 8)
|
||||
# define OTG_BUSDROP (1 << 7)
|
||||
# define OTG_PULLDOWN (1 << 5)
|
||||
# define OTG_PULLUP (1 << 4)
|
||||
# define OTG_DRV_VBUS (1 << 3)
|
||||
# define OTG_PD_VBUS (1 << 2)
|
||||
# define OTG_PU_VBUS (1 << 1)
|
||||
# define OTG_PU_ID (1 << 0)
|
||||
#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
|
||||
# define DRIVER_SWITCH (1 << 15)
|
||||
# define A_VBUS_ERR (1 << 13)
|
||||
# define A_REQ_TMROUT (1 << 12)
|
||||
# define A_SRP_DETECT (1 << 11)
|
||||
# define B_HNP_FAIL (1 << 10)
|
||||
# define B_SRP_TMROUT (1 << 9)
|
||||
# define B_SRP_DONE (1 << 8)
|
||||
# define B_SRP_STARTED (1 << 7)
|
||||
# define OPRT_CHG (1 << 0)
|
||||
#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
|
||||
// same bits as in IRQ_EN
|
||||
#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
|
||||
# define OTGVPD (1 << 14)
|
||||
# define OTGVPU (1 << 13)
|
||||
# define OTGPUID (1 << 12)
|
||||
# define USB2VDR (1 << 10)
|
||||
# define USB2PDEN (1 << 9)
|
||||
# define USB2PUEN (1 << 8)
|
||||
# define USB1VDR (1 << 6)
|
||||
# define USB1PDEN (1 << 5)
|
||||
# define USB1PUEN (1 << 4)
|
||||
# define USB0VDR (1 << 2)
|
||||
# define USB0PDEN (1 << 1)
|
||||
# define USB0PUEN (1 << 0)
|
||||
#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
|
||||
#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
/* OMAP1 */
|
||||
#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
|
||||
# define CONF_USB2_UNI_R (1 << 8)
|
||||
# define CONF_USB1_UNI_R (1 << 7)
|
||||
# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
|
||||
# define CONF_USB0_ISOLATE_R (1 << 3)
|
||||
# define CONF_USB_PWRDN_DM_R (1 << 2)
|
||||
# define CONF_USB_PWRDN_DP_R (1 << 1)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Texas Instruments' Message Manager
|
||||
*
|
||||
* Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Nishanth Menon
|
||||
*/
|
||||
|
||||
#ifndef TI_MSGMGR_H
|
||||
#define TI_MSGMGR_H
|
||||
|
||||
struct mbox_chan;
|
||||
|
||||
/**
|
||||
* struct ti_msgmgr_message - Message Manager structure
|
||||
* @len: Length of data in the Buffer
|
||||
* @buf: Buffer pointer
|
||||
* @chan_rx: Expected channel for response, must be provided to use polled rx
|
||||
* @timeout_rx_ms: Timeout value to use if polling for response
|
||||
*
|
||||
* This is the structure for data used in mbox_send_message
|
||||
* the length of data buffer used depends on the SoC integration
|
||||
* parameters - each message may be 64, 128 bytes long depending
|
||||
* on SoC. Client is supposed to be aware of this.
|
||||
*/
|
||||
struct ti_msgmgr_message {
|
||||
size_t len;
|
||||
u8 *buf;
|
||||
struct mbox_chan *chan_rx;
|
||||
int timeout_rx_ms;
|
||||
};
|
||||
|
||||
#endif /* TI_MSGMGR_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Texas Instruments' K3 TI SCI INTA MSI helper
|
||||
*
|
||||
* Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Lokesh Vutla <lokeshvutla@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
|
||||
#define __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
|
||||
|
||||
#include <linux/msi.h>
|
||||
#include <linux/soc/ti/ti_sci_protocol.h>
|
||||
|
||||
struct irq_domain
|
||||
*ti_sci_inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
|
||||
struct msi_domain_info *info,
|
||||
struct irq_domain *parent);
|
||||
int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev,
|
||||
struct ti_sci_resource *res);
|
||||
#endif /* __INCLUDE_LINUX_IRQCHIP_TI_SCI_INTA_H */
|
||||
@@ -0,0 +1,684 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Texas Instruments System Control Interface Protocol
|
||||
*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Nishanth Menon
|
||||
*/
|
||||
|
||||
#ifndef __TISCI_PROTOCOL_H
|
||||
#define __TISCI_PROTOCOL_H
|
||||
|
||||
/**
|
||||
* struct ti_sci_version_info - version information structure
|
||||
* @abi_major: Major ABI version. Change here implies risk of backward
|
||||
* compatibility break.
|
||||
* @abi_minor: Minor ABI version. Change here implies new feature addition,
|
||||
* or compatible change in ABI.
|
||||
* @firmware_revision: Firmware revision (not usually used).
|
||||
* @firmware_description: Firmware description (not usually used).
|
||||
*/
|
||||
struct ti_sci_version_info {
|
||||
u8 abi_major;
|
||||
u8 abi_minor;
|
||||
u16 firmware_revision;
|
||||
char firmware_description[32];
|
||||
};
|
||||
|
||||
struct ti_sci_handle;
|
||||
|
||||
/**
|
||||
* struct ti_sci_core_ops - SoC Core Operations
|
||||
* @reboot_device: Reboot the SoC
|
||||
* Returns 0 for successful request(ideally should never return),
|
||||
* else returns corresponding error value.
|
||||
*/
|
||||
struct ti_sci_core_ops {
|
||||
int (*reboot_device)(const struct ti_sci_handle *handle);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_dev_ops - Device control operations
|
||||
* @get_device: Command to request for device managed by TISCI
|
||||
* Returns 0 for successful exclusive request, else returns
|
||||
* corresponding error message.
|
||||
* @idle_device: Command to idle a device managed by TISCI
|
||||
* Returns 0 for successful exclusive request, else returns
|
||||
* corresponding error message.
|
||||
* @put_device: Command to release a device managed by TISCI
|
||||
* Returns 0 for successful release, else returns corresponding
|
||||
* error message.
|
||||
* @is_valid: Check if the device ID is a valid ID.
|
||||
* Returns 0 if the ID is valid, else returns corresponding error.
|
||||
* @get_context_loss_count: Command to retrieve context loss counter - this
|
||||
* increments every time the device looses context. Overflow
|
||||
* is possible.
|
||||
* - count: pointer to u32 which will retrieve counter
|
||||
* Returns 0 for successful information request and count has
|
||||
* proper data, else returns corresponding error message.
|
||||
* @is_idle: Reports back about device idle state
|
||||
* - req_state: Returns requested idle state
|
||||
* Returns 0 for successful information request and req_state and
|
||||
* current_state has proper data, else returns corresponding error
|
||||
* message.
|
||||
* @is_stop: Reports back about device stop state
|
||||
* - req_state: Returns requested stop state
|
||||
* - current_state: Returns current stop state
|
||||
* Returns 0 for successful information request and req_state and
|
||||
* current_state has proper data, else returns corresponding error
|
||||
* message.
|
||||
* @is_on: Reports back about device ON(or active) state
|
||||
* - req_state: Returns requested ON state
|
||||
* - current_state: Returns current ON state
|
||||
* Returns 0 for successful information request and req_state and
|
||||
* current_state has proper data, else returns corresponding error
|
||||
* message.
|
||||
* @is_transitioning: Reports back if the device is in the middle of transition
|
||||
* of state.
|
||||
* -current_state: Returns 'true' if currently transitioning.
|
||||
* @set_device_resets: Command to configure resets for device managed by TISCI.
|
||||
* -reset_state: Device specific reset bit field
|
||||
* Returns 0 for successful request, else returns
|
||||
* corresponding error message.
|
||||
* @get_device_resets: Command to read state of resets for device managed
|
||||
* by TISCI.
|
||||
* -reset_state: pointer to u32 which will retrieve resets
|
||||
* Returns 0 for successful request, else returns
|
||||
* corresponding error message.
|
||||
*
|
||||
* NOTE: for all these functions, the following parameters are generic in
|
||||
* nature:
|
||||
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
|
||||
* -id: Device Identifier
|
||||
*
|
||||
* Request for the device - NOTE: the client MUST maintain integrity of
|
||||
* usage count by balancing get_device with put_device. No refcounting is
|
||||
* managed by driver for that purpose.
|
||||
*/
|
||||
struct ti_sci_dev_ops {
|
||||
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
|
||||
int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
|
||||
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
|
||||
int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
|
||||
u32 id);
|
||||
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
|
||||
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
|
||||
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
|
||||
u32 id, u32 *count);
|
||||
int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
|
||||
bool *requested_state);
|
||||
int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
|
||||
bool *req_state, bool *current_state);
|
||||
int (*is_on)(const struct ti_sci_handle *handle, u32 id,
|
||||
bool *req_state, bool *current_state);
|
||||
int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
|
||||
bool *current_state);
|
||||
int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
|
||||
u32 reset_state);
|
||||
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
|
||||
u32 *reset_state);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_clk_ops - Clock control operations
|
||||
* @get_clock: Request for activation of clock and manage by processor
|
||||
* - needs_ssc: 'true' if Spread Spectrum clock is desired.
|
||||
* - can_change_freq: 'true' if frequency change is desired.
|
||||
* - enable_input_term: 'true' if input termination is desired.
|
||||
* @idle_clock: Request for Idling a clock managed by processor
|
||||
* @put_clock: Release the clock to be auto managed by TISCI
|
||||
* @is_auto: Is the clock being auto managed
|
||||
* - req_state: state indicating if the clock is auto managed
|
||||
* @is_on: Is the clock ON
|
||||
* - req_state: if the clock is requested to be forced ON
|
||||
* - current_state: if the clock is currently ON
|
||||
* @is_off: Is the clock OFF
|
||||
* - req_state: if the clock is requested to be forced OFF
|
||||
* - current_state: if the clock is currently Gated
|
||||
* @set_parent: Set the clock source of a specific device clock
|
||||
* - parent_id: Parent clock identifier to set.
|
||||
* @get_parent: Get the current clock source of a specific device clock
|
||||
* - parent_id: Parent clock identifier which is the parent.
|
||||
* @get_num_parents: Get the number of parents of the current clock source
|
||||
* - num_parents: returns the number of parent clocks.
|
||||
* @get_best_match_freq: Find a best matching frequency for a frequency
|
||||
* range.
|
||||
* - match_freq: Best matching frequency in Hz.
|
||||
* @set_freq: Set the Clock frequency
|
||||
* @get_freq: Get the Clock frequency
|
||||
* - current_freq: Frequency in Hz that the clock is at.
|
||||
*
|
||||
* NOTE: for all these functions, the following parameters are generic in
|
||||
* nature:
|
||||
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
|
||||
* -did: Device identifier this request is for
|
||||
* -cid: Clock identifier for the device for this request.
|
||||
* Each device has it's own set of clock inputs. This indexes
|
||||
* which clock input to modify.
|
||||
* -min_freq: The minimum allowable frequency in Hz. This is the minimum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* -target_freq: The target clock frequency in Hz. A frequency will be
|
||||
* processed as close to this target frequency as possible.
|
||||
* -max_freq: The maximum allowable frequency in Hz. This is the maximum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
*
|
||||
* Request for the clock - NOTE: the client MUST maintain integrity of
|
||||
* usage count by balancing get_clock with put_clock. No refcounting is
|
||||
* managed by driver for that purpose.
|
||||
*/
|
||||
struct ti_sci_clk_ops {
|
||||
int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
bool needs_ssc, bool can_change_freq,
|
||||
bool enable_input_term);
|
||||
int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
|
||||
int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
|
||||
int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
bool *req_state);
|
||||
int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
bool *req_state, bool *current_state);
|
||||
int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
bool *req_state, bool *current_state);
|
||||
int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
u32 parent_id);
|
||||
int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
u32 *parent_id);
|
||||
int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
|
||||
u32 cid, u32 *num_parents);
|
||||
int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
|
||||
u32 cid, u64 min_freq, u64 target_freq,
|
||||
u64 max_freq, u64 *match_freq);
|
||||
int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
u64 min_freq, u64 target_freq, u64 max_freq);
|
||||
int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
|
||||
u64 *current_freq);
|
||||
};
|
||||
|
||||
/* TISCI LPM IO isolation control values */
|
||||
#define TISCI_MSG_VALUE_IO_ENABLE 1
|
||||
#define TISCI_MSG_VALUE_IO_DISABLE 0
|
||||
|
||||
/* TISCI LPM constraint state values */
|
||||
#define TISCI_MSG_CONSTRAINT_SET 1
|
||||
#define TISCI_MSG_CONSTRAINT_CLR 0
|
||||
|
||||
/**
|
||||
* struct ti_sci_pm_ops - Low Power Mode (LPM) control operations
|
||||
* @lpm_wake_reason: Get the wake up source that woke the SoC from LPM
|
||||
* - source: The wake up source that woke soc from LPM.
|
||||
* - timestamp: Timestamp at which soc woke.
|
||||
* @set_device_constraint: Set LPM constraint on behalf of a device
|
||||
* - id: Device Identifier
|
||||
* - state: The desired state of device constraint: set or clear.
|
||||
* @set_latency_constraint: Set LPM resume latency constraint
|
||||
* - latency: maximum acceptable latency to wake up from low power mode
|
||||
* - state: The desired state of latency constraint: set or clear.
|
||||
*/
|
||||
struct ti_sci_pm_ops {
|
||||
int (*lpm_wake_reason)(const struct ti_sci_handle *handle,
|
||||
u32 *source, u64 *timestamp, u8 *pin, u8 *mode);
|
||||
int (*set_device_constraint)(const struct ti_sci_handle *handle,
|
||||
u32 id, u8 state);
|
||||
int (*set_latency_constraint)(const struct ti_sci_handle *handle,
|
||||
u16 latency, u8 state);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
|
||||
* @start: Start index of the first resource range.
|
||||
* @num: Number of resources in the first range.
|
||||
* @start_sec: Start index of the second resource range.
|
||||
* @num_sec: Number of resources in the second range.
|
||||
* @res_map: Bitmap to manage the allocation of these resources.
|
||||
*/
|
||||
struct ti_sci_resource_desc {
|
||||
u16 start;
|
||||
u16 num;
|
||||
u16 start_sec;
|
||||
u16 num_sec;
|
||||
unsigned long *res_map;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_core_ops - Resource management core operations
|
||||
* @get_range: Get a range of resources belonging to ti sci host.
|
||||
* @get_rage_from_shost: Get a range of resources belonging to
|
||||
* specified host id.
|
||||
* - s_host: Host processing entity to which the
|
||||
* resources are allocated
|
||||
*
|
||||
* NOTE: for these functions, all the parameters are consolidated and defined
|
||||
* as below:
|
||||
* - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
|
||||
* - dev_id: TISCI device ID.
|
||||
* - subtype: Resource assignment subtype that is being requested
|
||||
* from the given device.
|
||||
* - desc: Pointer to ti_sci_resource_desc to be updated with the resource
|
||||
* range start index and number of resources
|
||||
*/
|
||||
struct ti_sci_rm_core_ops {
|
||||
int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
|
||||
u8 subtype, struct ti_sci_resource_desc *desc);
|
||||
int (*get_range_from_shost)(const struct ti_sci_handle *handle,
|
||||
u32 dev_id, u8 subtype, u8 s_host,
|
||||
struct ti_sci_resource_desc *desc);
|
||||
};
|
||||
|
||||
#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
|
||||
#define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
|
||||
#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
|
||||
/**
|
||||
* struct ti_sci_rm_irq_ops: IRQ management operations
|
||||
* @set_irq: Set an IRQ route between the requested source
|
||||
* and destination
|
||||
* @set_event_map: Set an Event based peripheral irq to Interrupt
|
||||
* Aggregator.
|
||||
* @free_irq: Free an IRQ route between the requested source
|
||||
* and destination.
|
||||
* @free_event_map: Free an event based peripheral irq to Interrupt
|
||||
* Aggregator.
|
||||
*/
|
||||
struct ti_sci_rm_irq_ops {
|
||||
int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
|
||||
u16 src_index, u16 dst_id, u16 dst_host_irq);
|
||||
int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
|
||||
u16 src_index, u16 ia_id, u16 vint,
|
||||
u16 global_event, u8 vint_status_bit);
|
||||
int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
|
||||
u16 src_index, u16 dst_id, u16 dst_host_irq);
|
||||
int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
|
||||
u16 src_index, u16 ia_id, u16 vint,
|
||||
u16 global_event, u8 vint_status_bit);
|
||||
};
|
||||
|
||||
/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
|
||||
/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
|
||||
/* RA config.count parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
|
||||
/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
|
||||
/* RA config.size parameter is valid for RM ring configure TI_SCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
|
||||
/* RA config.order_id parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
|
||||
/* RA config.virtid parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6)
|
||||
/* RA config.asel parameter is valid for RM ring configure TISCI message */
|
||||
#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
|
||||
|
||||
#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
|
||||
(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
|
||||
TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_rm_ring_cfg - Ring configuration
|
||||
*
|
||||
* Parameters for Navigator Subsystem ring configuration
|
||||
* See @ti_sci_msg_rm_ring_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_cfg {
|
||||
u32 valid_params;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u32 addr_lo;
|
||||
u32 addr_hi;
|
||||
u32 count;
|
||||
u8 mode;
|
||||
u8 size;
|
||||
u8 order_id;
|
||||
u16 virtid;
|
||||
u8 asel;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
|
||||
* @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
|
||||
*/
|
||||
struct ti_sci_rm_ringacc_ops {
|
||||
int (*set_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_ring_cfg *params);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_psil_ops - PSI-L thread operations
|
||||
* @pair: pair PSI-L source thread to a destination thread.
|
||||
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
|
||||
* TCHAN_THRD_ID register is updated.
|
||||
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
|
||||
* RCHAN_THRD_ID register is updated.
|
||||
* @unpair: unpair PSI-L source thread from a destination thread.
|
||||
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
|
||||
* TCHAN_THRD_ID register is cleared.
|
||||
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
|
||||
* RCHAN_THRD_ID register is cleared.
|
||||
*/
|
||||
struct ti_sci_rm_psil_ops {
|
||||
int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
|
||||
u32 src_thread, u32 dst_thread);
|
||||
int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
|
||||
u32 src_thread, u32 dst_thread);
|
||||
};
|
||||
|
||||
/* UDMAP channel types */
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
|
||||
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
|
||||
|
||||
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
|
||||
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
|
||||
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
|
||||
#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
|
||||
|
||||
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
|
||||
#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
|
||||
|
||||
/* UDMAP TX/RX channel valid_params common declarations */
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP transmit channel
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP transmit channel registers.
|
||||
* See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_tx_ch_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u8 tx_pause_on_err;
|
||||
u8 tx_filt_einfo;
|
||||
u8 tx_filt_pswords;
|
||||
u8 tx_atype;
|
||||
u8 tx_chan_type;
|
||||
u8 tx_supr_tdpkt;
|
||||
u16 tx_fetch_size;
|
||||
u8 tx_credit_count;
|
||||
u16 txcq_qnum;
|
||||
u8 tx_priority;
|
||||
u8 tx_qos;
|
||||
u8 tx_orderid;
|
||||
u16 fdepth;
|
||||
u8 tx_sched_priority;
|
||||
u8 tx_burst_size;
|
||||
u8 tx_tdtype;
|
||||
u8 extended_ch_type;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive channel
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP receive channel registers.
|
||||
* See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_rx_ch_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u16 rx_fetch_size;
|
||||
u16 rxcq_qnum;
|
||||
u8 rx_priority;
|
||||
u8 rx_qos;
|
||||
u8 rx_orderid;
|
||||
u8 rx_sched_priority;
|
||||
u16 flowid_start;
|
||||
u16 flowid_cnt;
|
||||
u8 rx_pause_on_err;
|
||||
u8 rx_atype;
|
||||
u8 rx_chan_type;
|
||||
u8 rx_ignore_short;
|
||||
u8 rx_ignore_long;
|
||||
u8 rx_burst_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive flow
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP receive flow's registers.
|
||||
* See @tis_ci_msg_rm_udmap_flow_cfg_req
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_flow_cfg {
|
||||
u32 valid_params;
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
|
||||
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
|
||||
u16 nav_id;
|
||||
u16 flow_index;
|
||||
u8 rx_einfo_present;
|
||||
u8 rx_psinfo_present;
|
||||
u8 rx_error_handling;
|
||||
u8 rx_desc_type;
|
||||
u16 rx_sop_offset;
|
||||
u16 rx_dest_qnum;
|
||||
u8 rx_src_tag_hi;
|
||||
u8 rx_src_tag_lo;
|
||||
u8 rx_dest_tag_hi;
|
||||
u8 rx_dest_tag_lo;
|
||||
u8 rx_src_tag_hi_sel;
|
||||
u8 rx_src_tag_lo_sel;
|
||||
u8 rx_dest_tag_hi_sel;
|
||||
u8 rx_dest_tag_lo_sel;
|
||||
u16 rx_fdq0_sz0_qnum;
|
||||
u16 rx_fdq1_qnum;
|
||||
u16 rx_fdq2_qnum;
|
||||
u16 rx_fdq3_qnum;
|
||||
u8 rx_ps_location;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_rm_udmap_ops - UDMA Management operations
|
||||
* @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
|
||||
* @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
|
||||
* @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
|
||||
*/
|
||||
struct ti_sci_rm_udmap_ops {
|
||||
int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
|
||||
int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
|
||||
int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
|
||||
const struct ti_sci_msg_rm_udmap_flow_cfg *params);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_proc_ops - Processor Control operations
|
||||
* @request: Request to control a physical processor. The requesting host
|
||||
* should be in the processor access list
|
||||
* @release: Relinquish a physical processor control
|
||||
* @handover: Handover a physical processor control to another host
|
||||
* in the permitted list
|
||||
* @set_config: Set base configuration of a processor
|
||||
* @set_control: Setup limited control flags in specific cases
|
||||
* @get_status: Get the state of physical processor
|
||||
*
|
||||
* NOTE: The following paramteres are generic in nature for all these ops,
|
||||
* -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
|
||||
* -pid: Processor ID
|
||||
* -hid: Host ID
|
||||
*/
|
||||
struct ti_sci_proc_ops {
|
||||
int (*request)(const struct ti_sci_handle *handle, u8 pid);
|
||||
int (*release)(const struct ti_sci_handle *handle, u8 pid);
|
||||
int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
|
||||
int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u64 boot_vector, u32 cfg_set, u32 cfg_clr);
|
||||
int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u32 ctrl_set, u32 ctrl_clr);
|
||||
int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
|
||||
u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
|
||||
u32 *status_flags);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_ops - Function support for TI SCI
|
||||
* @dev_ops: Device specific operations
|
||||
* @clk_ops: Clock specific operations
|
||||
* @rm_core_ops: Resource management core operations.
|
||||
* @rm_irq_ops: IRQ management specific operations
|
||||
* @proc_ops: Processor Control specific operations
|
||||
*/
|
||||
struct ti_sci_ops {
|
||||
struct ti_sci_core_ops core_ops;
|
||||
struct ti_sci_dev_ops dev_ops;
|
||||
struct ti_sci_clk_ops clk_ops;
|
||||
struct ti_sci_pm_ops pm_ops;
|
||||
struct ti_sci_rm_core_ops rm_core_ops;
|
||||
struct ti_sci_rm_irq_ops rm_irq_ops;
|
||||
struct ti_sci_rm_ringacc_ops rm_ring_ops;
|
||||
struct ti_sci_rm_psil_ops rm_psil_ops;
|
||||
struct ti_sci_rm_udmap_ops rm_udmap_ops;
|
||||
struct ti_sci_proc_ops proc_ops;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_sci_handle - Handle returned to TI SCI clients for usage.
|
||||
* @version: structure containing version information
|
||||
* @ops: operations that are made available to TI SCI clients
|
||||
*/
|
||||
struct ti_sci_handle {
|
||||
struct ti_sci_version_info version;
|
||||
struct ti_sci_ops ops;
|
||||
};
|
||||
|
||||
#define TI_SCI_RESOURCE_NULL 0xffff
|
||||
|
||||
/**
|
||||
* struct ti_sci_resource - Structure representing a resource assigned
|
||||
* to a device.
|
||||
* @sets: Number of sets available from this resource type
|
||||
* @lock: Lock to guard the res map in each set.
|
||||
* @desc: Array of resource descriptors.
|
||||
*/
|
||||
struct ti_sci_resource {
|
||||
u16 sets;
|
||||
raw_spinlock_t lock;
|
||||
struct ti_sci_resource_desc *desc;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
|
||||
const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
|
||||
int ti_sci_put_handle(const struct ti_sci_handle *handle);
|
||||
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
|
||||
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
|
||||
const char *property);
|
||||
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
|
||||
const char *property);
|
||||
u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
|
||||
void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
|
||||
u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
|
||||
struct ti_sci_resource *
|
||||
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
|
||||
struct device *dev, u32 dev_id, char *of_prop);
|
||||
struct ti_sci_resource *
|
||||
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
|
||||
u32 dev_id, u32 sub_type);
|
||||
|
||||
#else /* CONFIG_TI_SCI_PROTOCOL */
|
||||
|
||||
static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
|
||||
const char *property)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
|
||||
const char *property)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
|
||||
{
|
||||
return TI_SCI_RESOURCE_NULL;
|
||||
}
|
||||
|
||||
static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
|
||||
{
|
||||
}
|
||||
|
||||
static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct ti_sci_resource *
|
||||
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
|
||||
struct device *dev, u32 dev_id, char *of_prop)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline struct ti_sci_resource *
|
||||
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
|
||||
u32 dev_id, u32 sub_type)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
#endif /* CONFIG_TI_SCI_PROTOCOL */
|
||||
|
||||
#endif /* __TISCI_PROTOCOL_H */
|
||||
Reference in New Issue
Block a user