restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
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@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2023 Advanced Micro Devices, Inc */
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#ifndef _PDSC_AUXBUS_H_
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#define _PDSC_AUXBUS_H_
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#include <linux/auxiliary_bus.h>
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struct pds_auxiliary_dev {
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struct auxiliary_device aux_dev;
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struct pci_dev *vf_pdev;
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u16 client_id;
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};
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int pds_client_adminq_cmd(struct pds_auxiliary_dev *padev,
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union pds_core_adminq_cmd *req,
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size_t req_len,
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union pds_core_adminq_comp *resp,
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u64 flags);
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#endif /* _PDSC_AUXBUS_H_ */
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@@ -0,0 +1,56 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
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/* Copyright(c) 2023 Advanced Micro Devices, Inc. */
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#ifndef _PDS_COMMON_H_
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#define _PDS_COMMON_H_
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#include <linux/notifier.h>
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#define PDS_CORE_DRV_NAME "pds_core"
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/* the device's internal addressing uses up to 52 bits */
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#define PDS_CORE_ADDR_LEN 52
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#define PDS_CORE_ADDR_MASK (BIT_ULL(PDS_ADDR_LEN) - 1)
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#define PDS_PAGE_SIZE 4096
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enum pds_core_driver_type {
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PDS_DRIVER_LINUX = 1,
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PDS_DRIVER_WIN = 2,
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PDS_DRIVER_DPDK = 3,
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PDS_DRIVER_FREEBSD = 4,
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PDS_DRIVER_IPXE = 5,
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PDS_DRIVER_ESXI = 6,
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};
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enum pds_core_vif_types {
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PDS_DEV_TYPE_CORE = 0,
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PDS_DEV_TYPE_VDPA = 1,
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PDS_DEV_TYPE_VFIO = 2,
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PDS_DEV_TYPE_ETH = 3,
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PDS_DEV_TYPE_RDMA = 4,
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PDS_DEV_TYPE_LM = 5,
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PDS_DEV_TYPE_FWCTL = 6,
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/* new ones added before this line */
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PDS_DEV_TYPE_MAX = 16 /* don't change - used in struct size */
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};
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#define PDS_DEV_TYPE_CORE_STR "Core"
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#define PDS_DEV_TYPE_VDPA_STR "vDPA"
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#define PDS_DEV_TYPE_VFIO_STR "vfio"
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#define PDS_DEV_TYPE_ETH_STR "Eth"
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#define PDS_DEV_TYPE_RDMA_STR "RDMA"
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#define PDS_DEV_TYPE_LM_STR "LM"
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#define PDS_DEV_TYPE_FWCTL_STR "fwctl"
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#define PDS_VDPA_DEV_NAME PDS_CORE_DRV_NAME "." PDS_DEV_TYPE_VDPA_STR
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#define PDS_VFIO_LM_DEV_NAME PDS_CORE_DRV_NAME "." PDS_DEV_TYPE_LM_STR "." PDS_DEV_TYPE_VFIO_STR
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struct pdsc;
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int pdsc_register_notify(struct notifier_block *nb);
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void pdsc_unregister_notify(struct notifier_block *nb);
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void *pdsc_get_pf_struct(struct pci_dev *vf_pdev);
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int pds_client_register(struct pdsc *pf, char *devname);
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int pds_client_unregister(struct pdsc *pf, u16 client_id);
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#endif /* _PDS_COMMON_H_ */
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@@ -0,0 +1,572 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
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/* Copyright(c) 2023 Advanced Micro Devices, Inc. */
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#ifndef _PDS_CORE_IF_H_
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#define _PDS_CORE_IF_H_
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#define PCI_VENDOR_ID_PENSANDO 0x1dd8
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#define PCI_DEVICE_ID_PENSANDO_CORE_PF 0x100c
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#define PCI_DEVICE_ID_VIRTIO_NET_TRANS 0x1000
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#define PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF 0x1003
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#define PCI_DEVICE_ID_PENSANDO_VDPA_VF 0x100b
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#define PDS_CORE_BARS_MAX 4
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#define PDS_CORE_PCI_BAR_DBELL 1
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/* Bar0 */
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#define PDS_CORE_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
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#define PDS_CORE_BAR0_SIZE 0x8000
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#define PDS_CORE_BAR0_DEV_INFO_REGS_OFFSET 0x0000
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#define PDS_CORE_BAR0_DEV_CMD_REGS_OFFSET 0x0800
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#define PDS_CORE_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
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#define PDS_CORE_BAR0_INTR_STATUS_OFFSET 0x1000
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#define PDS_CORE_BAR0_INTR_CTRL_OFFSET 0x2000
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#define PDS_CORE_DEV_CMD_DONE 0x00000001
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#define PDS_CORE_DEVCMD_TIMEOUT 5
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#define PDS_CORE_CLIENT_ID 0
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#define PDS_CORE_ASIC_TYPE_CAPRI 0
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/*
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* enum pds_core_cmd_opcode - Device commands
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*/
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enum pds_core_cmd_opcode {
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/* Core init */
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PDS_CORE_CMD_NOP = 0,
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PDS_CORE_CMD_IDENTIFY = 1,
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PDS_CORE_CMD_RESET = 2,
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PDS_CORE_CMD_INIT = 3,
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PDS_CORE_CMD_FW_DOWNLOAD = 4,
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PDS_CORE_CMD_FW_CONTROL = 5,
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/* SR/IOV commands */
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PDS_CORE_CMD_VF_GETATTR = 60,
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PDS_CORE_CMD_VF_SETATTR = 61,
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PDS_CORE_CMD_VF_CTRL = 62,
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/* Add commands before this line */
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PDS_CORE_CMD_MAX,
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PDS_CORE_CMD_COUNT
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};
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/*
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* enum pds_core_status_code - Device command return codes
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*/
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enum pds_core_status_code {
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PDS_RC_SUCCESS = 0, /* Success */
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PDS_RC_EVERSION = 1, /* Incorrect version for request */
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PDS_RC_EOPCODE = 2, /* Invalid cmd opcode */
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PDS_RC_EIO = 3, /* I/O error */
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PDS_RC_EPERM = 4, /* Permission denied */
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PDS_RC_EQID = 5, /* Bad qid */
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PDS_RC_EQTYPE = 6, /* Bad qtype */
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PDS_RC_ENOENT = 7, /* No such element */
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PDS_RC_EINTR = 8, /* operation interrupted */
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PDS_RC_EAGAIN = 9, /* Try again */
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PDS_RC_ENOMEM = 10, /* Out of memory */
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PDS_RC_EFAULT = 11, /* Bad address */
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PDS_RC_EBUSY = 12, /* Device or resource busy */
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PDS_RC_EEXIST = 13, /* object already exists */
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PDS_RC_EINVAL = 14, /* Invalid argument */
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PDS_RC_ENOSPC = 15, /* No space left or alloc failure */
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PDS_RC_ERANGE = 16, /* Parameter out of range */
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PDS_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
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PDS_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
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PDS_RC_ENOSUPP = 19, /* Operation not supported */
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PDS_RC_ERROR = 29, /* Generic error */
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PDS_RC_ERDMA = 30, /* Generic RDMA error */
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PDS_RC_EVFID = 31, /* VF ID does not exist */
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PDS_RC_BAD_FW = 32, /* FW file is invalid or corrupted */
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PDS_RC_ECLIENT = 33, /* No such client id */
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PDS_RC_BAD_PCI = 255, /* Broken PCI when reading status */
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};
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/**
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* struct pds_core_drv_identity - Driver identity information
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* @drv_type: Driver type (enum pds_core_driver_type)
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* @os_dist: OS distribution, numeric format
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* @os_dist_str: OS distribution, string format
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* @kernel_ver: Kernel version, numeric format
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* @kernel_ver_str: Kernel version, string format
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* @driver_ver_str: Driver version, string format
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*/
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struct pds_core_drv_identity {
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__le32 drv_type;
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__le32 os_dist;
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char os_dist_str[128];
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__le32 kernel_ver;
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char kernel_ver_str[32];
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char driver_ver_str[32];
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};
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#define PDS_DEV_TYPE_MAX 16
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/**
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* struct pds_core_dev_identity - Device identity information
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* @version: Version of device identify
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* @type: Identify type (0 for now)
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* @state: Device state
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* @rsvd: Word boundary padding
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* @nlifs: Number of LIFs provisioned
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* @nintrs: Number of interrupts provisioned
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* @ndbpgs_per_lif: Number of doorbell pages per LIF
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* @intr_coal_mult: Interrupt coalescing multiplication factor
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* Scale user-supplied interrupt coalescing
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* value in usecs to device units using:
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* device units = usecs * mult / div
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* @intr_coal_div: Interrupt coalescing division factor
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* Scale user-supplied interrupt coalescing
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* value in usecs to device units using:
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* device units = usecs * mult / div
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* @vif_types: How many of each VIF device type is supported
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*/
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struct pds_core_dev_identity {
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u8 version;
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u8 type;
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u8 state;
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u8 rsvd;
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__le32 nlifs;
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__le32 nintrs;
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__le32 ndbpgs_per_lif;
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__le32 intr_coal_mult;
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__le32 intr_coal_div;
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__le16 vif_types[PDS_DEV_TYPE_MAX];
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};
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#define PDS_CORE_IDENTITY_VERSION_1 1
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/**
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* struct pds_core_dev_identify_cmd - Driver/device identify command
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* @opcode: Opcode PDS_CORE_CMD_IDENTIFY
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* @ver: Highest version of identify supported by driver
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*
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* Expects to find driver identification info (struct pds_core_drv_identity)
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* in cmd_regs->data. Driver should keep the devcmd interface locked
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* while preparing the driver info.
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*/
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struct pds_core_dev_identify_cmd {
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u8 opcode;
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u8 ver;
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};
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/**
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* struct pds_core_dev_identify_comp - Device identify command completion
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* @status: Status of the command (enum pds_core_status_code)
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* @ver: Version of identify returned by device
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*
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* Device identification info (struct pds_core_dev_identity) can be found
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* in cmd_regs->data. Driver should keep the devcmd interface locked
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* while reading the results.
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*/
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struct pds_core_dev_identify_comp {
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u8 status;
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u8 ver;
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};
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/**
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* struct pds_core_dev_reset_cmd - Device reset command
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* @opcode: Opcode PDS_CORE_CMD_RESET
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*
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* Resets and clears all LIFs, VDevs, and VIFs on the device.
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*/
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struct pds_core_dev_reset_cmd {
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u8 opcode;
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};
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/**
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* struct pds_core_dev_reset_comp - Reset command completion
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* @status: Status of the command (enum pds_core_status_code)
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*/
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struct pds_core_dev_reset_comp {
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u8 status;
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};
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/*
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* struct pds_core_dev_init_data - Pointers and info needed for the Core
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* initialization PDS_CORE_CMD_INIT command. The in and out structs are
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* overlays on the pds_core_dev_cmd_regs.data space for passing data down
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* to the firmware on init, and then returning initialization results.
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*/
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struct pds_core_dev_init_data_in {
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__le64 adminq_q_base;
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__le64 adminq_cq_base;
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__le64 notifyq_cq_base;
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__le32 flags;
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__le16 intr_index;
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u8 adminq_ring_size;
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u8 notifyq_ring_size;
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};
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struct pds_core_dev_init_data_out {
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__le32 core_hw_index;
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__le32 adminq_hw_index;
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__le32 notifyq_hw_index;
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u8 adminq_hw_type;
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u8 notifyq_hw_type;
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};
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/**
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* struct pds_core_dev_init_cmd - Core device initialize
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* @opcode: opcode PDS_CORE_CMD_INIT
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*
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* Initializes the core device and sets up the AdminQ and NotifyQ.
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* Expects to find initialization data (struct pds_core_dev_init_data_in)
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* in cmd_regs->data. Driver should keep the devcmd interface locked
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* while preparing the driver info.
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*/
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struct pds_core_dev_init_cmd {
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u8 opcode;
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};
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/**
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* struct pds_core_dev_init_comp - Core init completion
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* @status: Status of the command (enum pds_core_status_code)
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*
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* Initialization result data (struct pds_core_dev_init_data_in)
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* is found in cmd_regs->data.
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*/
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struct pds_core_dev_init_comp {
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u8 status;
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};
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/**
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* struct pds_core_fw_download_cmd - Firmware download command
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* @opcode: opcode
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* @rsvd: Word boundary padding
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* @addr: DMA address of the firmware buffer
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* @offset: offset of the firmware buffer within the full image
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* @length: number of valid bytes in the firmware buffer
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*/
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struct pds_core_fw_download_cmd {
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u8 opcode;
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u8 rsvd[3];
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__le32 offset;
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__le64 addr;
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__le32 length;
|
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};
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/**
|
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* struct pds_core_fw_download_comp - Firmware download completion
|
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* @status: Status of the command (enum pds_core_status_code)
|
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*/
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struct pds_core_fw_download_comp {
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u8 status;
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};
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|
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/**
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* enum pds_core_fw_control_oper - FW control operations
|
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* @PDS_CORE_FW_INSTALL_ASYNC: Install firmware asynchronously
|
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* @PDS_CORE_FW_INSTALL_STATUS: Firmware installation status
|
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* @PDS_CORE_FW_ACTIVATE_ASYNC: Activate firmware asynchronously
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* @PDS_CORE_FW_ACTIVATE_STATUS: Firmware activate status
|
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* @PDS_CORE_FW_UPDATE_CLEANUP: Cleanup any firmware update leftovers
|
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* @PDS_CORE_FW_GET_BOOT: Return current active firmware slot
|
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* @PDS_CORE_FW_SET_BOOT: Set active firmware slot for next boot
|
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* @PDS_CORE_FW_GET_LIST: Return list of installed firmware images
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*/
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enum pds_core_fw_control_oper {
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PDS_CORE_FW_INSTALL_ASYNC = 0,
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PDS_CORE_FW_INSTALL_STATUS = 1,
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PDS_CORE_FW_ACTIVATE_ASYNC = 2,
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PDS_CORE_FW_ACTIVATE_STATUS = 3,
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PDS_CORE_FW_UPDATE_CLEANUP = 4,
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PDS_CORE_FW_GET_BOOT = 5,
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PDS_CORE_FW_SET_BOOT = 6,
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PDS_CORE_FW_GET_LIST = 7,
|
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};
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|
||||
enum pds_core_fw_slot {
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PDS_CORE_FW_SLOT_INVALID = 0,
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PDS_CORE_FW_SLOT_A = 1,
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PDS_CORE_FW_SLOT_B = 2,
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||||
PDS_CORE_FW_SLOT_GOLD = 3,
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};
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/**
|
||||
* struct pds_core_fw_control_cmd - Firmware control command
|
||||
* @opcode: opcode
|
||||
* @rsvd: Word boundary padding
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||||
* @oper: firmware control operation (enum pds_core_fw_control_oper)
|
||||
* @slot: slot to operate on (enum pds_core_fw_slot)
|
||||
*/
|
||||
struct pds_core_fw_control_cmd {
|
||||
u8 opcode;
|
||||
u8 rsvd[3];
|
||||
u8 oper;
|
||||
u8 slot;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_fw_control_comp - Firmware control copletion
|
||||
* @status: Status of the command (enum pds_core_status_code)
|
||||
* @rsvd: Word alignment space
|
||||
* @slot: Slot number (enum pds_core_fw_slot)
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||||
* @rsvd1: Struct padding
|
||||
* @color: Color bit
|
||||
*/
|
||||
struct pds_core_fw_control_comp {
|
||||
u8 status;
|
||||
u8 rsvd[3];
|
||||
u8 slot;
|
||||
u8 rsvd1[10];
|
||||
u8 color;
|
||||
};
|
||||
|
||||
struct pds_core_fw_name_info {
|
||||
#define PDS_CORE_FWSLOT_BUFLEN 8
|
||||
#define PDS_CORE_FWVERS_BUFLEN 32
|
||||
char slotname[PDS_CORE_FWSLOT_BUFLEN];
|
||||
char fw_version[PDS_CORE_FWVERS_BUFLEN];
|
||||
};
|
||||
|
||||
struct pds_core_fw_list_info {
|
||||
#define PDS_CORE_FWVERS_LIST_LEN 16
|
||||
u8 num_fw_slots;
|
||||
struct pds_core_fw_name_info fw_names[PDS_CORE_FWVERS_LIST_LEN];
|
||||
} __packed;
|
||||
|
||||
enum pds_core_vf_attr {
|
||||
PDS_CORE_VF_ATTR_SPOOFCHK = 1,
|
||||
PDS_CORE_VF_ATTR_TRUST = 2,
|
||||
PDS_CORE_VF_ATTR_MAC = 3,
|
||||
PDS_CORE_VF_ATTR_LINKSTATE = 4,
|
||||
PDS_CORE_VF_ATTR_VLAN = 5,
|
||||
PDS_CORE_VF_ATTR_RATE = 6,
|
||||
PDS_CORE_VF_ATTR_STATSADDR = 7,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum pds_core_vf_link_status - Virtual Function link status
|
||||
* @PDS_CORE_VF_LINK_STATUS_AUTO: Use link state of the uplink
|
||||
* @PDS_CORE_VF_LINK_STATUS_UP: Link always up
|
||||
* @PDS_CORE_VF_LINK_STATUS_DOWN: Link always down
|
||||
*/
|
||||
enum pds_core_vf_link_status {
|
||||
PDS_CORE_VF_LINK_STATUS_AUTO = 0,
|
||||
PDS_CORE_VF_LINK_STATUS_UP = 1,
|
||||
PDS_CORE_VF_LINK_STATUS_DOWN = 2,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_vf_setattr_cmd - Set VF attributes on the NIC
|
||||
* @opcode: Opcode
|
||||
* @attr: Attribute type (enum pds_core_vf_attr)
|
||||
* @vf_index: VF index
|
||||
* @macaddr: mac address
|
||||
* @vlanid: vlan ID
|
||||
* @maxrate: max Tx rate in Mbps
|
||||
* @spoofchk: enable address spoof checking
|
||||
* @trust: enable VF trust
|
||||
* @linkstate: set link up or down
|
||||
* @stats: stats addr struct
|
||||
* @stats.pa: set DMA address for VF stats
|
||||
* @stats.len: length of VF stats space
|
||||
* @pad: force union to specific size
|
||||
*/
|
||||
struct pds_core_vf_setattr_cmd {
|
||||
u8 opcode;
|
||||
u8 attr;
|
||||
__le16 vf_index;
|
||||
union {
|
||||
u8 macaddr[6];
|
||||
__le16 vlanid;
|
||||
__le32 maxrate;
|
||||
u8 spoofchk;
|
||||
u8 trust;
|
||||
u8 linkstate;
|
||||
struct {
|
||||
__le64 pa;
|
||||
__le32 len;
|
||||
} stats;
|
||||
u8 pad[60];
|
||||
} __packed;
|
||||
};
|
||||
|
||||
struct pds_core_vf_setattr_comp {
|
||||
u8 status;
|
||||
u8 attr;
|
||||
__le16 vf_index;
|
||||
__le16 comp_index;
|
||||
u8 rsvd[9];
|
||||
u8 color;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_vf_getattr_cmd - Get VF attributes from the NIC
|
||||
* @opcode: Opcode
|
||||
* @attr: Attribute type (enum pds_core_vf_attr)
|
||||
* @vf_index: VF index
|
||||
*/
|
||||
struct pds_core_vf_getattr_cmd {
|
||||
u8 opcode;
|
||||
u8 attr;
|
||||
__le16 vf_index;
|
||||
};
|
||||
|
||||
struct pds_core_vf_getattr_comp {
|
||||
u8 status;
|
||||
u8 attr;
|
||||
__le16 vf_index;
|
||||
union {
|
||||
u8 macaddr[6];
|
||||
__le16 vlanid;
|
||||
__le32 maxrate;
|
||||
u8 spoofchk;
|
||||
u8 trust;
|
||||
u8 linkstate;
|
||||
__le64 stats_pa;
|
||||
u8 pad[11];
|
||||
} __packed;
|
||||
u8 color;
|
||||
};
|
||||
|
||||
enum pds_core_vf_ctrl_opcode {
|
||||
PDS_CORE_VF_CTRL_START_ALL = 0,
|
||||
PDS_CORE_VF_CTRL_START = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_vf_ctrl_cmd - VF control command
|
||||
* @opcode: Opcode for the command
|
||||
* @ctrl_opcode: VF control operation type
|
||||
* @vf_index: VF Index. It is unused if op START_ALL is used.
|
||||
*/
|
||||
|
||||
struct pds_core_vf_ctrl_cmd {
|
||||
u8 opcode;
|
||||
u8 ctrl_opcode;
|
||||
__le16 vf_index;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_vf_ctrl_comp - VF_CTRL command completion.
|
||||
* @status: Status of the command (enum pds_core_status_code)
|
||||
*/
|
||||
struct pds_core_vf_ctrl_comp {
|
||||
u8 status;
|
||||
};
|
||||
|
||||
/*
|
||||
* union pds_core_dev_cmd - Overlay of core device command structures
|
||||
*/
|
||||
union pds_core_dev_cmd {
|
||||
u8 opcode;
|
||||
u32 words[16];
|
||||
|
||||
struct pds_core_dev_identify_cmd identify;
|
||||
struct pds_core_dev_init_cmd init;
|
||||
struct pds_core_dev_reset_cmd reset;
|
||||
struct pds_core_fw_download_cmd fw_download;
|
||||
struct pds_core_fw_control_cmd fw_control;
|
||||
|
||||
struct pds_core_vf_setattr_cmd vf_setattr;
|
||||
struct pds_core_vf_getattr_cmd vf_getattr;
|
||||
struct pds_core_vf_ctrl_cmd vf_ctrl;
|
||||
};
|
||||
|
||||
/*
|
||||
* union pds_core_dev_comp - Overlay of core device completion structures
|
||||
*/
|
||||
union pds_core_dev_comp {
|
||||
u8 status;
|
||||
u8 bytes[16];
|
||||
|
||||
struct pds_core_dev_identify_comp identify;
|
||||
struct pds_core_dev_reset_comp reset;
|
||||
struct pds_core_dev_init_comp init;
|
||||
struct pds_core_fw_download_comp fw_download;
|
||||
struct pds_core_fw_control_comp fw_control;
|
||||
|
||||
struct pds_core_vf_setattr_comp vf_setattr;
|
||||
struct pds_core_vf_getattr_comp vf_getattr;
|
||||
struct pds_core_vf_ctrl_comp vf_ctrl;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_dev_hwstamp_regs - Hardware current timestamp registers
|
||||
* @tick_low: Low 32 bits of hardware timestamp
|
||||
* @tick_high: High 32 bits of hardware timestamp
|
||||
*/
|
||||
struct pds_core_dev_hwstamp_regs {
|
||||
u32 tick_low;
|
||||
u32 tick_high;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pds_core_dev_info_regs - Device info register format (read-only)
|
||||
* @signature: Signature value of 0x44455649 ('DEVI')
|
||||
* @version: Current version of info
|
||||
* @asic_type: Asic type
|
||||
* @asic_rev: Asic revision
|
||||
* @fw_status: Firmware status
|
||||
* bit 0 - 1 = fw running
|
||||
* bit 4-7 - 4 bit generation number, changes on fw restart
|
||||
* @fw_heartbeat: Firmware heartbeat counter
|
||||
* @serial_num: Serial number
|
||||
* @fw_version: Firmware version
|
||||
* @oprom_regs: oprom_regs to store oprom debug enable/disable and bmp
|
||||
* @rsvd_pad1024: Struct padding
|
||||
* @hwstamp: Hardware current timestamp registers
|
||||
* @rsvd_pad2048: Struct padding
|
||||
*/
|
||||
struct pds_core_dev_info_regs {
|
||||
#define PDS_CORE_DEVINFO_FWVERS_BUFLEN 32
|
||||
#define PDS_CORE_DEVINFO_SERIAL_BUFLEN 32
|
||||
u32 signature;
|
||||
u8 version;
|
||||
u8 asic_type;
|
||||
u8 asic_rev;
|
||||
#define PDS_CORE_FW_STS_F_STOPPED 0x00
|
||||
#define PDS_CORE_FW_STS_F_RUNNING 0x01
|
||||
#define PDS_CORE_FW_STS_F_GENERATION 0xF0
|
||||
u8 fw_status;
|
||||
__le32 fw_heartbeat;
|
||||
char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN];
|
||||
char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN];
|
||||
u8 oprom_regs[32]; /* reserved */
|
||||
u8 rsvd_pad1024[916];
|
||||
struct pds_core_dev_hwstamp_regs hwstamp; /* on 1k boundary */
|
||||
u8 rsvd_pad2048[1016];
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct pds_core_dev_cmd_regs - Device command register format (read-write)
|
||||
* @doorbell: Device Cmd Doorbell, write-only
|
||||
* Write a 1 to signal device to process cmd
|
||||
* @done: Command completed indicator, poll for completion
|
||||
* bit 0 == 1 when command is complete
|
||||
* @cmd: Opcode-specific command bytes
|
||||
* @comp: Opcode-specific response bytes
|
||||
* @rsvd: Struct padding
|
||||
* @data: Opcode-specific side-data
|
||||
*/
|
||||
struct pds_core_dev_cmd_regs {
|
||||
u32 doorbell;
|
||||
u32 done;
|
||||
union pds_core_dev_cmd cmd;
|
||||
union pds_core_dev_comp comp;
|
||||
u8 rsvd[48];
|
||||
u32 data[478];
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct pds_core_dev_regs - Device register format for bar 0 page 0
|
||||
* @info: Device info registers
|
||||
* @devcmd: Device command registers
|
||||
*/
|
||||
struct pds_core_dev_regs {
|
||||
struct pds_core_dev_info_regs info;
|
||||
struct pds_core_dev_cmd_regs devcmd;
|
||||
} __packed;
|
||||
|
||||
#ifndef __CHECKER__
|
||||
static_assert(sizeof(struct pds_core_drv_identity) <= 1912);
|
||||
static_assert(sizeof(struct pds_core_dev_identity) <= 1912);
|
||||
static_assert(sizeof(union pds_core_dev_cmd) == 64);
|
||||
static_assert(sizeof(union pds_core_dev_comp) == 16);
|
||||
static_assert(sizeof(struct pds_core_dev_info_regs) == 2048);
|
||||
static_assert(sizeof(struct pds_core_dev_cmd_regs) == 2048);
|
||||
static_assert(sizeof(struct pds_core_dev_regs) == 4096);
|
||||
#endif /* __CHECKER__ */
|
||||
|
||||
#endif /* _PDS_CORE_IF_H_ */
|
||||
@@ -0,0 +1,163 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
|
||||
/* Copyright(c) 2023 Advanced Micro Devices, Inc. */
|
||||
|
||||
#ifndef _PDS_INTR_H_
|
||||
#define _PDS_INTR_H_
|
||||
|
||||
/*
|
||||
* Interrupt control register
|
||||
* @coal_init: Coalescing timer initial value, in
|
||||
* device units. Use @identity->intr_coal_mult
|
||||
* and @identity->intr_coal_div to convert from
|
||||
* usecs to device units:
|
||||
*
|
||||
* coal_init = coal_usecs * coal_mutl / coal_div
|
||||
*
|
||||
* When an interrupt is sent the interrupt
|
||||
* coalescing timer current value
|
||||
* (@coalescing_curr) is initialized with this
|
||||
* value and begins counting down. No more
|
||||
* interrupts are sent until the coalescing
|
||||
* timer reaches 0. When @coalescing_init=0
|
||||
* interrupt coalescing is effectively disabled
|
||||
* and every interrupt assert results in an
|
||||
* interrupt. Reset value: 0
|
||||
* @mask: Interrupt mask. When @mask=1 the interrupt
|
||||
* resource will not send an interrupt. When
|
||||
* @mask=0 the interrupt resource will send an
|
||||
* interrupt if an interrupt event is pending
|
||||
* or on the next interrupt assertion event.
|
||||
* Reset value: 1
|
||||
* @credits: Interrupt credits. This register indicates
|
||||
* how many interrupt events the hardware has
|
||||
* sent. When written by software this
|
||||
* register atomically decrements @int_credits
|
||||
* by the value written. When @int_credits
|
||||
* becomes 0 then the "pending interrupt" bit
|
||||
* in the Interrupt Status register is cleared
|
||||
* by the hardware and any pending but unsent
|
||||
* interrupts are cleared.
|
||||
* !!!IMPORTANT!!! This is a signed register.
|
||||
* @flags: Interrupt control flags
|
||||
* @unmask -- When this bit is written with a 1
|
||||
* the interrupt resource will set mask=0.
|
||||
* @coal_timer_reset -- When this
|
||||
* bit is written with a 1 the
|
||||
* @coalescing_curr will be reloaded with
|
||||
* @coalescing_init to reset the coalescing
|
||||
* timer.
|
||||
* @mask_on_assert: Automatically mask on assertion. When
|
||||
* @mask_on_assert=1 the interrupt resource
|
||||
* will set @mask=1 whenever an interrupt is
|
||||
* sent. When using interrupts in Legacy
|
||||
* Interrupt mode the driver must select
|
||||
* @mask_on_assert=0 for proper interrupt
|
||||
* operation.
|
||||
* @coalescing_curr: Coalescing timer current value, in
|
||||
* microseconds. When this value reaches 0
|
||||
* the interrupt resource is again eligible to
|
||||
* send an interrupt. If an interrupt event
|
||||
* is already pending when @coalescing_curr
|
||||
* reaches 0 the pending interrupt will be
|
||||
* sent, otherwise an interrupt will be sent
|
||||
* on the next interrupt assertion event.
|
||||
*/
|
||||
struct pds_core_intr {
|
||||
u32 coal_init;
|
||||
u32 mask;
|
||||
u16 credits;
|
||||
u16 flags;
|
||||
#define PDS_CORE_INTR_F_UNMASK 0x0001
|
||||
#define PDS_CORE_INTR_F_TIMER_RESET 0x0002
|
||||
u32 mask_on_assert;
|
||||
u32 coalescing_curr;
|
||||
u32 rsvd6[3];
|
||||
};
|
||||
|
||||
#ifndef __CHECKER__
|
||||
static_assert(sizeof(struct pds_core_intr) == 32);
|
||||
#endif /* __CHECKER__ */
|
||||
|
||||
#define PDS_CORE_INTR_CTRL_REGS_MAX 2048
|
||||
#define PDS_CORE_INTR_CTRL_COAL_MAX 0x3F
|
||||
#define PDS_CORE_INTR_INDEX_NOT_ASSIGNED -1
|
||||
|
||||
struct pds_core_intr_status {
|
||||
u32 status[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* enum pds_core_intr_mask_vals - valid values for mask and mask_assert.
|
||||
* @PDS_CORE_INTR_MASK_CLEAR: unmask interrupt.
|
||||
* @PDS_CORE_INTR_MASK_SET: mask interrupt.
|
||||
*/
|
||||
enum pds_core_intr_mask_vals {
|
||||
PDS_CORE_INTR_MASK_CLEAR = 0,
|
||||
PDS_CORE_INTR_MASK_SET = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum pds_core_intr_credits_bits - Bitwise composition of credits values.
|
||||
* @PDS_CORE_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
|
||||
* @PDS_CORE_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
|
||||
* @PDS_CORE_INTR_CRED_UNMASK: unmask the interrupt.
|
||||
* @PDS_CORE_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
|
||||
* @PDS_CORE_INTR_CRED_REARM: unmask the and reset the timer.
|
||||
*/
|
||||
enum pds_core_intr_credits_bits {
|
||||
PDS_CORE_INTR_CRED_COUNT = 0x7fffu,
|
||||
PDS_CORE_INTR_CRED_COUNT_SIGNED = 0xffffu,
|
||||
PDS_CORE_INTR_CRED_UNMASK = 0x10000u,
|
||||
PDS_CORE_INTR_CRED_RESET_COALESCE = 0x20000u,
|
||||
PDS_CORE_INTR_CRED_REARM = (PDS_CORE_INTR_CRED_UNMASK |
|
||||
PDS_CORE_INTR_CRED_RESET_COALESCE),
|
||||
};
|
||||
|
||||
static inline void
|
||||
pds_core_intr_coal_init(struct pds_core_intr __iomem *intr_ctrl, u32 coal)
|
||||
{
|
||||
iowrite32(coal, &intr_ctrl->coal_init);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pds_core_intr_mask(struct pds_core_intr __iomem *intr_ctrl, u32 mask)
|
||||
{
|
||||
iowrite32(mask, &intr_ctrl->mask);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pds_core_intr_credits(struct pds_core_intr __iomem *intr_ctrl,
|
||||
u32 cred, u32 flags)
|
||||
{
|
||||
if (WARN_ON_ONCE(cred > PDS_CORE_INTR_CRED_COUNT)) {
|
||||
cred = ioread32(&intr_ctrl->credits);
|
||||
cred &= PDS_CORE_INTR_CRED_COUNT_SIGNED;
|
||||
}
|
||||
|
||||
iowrite32(cred | flags, &intr_ctrl->credits);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pds_core_intr_clean_flags(struct pds_core_intr __iomem *intr_ctrl, u32 flags)
|
||||
{
|
||||
u32 cred;
|
||||
|
||||
cred = ioread32(&intr_ctrl->credits);
|
||||
cred &= PDS_CORE_INTR_CRED_COUNT_SIGNED;
|
||||
cred |= flags;
|
||||
iowrite32(cred, &intr_ctrl->credits);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pds_core_intr_clean(struct pds_core_intr __iomem *intr_ctrl)
|
||||
{
|
||||
pds_core_intr_clean_flags(intr_ctrl, PDS_CORE_INTR_CRED_RESET_COALESCE);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pds_core_intr_mask_assert(struct pds_core_intr __iomem *intr_ctrl, u32 mask)
|
||||
{
|
||||
iowrite32(mask, &intr_ctrl->mask_on_assert);
|
||||
}
|
||||
|
||||
#endif /* _PDS_INTR_H_ */
|
||||
Reference in New Issue
Block a user