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restore lost packages from 0.2.3 + fix overwritten 0.2.4 files

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- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.)
- Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber)
- Restore 20+ local/scripts (audit, lint, test, build helpers)
- Restore src/cook/scheduler.rs, status.rs, gnu-config/
- Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh
- Recover TLC source from HEAD (was overwritten by 0.2.3 checkout)
- Recover 11 local/docs plans from HEAD (were overwritten)
- Recover qt6-wayland-smoke symlink from HEAD
- Fix MOTD: remove garbled ASCII art, use clean text
- Update version: 0.2.0 -> 0.2.4 in os-release, motd, config
- Reduce filesystem_size: 1536 -> 512 MiB
- Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages
- Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
vasilito
2026-06-19 12:39:14 +03:00
parent ffbe098ef8
commit dc68054305
6418 changed files with 7066233 additions and 8670 deletions
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local/recipes/gpu/amdgpu-source/include/linux/mfd/88pm80x.h
+370
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@@ -0,0 +1,370 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell 88PM80x Interface
*
* Copyright (C) 2012 Marvell International Ltd.
* Qiao Zhou <zhouqiao@marvell.com>
*/
#ifndef __LINUX_MFD_88PM80X_H
#define __LINUX_MFD_88PM80X_H
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/atomic.h>
enum {
CHIP_INVALID = 0,
CHIP_PM800,
CHIP_PM805,
CHIP_PM860,
CHIP_MAX,
};
enum {
PM800_ID_BUCK1 = 0,
PM800_ID_BUCK2,
PM800_ID_BUCK3,
PM800_ID_BUCK4,
PM800_ID_BUCK5,
PM800_ID_LDO1,
PM800_ID_LDO2,
PM800_ID_LDO3,
PM800_ID_LDO4,
PM800_ID_LDO5,
PM800_ID_LDO6,
PM800_ID_LDO7,
PM800_ID_LDO8,
PM800_ID_LDO9,
PM800_ID_LDO10,
PM800_ID_LDO11,
PM800_ID_LDO12,
PM800_ID_LDO13,
PM800_ID_LDO14,
PM800_ID_LDO15,
PM800_ID_LDO16,
PM800_ID_LDO17,
PM800_ID_LDO18,
PM800_ID_LDO19,
PM800_ID_RG_MAX,
};
#define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */
#define PM800_NUM_BUCK (5) /*5 Bucks */
#define PM800_NUM_LDO (19) /*19 Bucks */
/* page 0 basic: slave adder 0x60 */
#define PM800_STATUS_1 (0x01)
#define PM800_ONKEY_STS1 BIT(0)
#define PM800_EXTON_STS1 BIT(1)
#define PM800_CHG_STS1 BIT(2)
#define PM800_BAT_STS1 BIT(3)
#define PM800_VBUS_STS1 BIT(4)
#define PM800_LDO_PGOOD_STS1 BIT(5)
#define PM800_BUCK_PGOOD_STS1 BIT(6)
#define PM800_STATUS_2 (0x02)
#define PM800_RTC_ALARM_STS2 BIT(0)
/* Wakeup Registers */
#define PM800_WAKEUP1 (0x0D)
#define PM800_WAKEUP2 (0x0E)
#define PM800_WAKEUP2_INV_INT BIT(0)
#define PM800_WAKEUP2_INT_CLEAR BIT(1)
#define PM800_WAKEUP2_INT_MASK BIT(2)
#define PM800_POWER_UP_LOG (0x10)
/* Referance and low power registers */
#define PM800_LOW_POWER1 (0x20)
#define PM800_LOW_POWER2 (0x21)
#define PM800_LOW_POWER_CONFIG3 (0x22)
#define PM800_LOW_POWER_CONFIG4 (0x23)
/* GPIO register */
#define PM800_GPIO_0_1_CNTRL (0x30)
#define PM800_GPIO0_VAL BIT(0)
#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
#define PM800_GPIO1_VAL BIT(4)
#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
#define PM800_GPIO_2_3_CNTRL (0x31)
#define PM800_GPIO2_VAL BIT(0)
#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
#define PM800_GPIO3_VAL BIT(4)
#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
#define PM800_GPIO3_MODE_MASK 0x1F
#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
#define PM800_GPIO_4_CNTRL (0x32)
#define PM800_GPIO4_VAL BIT(0)
#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
#define PM800_HEADSET_CNTRL (0x38)
#define PM800_HEADSET_DET_EN BIT(7)
#define PM800_HSDET_SLP BIT(1)
/* PWM register */
#define PM800_PWM1 (0x40)
#define PM800_PWM2 (0x41)
#define PM800_PWM3 (0x42)
#define PM800_PWM4 (0x43)
/* RTC Registers */
#define PM800_RTC_CONTROL (0xD0)
#define PM800_RTC_MISC1 (0xE1)
#define PM800_RTC_MISC2 (0xE2)
#define PM800_RTC_MISC3 (0xE3)
#define PM800_RTC_MISC4 (0xE4)
#define PM800_RTC_MISC5 (0xE7)
/* bit definitions of RTC Register 1 (0xD0) */
#define PM800_ALARM1_EN BIT(0)
#define PM800_ALARM_WAKEUP BIT(4)
#define PM800_ALARM BIT(5)
#define PM800_RTC1_USE_XO BIT(7)
/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
/* buck registers */
#define PM800_SLEEP_BUCK1 (0x30)
/* BUCK Sleep Mode Register 1: BUCK[1..4] */
#define PM800_BUCK_SLP1 (0x5A)
#define PM800_BUCK1_SLP1_SHIFT 0
#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
/* page 2 GPADC: slave adder 0x02 */
#define PM800_GPADC_MEAS_EN1 (0x01)
#define PM800_MEAS_EN1_VBAT BIT(2)
#define PM800_GPADC_MEAS_EN2 (0x02)
#define PM800_MEAS_EN2_RFTMP BIT(0)
#define PM800_MEAS_GP0_EN BIT(2)
#define PM800_MEAS_GP1_EN BIT(3)
#define PM800_MEAS_GP2_EN BIT(4)
#define PM800_MEAS_GP3_EN BIT(5)
#define PM800_MEAS_GP4_EN BIT(6)
#define PM800_GPADC_MISC_CONFIG1 (0x05)
#define PM800_GPADC_MISC_CONFIG2 (0x06)
#define PM800_GPADC_MISC_GPFSM_EN BIT(0)
#define PM800_GPADC_SLOW_MODE(x) (x << 3)
#define PM800_GPADC_MISC_CONFIG3 (0x09)
#define PM800_GPADC_MISC_CONFIG4 (0x0A)
#define PM800_GPADC_PREBIAS1 (0x0F)
#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
#define PM800_GPADC_PREBIAS2 (0x10)
#define PM800_GP_BIAS_ENA1 (0x14)
#define PM800_GPADC_GP_BIAS_EN0 BIT(0)
#define PM800_GPADC_GP_BIAS_EN1 BIT(1)
#define PM800_GPADC_GP_BIAS_EN2 BIT(2)
#define PM800_GPADC_GP_BIAS_EN3 BIT(3)
#define PM800_GP_BIAS_OUT1 (0x15)
#define PM800_BIAS_OUT_GP0 BIT(0)
#define PM800_BIAS_OUT_GP1 BIT(1)
#define PM800_BIAS_OUT_GP2 BIT(2)
#define PM800_BIAS_OUT_GP3 BIT(3)
#define PM800_GPADC0_LOW_TH 0x20
#define PM800_GPADC1_LOW_TH 0x21
#define PM800_GPADC2_LOW_TH 0x22
#define PM800_GPADC3_LOW_TH 0x23
#define PM800_GPADC4_LOW_TH 0x24
#define PM800_GPADC0_UPP_TH 0x30
#define PM800_GPADC1_UPP_TH 0x31
#define PM800_GPADC2_UPP_TH 0x32
#define PM800_GPADC3_UPP_TH 0x33
#define PM800_GPADC4_UPP_TH 0x34
#define PM800_VBBAT_MEAS1 0x40
#define PM800_VBBAT_MEAS2 0x41
#define PM800_VBAT_MEAS1 0x42
#define PM800_VBAT_MEAS2 0x43
#define PM800_VSYS_MEAS1 0x44
#define PM800_VSYS_MEAS2 0x45
#define PM800_VCHG_MEAS1 0x46
#define PM800_VCHG_MEAS2 0x47
#define PM800_TINT_MEAS1 0x50
#define PM800_TINT_MEAS2 0x51
#define PM800_PMOD_MEAS1 0x52
#define PM800_PMOD_MEAS2 0x53
#define PM800_GPADC0_MEAS1 0x54
#define PM800_GPADC0_MEAS2 0x55
#define PM800_GPADC1_MEAS1 0x56
#define PM800_GPADC1_MEAS2 0x57
#define PM800_GPADC2_MEAS1 0x58
#define PM800_GPADC2_MEAS2 0x59
#define PM800_GPADC3_MEAS1 0x5A
#define PM800_GPADC3_MEAS2 0x5B
#define PM800_GPADC4_MEAS1 0x5C
#define PM800_GPADC4_MEAS2 0x5D
#define PM800_GPADC4_AVG1 0xA8
#define PM800_GPADC4_AVG2 0xA9
/* 88PM805 Registers */
#define PM805_MAIN_POWERUP (0x01)
#define PM805_INT_STATUS0 (0x02) /* for ena/dis all interrupts */
#define PM805_STATUS0_INT_CLEAR (1 << 0)
#define PM805_STATUS0_INV_INT (1 << 1)
#define PM800_STATUS0_INT_MASK (1 << 2)
#define PM805_INT_STATUS1 (0x03)
#define PM805_INT1_HP1_SHRT BIT(0)
#define PM805_INT1_HP2_SHRT BIT(1)
#define PM805_INT1_MIC_CONFLICT BIT(2)
#define PM805_INT1_CLIP_FAULT BIT(3)
#define PM805_INT1_LDO_OFF BIT(4)
#define PM805_INT1_SRC_DPLL_LOCK BIT(5)
#define PM805_INT_STATUS2 (0x04)
#define PM805_INT2_MIC_DET BIT(0)
#define PM805_INT2_SHRT_BTN_DET BIT(1)
#define PM805_INT2_VOLM_BTN_DET BIT(2)
#define PM805_INT2_VOLP_BTN_DET BIT(3)
#define PM805_INT2_RAW_PLL_FAULT BIT(4)
#define PM805_INT2_FINE_PLL_FAULT BIT(5)
#define PM805_INT_MASK1 (0x05)
#define PM805_INT_MASK2 (0x06)
#define PM805_SHRT_BTN_DET BIT(1)
/* number of status and int reg in a row */
#define PM805_INT_REG_NUM (2)
#define PM805_MIC_DET1 (0x07)
#define PM805_MIC_DET_EN_MIC_DET BIT(0)
#define PM805_MIC_DET2 (0x08)
#define PM805_MIC_DET_STATUS1 (0x09)
#define PM805_MIC_DET_STATUS3 (0x0A)
#define PM805_AUTO_SEQ_STATUS1 (0x0B)
#define PM805_AUTO_SEQ_STATUS2 (0x0C)
#define PM805_ADC_SETTING1 (0x10)
#define PM805_ADC_SETTING2 (0x11)
#define PM805_ADC_SETTING3 (0x11)
#define PM805_ADC_GAIN1 (0x12)
#define PM805_ADC_GAIN2 (0x13)
#define PM805_DMIC_SETTING (0x15)
#define PM805_DWS_SETTING (0x16)
#define PM805_MIC_CONFLICT_STS (0x17)
#define PM805_PDM_SETTING1 (0x20)
#define PM805_PDM_SETTING2 (0x21)
#define PM805_PDM_SETTING3 (0x22)
#define PM805_PDM_CONTROL1 (0x23)
#define PM805_PDM_CONTROL2 (0x24)
#define PM805_PDM_CONTROL3 (0x25)
#define PM805_HEADPHONE_SETTING (0x26)
#define PM805_HEADPHONE_GAIN_A2A (0x27)
#define PM805_HEADPHONE_SHORT_STATE (0x28)
#define PM805_EARPHONE_SETTING (0x29)
#define PM805_AUTO_SEQ_SETTING (0x2A)
struct pm80x_rtc_pdata {
int vrtc;
int rtc_wakeup;
};
struct pm80x_subchip {
struct i2c_client *power_page; /* chip client for power page */
struct i2c_client *gpadc_page; /* chip client for gpadc page */
struct regmap *regmap_power;
struct regmap *regmap_gpadc;
unsigned short power_page_addr; /* power page I2C address */
unsigned short gpadc_page_addr; /* gpadc page I2C address */
};
struct pm80x_chip {
struct pm80x_subchip *subchip;
struct device *dev;
struct i2c_client *client;
struct i2c_client *companion;
struct regmap *regmap;
const struct regmap_irq_chip *regmap_irq_chip;
struct regmap_irq_chip_data *irq_data;
int type;
int irq;
int irq_mode;
unsigned long wu_flag;
spinlock_t lock;
};
struct pm80x_platform_data {
struct pm80x_rtc_pdata *rtc;
/*
* For the regulator not defined, set regulators[not_defined] to be
* NULL. num_regulators are the number of regulators supposed to be
* initialized. If all regulators are not defined, set num_regulators
* to be 0.
*/
struct regulator_init_data *regulators[PM800_ID_RG_MAX];
unsigned int num_regulators;
int irq_mode; /* Clear interrupt by read/write(0/1) */
int batt_det; /* enable/disable */
int (*plat_config)(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata);
};
extern const struct dev_pm_ops pm80x_pm_ops;
extern const struct regmap_config pm80x_regmap_config;
static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
irq_handler_t handler, unsigned long flags,
const char *name, void *data)
{
if (!pm80x->irq_data)
return -EINVAL;
return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
NULL, handler, flags, name, data);
}
static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
{
if (!pm80x->irq_data)
return;
free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
}
#ifdef CONFIG_PM
static inline int pm80x_dev_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
int irq = platform_get_irq(pdev, 0);
if (device_may_wakeup(dev))
set_bit(irq, &chip->wu_flag);
return 0;
}
static inline int pm80x_dev_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
int irq = platform_get_irq(pdev, 0);
if (device_may_wakeup(dev))
clear_bit(irq, &chip->wu_flag);
return 0;
}
#endif
extern int pm80x_init(struct i2c_client *client);
extern int pm80x_deinit(void);
#endif /* __LINUX_MFD_88PM80X_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/88pm860x.h
+478
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@@ -0,0 +1,478 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell 88PM860x Interface
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <haojian.zhuang@marvell.com>
*/
#ifndef __LINUX_MFD_88PM860X_H
#define __LINUX_MFD_88PM860X_H
#include <linux/interrupt.h>
#define MFD_NAME_SIZE (40)
enum {
CHIP_INVALID = 0,
CHIP_PM8606,
CHIP_PM8607,
CHIP_MAX,
};
enum {
PM8606_ID_INVALID,
PM8606_ID_BACKLIGHT,
PM8606_ID_LED,
PM8606_ID_VIBRATOR,
PM8606_ID_TOUCH,
PM8606_ID_SOUND,
PM8606_ID_CHARGER,
PM8606_ID_MAX,
};
/* 8606 Registers */
#define PM8606_DCM_BOOST (0x00)
#define PM8606_PWM (0x01)
#define PM8607_MISC2 (0x42)
/* Power Up Log Register */
#define PM8607_POWER_UP_LOG (0x3F)
/* Charger Control Registers */
#define PM8607_CCNT (0x47)
#define PM8607_CHG_CTRL1 (0x48)
#define PM8607_CHG_CTRL2 (0x49)
#define PM8607_CHG_CTRL3 (0x4A)
#define PM8607_CHG_CTRL4 (0x4B)
#define PM8607_CHG_CTRL5 (0x4C)
#define PM8607_CHG_CTRL6 (0x4D)
#define PM8607_CHG_CTRL7 (0x4E)
/* Backlight Registers */
#define PM8606_WLED1A (0x02)
#define PM8606_WLED1B (0x03)
#define PM8606_WLED2A (0x04)
#define PM8606_WLED2B (0x05)
#define PM8606_WLED3A (0x06)
#define PM8606_WLED3B (0x07)
/* LED Registers */
#define PM8606_RGB2A (0x08)
#define PM8606_RGB2B (0x09)
#define PM8606_RGB2C (0x0A)
#define PM8606_RGB2D (0x0B)
#define PM8606_RGB1A (0x0C)
#define PM8606_RGB1B (0x0D)
#define PM8606_RGB1C (0x0E)
#define PM8606_RGB1D (0x0F)
#define PM8606_PREREGULATORA (0x10)
#define PM8606_PREREGULATORB (0x11)
#define PM8606_VIBRATORA (0x12)
#define PM8606_VIBRATORB (0x13)
#define PM8606_VCHG (0x14)
#define PM8606_VSYS (0x15)
#define PM8606_MISC (0x16)
#define PM8606_CHIP_ID (0x17)
#define PM8606_STATUS (0x18)
#define PM8606_FLAGS (0x19)
#define PM8606_PROTECTA (0x1A)
#define PM8606_PROTECTB (0x1B)
#define PM8606_PROTECTC (0x1C)
/* Bit definitions of PM8606 registers */
#define PM8606_DCM_500MA (0x0) /* current limit */
#define PM8606_DCM_750MA (0x1)
#define PM8606_DCM_1000MA (0x2)
#define PM8606_DCM_1250MA (0x3)
#define PM8606_DCM_250MV (0x0 << 2)
#define PM8606_DCM_300MV (0x1 << 2)
#define PM8606_DCM_350MV (0x2 << 2)
#define PM8606_DCM_400MV (0x3 << 2)
#define PM8606_PWM_31200HZ (0x0)
#define PM8606_PWM_15600HZ (0x1)
#define PM8606_PWM_7800HZ (0x2)
#define PM8606_PWM_3900HZ (0x3)
#define PM8606_PWM_1950HZ (0x4)
#define PM8606_PWM_976HZ (0x5)
#define PM8606_PWM_488HZ (0x6)
#define PM8606_PWM_244HZ (0x7)
#define PM8606_PWM_FREQ_MASK (0x7)
#define PM8606_WLED_ON (1 << 0)
#define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1)
#define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5)
#define PM8606_VSYS_EN (1 << 1)
#define PM8606_MISC_OSC_EN (1 << 4)
enum {
PM8607_ID_BUCK1 = 0,
PM8607_ID_BUCK2,
PM8607_ID_BUCK3,
PM8607_ID_LDO1,
PM8607_ID_LDO2,
PM8607_ID_LDO3,
PM8607_ID_LDO4,
PM8607_ID_LDO5,
PM8607_ID_LDO6,
PM8607_ID_LDO7,
PM8607_ID_LDO8,
PM8607_ID_LDO9,
PM8607_ID_LDO10,
PM8607_ID_LDO11,
PM8607_ID_LDO12,
PM8607_ID_LDO13,
PM8607_ID_LDO14,
PM8607_ID_LDO15,
PM8606_ID_PREG,
PM8607_ID_RG_MAX,
};
/* 8607 chip ID is 0x40 or 0x50 */
#define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */
/* Interrupt Registers */
#define PM8607_STATUS_1 (0x01)
#define PM8607_STATUS_2 (0x02)
#define PM8607_INT_STATUS1 (0x03)
#define PM8607_INT_STATUS2 (0x04)
#define PM8607_INT_STATUS3 (0x05)
#define PM8607_INT_MASK_1 (0x06)
#define PM8607_INT_MASK_2 (0x07)
#define PM8607_INT_MASK_3 (0x08)
/* Regulator Control Registers */
#define PM8607_LDO1 (0x10)
#define PM8607_LDO2 (0x11)
#define PM8607_LDO3 (0x12)
#define PM8607_LDO4 (0x13)
#define PM8607_LDO5 (0x14)
#define PM8607_LDO6 (0x15)
#define PM8607_LDO7 (0x16)
#define PM8607_LDO8 (0x17)
#define PM8607_LDO9 (0x18)
#define PM8607_LDO10 (0x19)
#define PM8607_LDO12 (0x1A)
#define PM8607_LDO14 (0x1B)
#define PM8607_SLEEP_MODE1 (0x1C)
#define PM8607_SLEEP_MODE2 (0x1D)
#define PM8607_SLEEP_MODE3 (0x1E)
#define PM8607_SLEEP_MODE4 (0x1F)
#define PM8607_GO (0x20)
#define PM8607_SLEEP_BUCK1 (0x21)
#define PM8607_SLEEP_BUCK2 (0x22)
#define PM8607_SLEEP_BUCK3 (0x23)
#define PM8607_BUCK1 (0x24)
#define PM8607_BUCK2 (0x25)
#define PM8607_BUCK3 (0x26)
#define PM8607_BUCK_CONTROLS (0x27)
#define PM8607_SUPPLIES_EN11 (0x2B)
#define PM8607_SUPPLIES_EN12 (0x2C)
#define PM8607_GROUP1 (0x2D)
#define PM8607_GROUP2 (0x2E)
#define PM8607_GROUP3 (0x2F)
#define PM8607_GROUP4 (0x30)
#define PM8607_GROUP5 (0x31)
#define PM8607_GROUP6 (0x32)
#define PM8607_SUPPLIES_EN21 (0x33)
#define PM8607_SUPPLIES_EN22 (0x34)
/* Vibrator Control Registers */
#define PM8607_VIBRATOR_SET (0x28)
#define PM8607_VIBRATOR_PWM (0x29)
/* GPADC Registers */
#define PM8607_GP_BIAS1 (0x4F)
#define PM8607_MEAS_EN1 (0x50)
#define PM8607_MEAS_EN2 (0x51)
#define PM8607_MEAS_EN3 (0x52)
#define PM8607_MEAS_OFF_TIME1 (0x53)
#define PM8607_MEAS_OFF_TIME2 (0x54)
#define PM8607_TSI_PREBIAS (0x55) /* prebias time */
#define PM8607_PD_PREBIAS (0x56) /* prebias time */
#define PM8607_GPADC_MISC1 (0x57)
/* bit definitions of MEAS_EN1*/
#define PM8607_MEAS_EN1_VBAT (1 << 0)
#define PM8607_MEAS_EN1_VCHG (1 << 1)
#define PM8607_MEAS_EN1_VSYS (1 << 2)
#define PM8607_MEAS_EN1_TINT (1 << 3)
#define PM8607_MEAS_EN1_RFTMP (1 << 4)
#define PM8607_MEAS_EN1_TBAT (1 << 5)
#define PM8607_MEAS_EN1_GPADC2 (1 << 6)
#define PM8607_MEAS_EN1_GPADC3 (1 << 7)
/* Battery Monitor Registers */
#define PM8607_GP_BIAS2 (0x5A)
#define PM8607_VBAT_LOWTH (0x5B)
#define PM8607_VCHG_LOWTH (0x5C)
#define PM8607_VSYS_LOWTH (0x5D)
#define PM8607_TINT_LOWTH (0x5E)
#define PM8607_GPADC0_LOWTH (0x5F)
#define PM8607_GPADC1_LOWTH (0x60)
#define PM8607_GPADC2_LOWTH (0x61)
#define PM8607_GPADC3_LOWTH (0x62)
#define PM8607_VBAT_HIGHTH (0x63)
#define PM8607_VCHG_HIGHTH (0x64)
#define PM8607_VSYS_HIGHTH (0x65)
#define PM8607_TINT_HIGHTH (0x66)
#define PM8607_GPADC0_HIGHTH (0x67)
#define PM8607_GPADC1_HIGHTH (0x68)
#define PM8607_GPADC2_HIGHTH (0x69)
#define PM8607_GPADC3_HIGHTH (0x6A)
#define PM8607_IBAT_MEAS1 (0x6B)
#define PM8607_IBAT_MEAS2 (0x6C)
#define PM8607_VBAT_MEAS1 (0x6D)
#define PM8607_VBAT_MEAS2 (0x6E)
#define PM8607_VCHG_MEAS1 (0x6F)
#define PM8607_VCHG_MEAS2 (0x70)
#define PM8607_VSYS_MEAS1 (0x71)
#define PM8607_VSYS_MEAS2 (0x72)
#define PM8607_TINT_MEAS1 (0x73)
#define PM8607_TINT_MEAS2 (0x74)
#define PM8607_GPADC0_MEAS1 (0x75)
#define PM8607_GPADC0_MEAS2 (0x76)
#define PM8607_GPADC1_MEAS1 (0x77)
#define PM8607_GPADC1_MEAS2 (0x78)
#define PM8607_GPADC2_MEAS1 (0x79)
#define PM8607_GPADC2_MEAS2 (0x7A)
#define PM8607_GPADC3_MEAS1 (0x7B)
#define PM8607_GPADC3_MEAS2 (0x7C)
#define PM8607_CCNT_MEAS1 (0x95)
#define PM8607_CCNT_MEAS2 (0x96)
#define PM8607_VBAT_AVG (0x97)
#define PM8607_VCHG_AVG (0x98)
#define PM8607_VSYS_AVG (0x99)
#define PM8607_VBAT_MIN (0x9A)
#define PM8607_VCHG_MIN (0x9B)
#define PM8607_VSYS_MIN (0x9C)
#define PM8607_VBAT_MAX (0x9D)
#define PM8607_VCHG_MAX (0x9E)
#define PM8607_VSYS_MAX (0x9F)
#define PM8607_GPADC_MISC2 (0x59)
#define PM8607_GPADC0_GP_BIAS_A0 (1 << 0)
#define PM8607_GPADC1_GP_BIAS_A1 (1 << 1)
#define PM8607_GPADC2_GP_BIAS_A2 (1 << 2)
#define PM8607_GPADC3_GP_BIAS_A3 (1 << 3)
#define PM8607_GPADC2_GP_BIAS_OUT2 (1 << 6)
/* RTC Control Registers */
#define PM8607_RTC1 (0xA0)
#define PM8607_RTC_COUNTER1 (0xA1)
#define PM8607_RTC_COUNTER2 (0xA2)
#define PM8607_RTC_COUNTER3 (0xA3)
#define PM8607_RTC_COUNTER4 (0xA4)
#define PM8607_RTC_EXPIRE1 (0xA5)
#define PM8607_RTC_EXPIRE2 (0xA6)
#define PM8607_RTC_EXPIRE3 (0xA7)
#define PM8607_RTC_EXPIRE4 (0xA8)
#define PM8607_RTC_TRIM1 (0xA9)
#define PM8607_RTC_TRIM2 (0xAA)
#define PM8607_RTC_TRIM3 (0xAB)
#define PM8607_RTC_TRIM4 (0xAC)
#define PM8607_RTC_MISC1 (0xAD)
#define PM8607_RTC_MISC2 (0xAE)
#define PM8607_RTC_MISC3 (0xAF)
/* Misc Registers */
#define PM8607_CHIP_ID (0x00)
#define PM8607_B0_MISC1 (0x0C)
#define PM8607_LDO1 (0x10)
#define PM8607_DVC3 (0x26)
#define PM8607_A1_MISC1 (0x40)
/* bit definitions of Status Query Interface */
#define PM8607_STATUS_CC (1 << 3)
#define PM8607_STATUS_PEN (1 << 4)
#define PM8607_STATUS_HEADSET (1 << 5)
#define PM8607_STATUS_HOOK (1 << 6)
#define PM8607_STATUS_MICIN (1 << 7)
#define PM8607_STATUS_ONKEY (1 << 8)
#define PM8607_STATUS_EXTON (1 << 9)
#define PM8607_STATUS_CHG (1 << 10)
#define PM8607_STATUS_BAT (1 << 11)
#define PM8607_STATUS_VBUS (1 << 12)
#define PM8607_STATUS_OV (1 << 13)
/* bit definitions of BUCK3 */
#define PM8607_BUCK3_DOUBLE (1 << 6)
/* bit definitions of Misc1 */
#define PM8607_A1_MISC1_PI2C (1 << 0)
#define PM8607_B0_MISC1_INV_INT (1 << 0)
#define PM8607_B0_MISC1_INT_CLEAR (1 << 1)
#define PM8607_B0_MISC1_INT_MASK (1 << 2)
#define PM8607_B0_MISC1_PI2C (1 << 3)
#define PM8607_B0_MISC1_RESET (1 << 6)
/* bits definitions of GPADC */
#define PM8607_GPADC_EN (1 << 0)
#define PM8607_GPADC_PREBIAS_MASK (3 << 1)
#define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */
#define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */
#define PM8607_GPADC_SW_CAL_MASK (1 << 7)
#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
#define PM8607_PD_PRECHG_MASK (7 << 5)
#define PM8606_REF_GP_OSC_OFF 0
#define PM8606_REF_GP_OSC_ON 1
#define PM8606_REF_GP_OSC_UNKNOWN 2
/* Clients of reference group and 8MHz oscillator in 88PM8606 */
enum pm8606_ref_gp_and_osc_clients {
REF_GP_NO_CLIENTS = 0,
WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/
WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/
WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/
RGB1_ENABLE = (1<<3), /*PF 0x07.1*/
RGB2_ENABLE = (1<<4), /*PF 0x07.2*/
LDO_VBR_EN = (1<<5), /*PF 0x12.0*/
REF_GP_MAX_CLIENT = 0xFFFF
};
/* Interrupt Number in 88PM8607 */
enum {
PM8607_IRQ_ONKEY,
PM8607_IRQ_EXTON,
PM8607_IRQ_CHG,
PM8607_IRQ_BAT,
PM8607_IRQ_RTC,
PM8607_IRQ_CC,
PM8607_IRQ_VBAT,
PM8607_IRQ_VCHG,
PM8607_IRQ_VSYS,
PM8607_IRQ_TINT,
PM8607_IRQ_GPADC0,
PM8607_IRQ_GPADC1,
PM8607_IRQ_GPADC2,
PM8607_IRQ_GPADC3,
PM8607_IRQ_AUDIO_SHORT,
PM8607_IRQ_PEN,
PM8607_IRQ_HEADSET,
PM8607_IRQ_HOOK,
PM8607_IRQ_MICIN,
PM8607_IRQ_CHG_FAIL,
PM8607_IRQ_CHG_DONE,
PM8607_IRQ_CHG_FAULT,
};
enum {
PM8607_CHIP_A0 = 0x40,
PM8607_CHIP_A1 = 0x41,
PM8607_CHIP_B0 = 0x48,
};
struct pm860x_chip {
struct device *dev;
struct mutex irq_lock;
struct mutex osc_lock;
struct i2c_client *client;
struct i2c_client *companion; /* companion chip client */
struct regmap *regmap;
struct regmap *regmap_companion;
int buck3_double; /* DVC ramp slope double */
int companion_addr;
unsigned short osc_vote;
int id;
int irq_mode;
int irq_base;
int core_irq;
unsigned char chip_version;
unsigned char osc_status;
unsigned int wakeup_flag;
};
enum {
GI2C_PORT = 0,
PI2C_PORT,
};
struct pm860x_backlight_pdata {
int pwm;
int iset;
};
struct pm860x_led_pdata {
int iset;
};
struct pm860x_rtc_pdata {
int (*sync)(unsigned int ticks);
int vrtc;
};
struct pm860x_touch_pdata {
int gpadc_prebias;
int slot_cycle;
int off_scale;
int sw_cal;
int tsi_prebias; /* time, slot */
int pen_prebias; /* time, slot */
int pen_prechg; /* time, slot */
int res_x; /* resistor of Xplate */
unsigned long flags;
};
struct pm860x_power_pdata {
int max_capacity;
int resistor;
};
struct pm860x_platform_data {
struct pm860x_backlight_pdata *backlight;
struct pm860x_led_pdata *led;
struct pm860x_rtc_pdata *rtc;
struct pm860x_touch_pdata *touch;
struct pm860x_power_pdata *power;
struct regulator_init_data *buck1;
struct regulator_init_data *buck2;
struct regulator_init_data *buck3;
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldo8;
struct regulator_init_data *ldo9;
struct regulator_init_data *ldo10;
struct regulator_init_data *ldo12;
struct regulator_init_data *ldo_vibrator;
struct regulator_init_data *ldo14;
struct charger_desc *chg_desc;
int companion_addr; /* I2C address of companion chip */
int i2c_port; /* Controlled by GI2C or PI2C */
int irq_mode; /* Clear interrupt by read/write(0/1) */
int irq_base; /* IRQ base number of 88pm860x */
int num_leds;
int num_backlights;
};
extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
extern int pm860x_reg_read(struct i2c_client *, int);
extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_page_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_page_bulk_read(struct i2c_client *, int, int,
unsigned char *);
#endif /* __LINUX_MFD_88PM860X_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/88pm886.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __MFD_88PM886_H
#define __MFD_88PM886_H
#include <linux/i2c.h>
#include <linux/regmap.h>
#define PM886_A1_CHIP_ID 0xa1
#define PM886_IRQ_ONKEY 0
#define PM886_PAGE_OFFSET_REGULATORS 1
#define PM886_PAGE_OFFSET_GPADC 2
#define PM886_REG_ID 0x00
#define PM886_REG_STATUS1 0x01
#define PM886_ONKEY_STS1 BIT(0)
#define PM886_REG_INT_STATUS1 0x05
#define PM886_REG_INT_ENA_1 0x0a
#define PM886_INT_ENA1_ONKEY BIT(0)
#define PM886_REG_MISC_CONFIG1 0x14
#define PM886_SW_PDOWN BIT(5)
#define PM886_REG_MISC_CONFIG2 0x15
#define PM886_INT_INV BIT(0)
#define PM886_INT_CLEAR BIT(1)
#define PM886_INT_RC 0x00
#define PM886_INT_WC BIT(1)
#define PM886_INT_MASK_MODE BIT(2)
#define PM886_REG_RTC_CNT1 0xd1
#define PM886_REG_RTC_CNT2 0xd2
#define PM886_REG_RTC_CNT3 0xd3
#define PM886_REG_RTC_CNT4 0xd4
#define PM886_REG_RTC_SPARE1 0xea
#define PM886_REG_RTC_SPARE2 0xeb
#define PM886_REG_RTC_SPARE3 0xec
#define PM886_REG_RTC_SPARE4 0xed
#define PM886_REG_RTC_SPARE5 0xee
#define PM886_REG_RTC_SPARE6 0xef
#define PM886_REG_BUCK_EN 0x08
#define PM886_REG_LDO_EN1 0x09
#define PM886_REG_LDO_EN2 0x0a
#define PM886_REG_LDO1_VOUT 0x20
#define PM886_REG_LDO2_VOUT 0x26
#define PM886_REG_LDO3_VOUT 0x2c
#define PM886_REG_LDO4_VOUT 0x32
#define PM886_REG_LDO5_VOUT 0x38
#define PM886_REG_LDO6_VOUT 0x3e
#define PM886_REG_LDO7_VOUT 0x44
#define PM886_REG_LDO8_VOUT 0x4a
#define PM886_REG_LDO9_VOUT 0x50
#define PM886_REG_LDO10_VOUT 0x56
#define PM886_REG_LDO11_VOUT 0x5c
#define PM886_REG_LDO12_VOUT 0x62
#define PM886_REG_LDO13_VOUT 0x68
#define PM886_REG_LDO14_VOUT 0x6e
#define PM886_REG_LDO15_VOUT 0x74
#define PM886_REG_LDO16_VOUT 0x7a
#define PM886_REG_BUCK1_VOUT 0xa5
#define PM886_REG_BUCK2_VOUT 0xb3
#define PM886_REG_BUCK3_VOUT 0xc1
#define PM886_REG_BUCK4_VOUT 0xcf
#define PM886_REG_BUCK5_VOUT 0xdd
#define PM886_LDO_VSEL_MASK 0x0f
#define PM886_BUCK_VSEL_MASK 0x7f
/* GPADC enable/disable registers */
#define PM886_REG_GPADC_CONFIG(n) (n)
#define PM886_GPADC_VSC_EN BIT(0)
#define PM886_GPADC_VBAT_EN BIT(1)
#define PM886_GPADC_GNDDET1_EN BIT(3)
#define PM886_GPADC_VBUS_EN BIT(4)
#define PM886_GPADC_VCHG_PWR_EN BIT(5)
#define PM886_GPADC_VCF_OUT_EN BIT(6)
#define PM886_GPADC_CONFIG1_EN_ALL \
(PM886_GPADC_VSC_EN | \
PM886_GPADC_VBAT_EN | \
PM886_GPADC_GNDDET1_EN | \
PM886_GPADC_VBUS_EN | \
PM886_GPADC_VCHG_PWR_EN | \
PM886_GPADC_VCF_OUT_EN)
#define PM886_GPADC_TINT_EN BIT(0)
#define PM886_GPADC_PMODE_EN BIT(1)
#define PM886_GPADC_GPADC0_EN BIT(2)
#define PM886_GPADC_GPADC1_EN BIT(3)
#define PM886_GPADC_GPADC2_EN BIT(4)
#define PM886_GPADC_GPADC3_EN BIT(5)
#define PM886_GPADC_MIC_DET_EN BIT(6)
#define PM886_GPADC_CONFIG2_EN_ALL \
(PM886_GPADC_TINT_EN | \
PM886_GPADC_GPADC0_EN | \
PM886_GPADC_GPADC1_EN | \
PM886_GPADC_GPADC2_EN | \
PM886_GPADC_GPADC3_EN | \
PM886_GPADC_MIC_DET_EN)
/* No CONFIG3_EN_ALL because this is the only bit there. */
#define PM886_GPADC_GND_DET2_EN BIT(0)
/* GPADC channel registers */
#define PM886_REG_GPADC_VSC 0x40
#define PM886_REG_GPADC_VCHG_PWR 0x4c
#define PM886_REG_GPADC_VCF_OUT 0x4e
#define PM886_REG_GPADC_TINT 0x50
#define PM886_REG_GPADC_GPADC0 0x54
#define PM886_REG_GPADC_GPADC1 0x56
#define PM886_REG_GPADC_GPADC2 0x58
#define PM886_REG_GPADC_VBAT 0xa0
#define PM886_REG_GPADC_GND_DET1 0xa4
#define PM886_REG_GPADC_GND_DET2 0xa6
#define PM886_REG_GPADC_VBUS 0xa8
#define PM886_REG_GPADC_GPADC3 0xaa
#define PM886_REG_GPADC_MIC_DET 0xac
#define PM886_REG_GPADC_VBAT_SLP 0xb0
/* VBAT_SLP is the last register and is 2 bytes wide like other channels. */
#define PM886_GPADC_MAX_REGISTER (PM886_REG_GPADC_VBAT_SLP + 1)
#define PM886_GPADC_BIAS_LEVELS 16
#define PM886_GPADC_INDEX_TO_BIAS_uA(i) (1 + (i) * 5)
struct pm886_chip {
struct i2c_client *client;
unsigned int chip_id;
struct regmap *regmap;
};
#endif /* __MFD_88PM886_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/aat2870.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/include/linux/mfd/aat2870.h
*
* Copyright (c) 2011, NVIDIA Corporation.
* Author: Jin Park <jinyoungp@nvidia.com>
*/
#ifndef __LINUX_MFD_AAT2870_H
#define __LINUX_MFD_AAT2870_H
#include <linux/debugfs.h>
#include <linux/i2c.h>
/* Register offsets */
#define AAT2870_BL_CH_EN 0x00
#define AAT2870_BLM 0x01
#define AAT2870_BLS 0x02
#define AAT2870_BL1 0x03
#define AAT2870_BL2 0x04
#define AAT2870_BL3 0x05
#define AAT2870_BL4 0x06
#define AAT2870_BL5 0x07
#define AAT2870_BL6 0x08
#define AAT2870_BL7 0x09
#define AAT2870_BL8 0x0A
#define AAT2870_FLR 0x0B
#define AAT2870_FM 0x0C
#define AAT2870_FS 0x0D
#define AAT2870_ALS_CFG0 0x0E
#define AAT2870_ALS_CFG1 0x0F
#define AAT2870_ALS_CFG2 0x10
#define AAT2870_AMB 0x11
#define AAT2870_ALS0 0x12
#define AAT2870_ALS1 0x13
#define AAT2870_ALS2 0x14
#define AAT2870_ALS3 0x15
#define AAT2870_ALS4 0x16
#define AAT2870_ALS5 0x17
#define AAT2870_ALS6 0x18
#define AAT2870_ALS7 0x19
#define AAT2870_ALS8 0x1A
#define AAT2870_ALS9 0x1B
#define AAT2870_ALSA 0x1C
#define AAT2870_ALSB 0x1D
#define AAT2870_ALSC 0x1E
#define AAT2870_ALSD 0x1F
#define AAT2870_ALSE 0x20
#define AAT2870_ALSF 0x21
#define AAT2870_SUB_SET 0x22
#define AAT2870_SUB_CTRL 0x23
#define AAT2870_LDO_AB 0x24
#define AAT2870_LDO_CD 0x25
#define AAT2870_LDO_EN 0x26
#define AAT2870_REG_NUM 0x27
/* Device IDs */
enum aat2870_id {
AAT2870_ID_BL,
AAT2870_ID_LDOA,
AAT2870_ID_LDOB,
AAT2870_ID_LDOC,
AAT2870_ID_LDOD
};
/* Backlight channels */
#define AAT2870_BL_CH1 0x01
#define AAT2870_BL_CH2 0x02
#define AAT2870_BL_CH3 0x04
#define AAT2870_BL_CH4 0x08
#define AAT2870_BL_CH5 0x10
#define AAT2870_BL_CH6 0x20
#define AAT2870_BL_CH7 0x40
#define AAT2870_BL_CH8 0x80
#define AAT2870_BL_CH_ALL 0xFF
/* Backlight current magnitude (mA) */
enum aat2870_current {
AAT2870_CURRENT_0_45 = 1,
AAT2870_CURRENT_0_90,
AAT2870_CURRENT_1_80,
AAT2870_CURRENT_2_70,
AAT2870_CURRENT_3_60,
AAT2870_CURRENT_4_50,
AAT2870_CURRENT_5_40,
AAT2870_CURRENT_6_30,
AAT2870_CURRENT_7_20,
AAT2870_CURRENT_8_10,
AAT2870_CURRENT_9_00,
AAT2870_CURRENT_9_90,
AAT2870_CURRENT_10_8,
AAT2870_CURRENT_11_7,
AAT2870_CURRENT_12_6,
AAT2870_CURRENT_13_5,
AAT2870_CURRENT_14_4,
AAT2870_CURRENT_15_3,
AAT2870_CURRENT_16_2,
AAT2870_CURRENT_17_1,
AAT2870_CURRENT_18_0,
AAT2870_CURRENT_18_9,
AAT2870_CURRENT_19_8,
AAT2870_CURRENT_20_7,
AAT2870_CURRENT_21_6,
AAT2870_CURRENT_22_5,
AAT2870_CURRENT_23_4,
AAT2870_CURRENT_24_3,
AAT2870_CURRENT_25_2,
AAT2870_CURRENT_26_1,
AAT2870_CURRENT_27_0,
AAT2870_CURRENT_27_9
};
struct aat2870_register {
bool readable;
bool writeable;
u8 value;
};
struct aat2870_data {
struct device *dev;
struct i2c_client *client;
struct mutex io_lock;
struct aat2870_register *reg_cache; /* register cache */
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
bool is_enable;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
/* i2c io funcntions */
int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
};
struct aat2870_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct aat2870_platform_data {
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
struct aat2870_subdev_info *subdevs;
int num_subdevs;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
};
struct aat2870_bl_platform_data {
/* backlight channels, default is AAT2870_BL_CH_ALL */
int channels;
/* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
int max_current;
/* maximum brightness, default is 255 */
int max_brightness;
};
#endif /* __LINUX_MFD_AAT2870_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/abx500.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2007-2009 ST-Ericsson AB
*
* ABX500 core access functions.
* The abx500 interface is used for the Analog Baseband chips.
*
* Author: Mattias Wallin <mattias.wallin@stericsson.com>
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
* Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_ABX500_H
#define MFD_ABX500_H
/**
* struct abx500_init_setting
* Initial value of the registers for driver to use during setup.
*/
struct abx500_init_settings {
u8 bank;
u8 reg;
u8 setting;
};
int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 value);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 *value);
int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
/**
* abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
* target register
*
* @dev: The AB sub device.
* @bank: The i2c bank number.
* @bitmask: The bit mask to use.
* @bitvalues: The new bit values.
*
* Updates the value of an AB register:
* value -> ((value & ~bitmask) | (bitvalues & bitmask))
*/
int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
u8 reg, u8 bitmask, u8 bitvalues);
int abx500_get_chip_id(struct device *dev);
int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
struct abx500_ops {
int (*get_chip_id) (struct device *);
int (*get_register) (struct device *, u8, u8, u8 *);
int (*set_register) (struct device *, u8, u8, u8);
int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
int (*event_registers_startup_state_get) (struct device *, u8 *);
int (*startup_irq_enabled) (struct device *, unsigned int);
void (*dump_all_banks) (struct device *);
};
int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
void abx500_remove_ops(struct device *dev);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/abx500/ab8500-codec.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Ola Lilja <ola.o.lilja@stericsson.com>
* for ST-Ericsson.
*
* License terms:
*/
#ifndef AB8500_CORE_CODEC_H
#define AB8500_CORE_CODEC_H
/* Mic-types */
enum amic_type {
AMIC_TYPE_SINGLE_ENDED,
AMIC_TYPE_DIFFERENTIAL
};
/* Mic-biases */
enum amic_micbias {
AMIC_MICBIAS_VAMIC1,
AMIC_MICBIAS_VAMIC2,
AMIC_MICBIAS_UNKNOWN
};
/* Bias-voltage */
enum ear_cm_voltage {
EAR_CMV_0_95V,
EAR_CMV_1_10V,
EAR_CMV_1_27V,
EAR_CMV_1_58V,
EAR_CMV_UNKNOWN
};
/* Analog microphone settings */
struct amic_settings {
enum amic_type mic1_type;
enum amic_type mic2_type;
enum amic_micbias mic1a_micbias;
enum amic_micbias mic1b_micbias;
enum amic_micbias mic2_micbias;
};
/* Platform data structure for the audio-parts of the AB8500 */
struct ab8500_codec_platform_data {
struct amic_settings amics;
enum ear_cm_voltage ear_cmv;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/abx500/ab8500-sysctrl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2010
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
*/
#ifndef __AB8500_SYSCTRL_H
#define __AB8500_SYSCTRL_H
#include <linux/bitops.h>
#ifdef CONFIG_AB8500_CORE
int ab8500_sysctrl_read(u16 reg, u8 *value);
int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
#else
static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
{
return 0;
}
static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
{
return 0;
}
#endif /* CONFIG_AB8500_CORE */
static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, bits);
}
static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, 0);
}
/* Registers */
#define AB8500_TURNONSTATUS 0x100
#define AB8500_RESETSTATUS 0x101
#define AB8500_PONKEY1PRESSSTATUS 0x102
#define AB8500_SYSCLKREQSTATUS 0x142
#define AB8500_STW4500CTRL1 0x180
#define AB8500_STW4500CTRL2 0x181
#define AB8500_STW4500CTRL3 0x200
#define AB8500_MAINWDOGCTRL 0x201
#define AB8500_MAINWDOGTIMER 0x202
#define AB8500_LOWBAT 0x203
#define AB8500_BATTOK 0x204
#define AB8500_SYSCLKTIMER 0x205
#define AB8500_SMPSCLKCTRL 0x206
#define AB8500_SMPSCLKSEL1 0x207
#define AB8500_SMPSCLKSEL2 0x208
#define AB8500_SMPSCLKSEL3 0x209
#define AB8500_SYSULPCLKCONF 0x20A
#define AB8500_SYSULPCLKCTRL1 0x20B
#define AB8500_SYSCLKCTRL 0x20C
#define AB8500_SYSCLKREQ1VALID 0x20D
#define AB8500_SYSTEMCTRLSUP 0x20F
#define AB8500_SYSCLKREQ1RFCLKBUF 0x210
#define AB8500_SYSCLKREQ2RFCLKBUF 0x211
#define AB8500_SYSCLKREQ3RFCLKBUF 0x212
#define AB8500_SYSCLKREQ4RFCLKBUF 0x213
#define AB8500_SYSCLKREQ5RFCLKBUF 0x214
#define AB8500_SYSCLKREQ6RFCLKBUF 0x215
#define AB8500_SYSCLKREQ7RFCLKBUF 0x216
#define AB8500_SYSCLKREQ8RFCLKBUF 0x217
#define AB8500_DITHERCLKCTRL 0x220
#define AB8500_SWATCTRL 0x230
#define AB8500_HIQCLKCTRL 0x232
#define AB8500_VSIMSYSCLKCTRL 0x233
#define AB9540_SYSCLK12BUFCTRL 0x234
#define AB9540_SYSCLK12CONFCTRL 0x235
#define AB9540_SYSCLK12BUFCTRL2 0x236
#define AB9540_SYSCLK12BUF1VALID 0x237
#define AB9540_SYSCLK12BUF2VALID 0x238
#define AB9540_SYSCLK12BUF3VALID 0x239
#define AB9540_SYSCLK12BUF4VALID 0x23A
/* Bits */
#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
#define AB8500_STW4500CTRL1_SWOFF BIT(0)
#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
#define AB8500_STW4500CTRL3_THSDENA BIT(3)
#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
#define AB8500_LOWBAT_LOWBATENA BIT(0)
#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
#define AB8500_LOWBAT_LOWBAT_SHIFT 1
#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
#define AB8500_SWATCTRL_UPDATERF BIT(0)
#define AB8500_SWATCTRL_SWATENABLE BIT(1)
#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
#define AB8500_ENABLE_WD 0x1
#define AB8500_KICK_WD 0x2
#define AB8500_WD_RESTART_ON_EXPIRE 0x10
#endif /* __AB8500_SYSCTRL_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/abx500/ab8500.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
*/
#ifndef MFD_AB8500_H
#define MFD_AB8500_H
#include <linux/atomic.h>
#include <linux/mutex.h>
#include <linux/irqdomain.h>
struct device;
/*
* AB IC versions
*
* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
* print of version string.
*/
enum ab8500_version {
AB8500_VERSION_AB8500 = 0x0,
AB8500_VERSION_AB8505 = 0x1,
AB8500_VERSION_AB9540 = 0x2,
AB8500_VERSION_AB8540 = 0x4,
AB8500_VERSION_UNDEFINED,
};
/* AB8500 CIDs*/
#define AB8500_CUTEARLY 0x00
#define AB8500_CUT1P0 0x10
#define AB8500_CUT1P1 0x11
#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */
#define AB8500_CUT2P0 0x20
#define AB8500_CUT3P0 0x30
#define AB8500_CUT3P3 0x33
/*
* AB8500 bank addresses
*/
#define AB8500_M_FSM_RANK 0x0
#define AB8500_SYS_CTRL1_BLOCK 0x1
#define AB8500_SYS_CTRL2_BLOCK 0x2
#define AB8500_REGU_CTRL1 0x3
#define AB8500_REGU_CTRL2 0x4
#define AB8500_USB 0x5
#define AB8500_TVOUT 0x6
#define AB8500_DBI 0x7
#define AB8500_ECI_AV_ACC 0x8
#define AB8500_RESERVED 0x9
#define AB8500_GPADC 0xA
#define AB8500_CHARGER 0xB
#define AB8500_GAS_GAUGE 0xC
#define AB8500_AUDIO 0xD
#define AB8500_INTERRUPT 0xE
#define AB8500_RTC 0xF
#define AB8500_MISC 0x10
#define AB8500_DEVELOPMENT 0x11
#define AB8500_DEBUG 0x12
#define AB8500_PROD_TEST 0x13
#define AB8500_STE_TEST 0x14
#define AB8500_OTP_EMUL 0x15
#define AB8500_DEBUG_FIELD_LAST 0x16
/*
* Interrupts
* Values used to index into array ab8500_irq_regoffset[] defined in
* drivers/mdf/ab8500-core.c
*/
/* Definitions for AB8500, AB9540 and AB8540 */
/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */
#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */
#define AB8500_INT_TEMP_WARM 3
#define AB8500_INT_PON_KEY2DB_F 4
#define AB8500_INT_PON_KEY2DB_R 5
#define AB8500_INT_PON_KEY1DB_F 6
#define AB8500_INT_PON_KEY1DB_R 7
/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
#define AB8500_INT_BATT_OVV 8
#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */
#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */
#define AB8500_INT_VBUS_DET_F 14
#define AB8500_INT_VBUS_DET_R 15
/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
#define AB8500_INT_VBUS_CH_DROP_END 16
#define AB8500_INT_RTC_60S 17
#define AB8500_INT_RTC_ALARM 18
#define AB8540_INT_BIF_INT 19
#define AB8500_INT_BAT_CTRL_INDB 20
#define AB8500_INT_CH_WD_EXP 21
#define AB8500_INT_VBUS_OVV 22
#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */
/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
#define AB8500_INT_CCN_CONV_ACC 24
#define AB8500_INT_INT_AUD 25
#define AB8500_INT_CCEOC 26
#define AB8500_INT_CC_INT_CALIB 27
#define AB8500_INT_LOW_BAT_F 28
#define AB8500_INT_LOW_BAT_R 29
#define AB8500_INT_BUP_CHG_NOT_OK 30
#define AB8500_INT_BUP_CHG_OK 31
/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */
#define AB8500_INT_ACC_DETECT_1DB_F 33
#define AB8500_INT_ACC_DETECT_1DB_R 34
#define AB8500_INT_ACC_DETECT_22DB_F 35
#define AB8500_INT_ACC_DETECT_22DB_R 36
#define AB8500_INT_ACC_DETECT_21DB_F 37
#define AB8500_INT_ACC_DETECT_21DB_R 38
#define AB8500_INT_GP_SW_ADC_CONV_END 39
/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO10R 44 /* not 8540 */
#define AB8500_INT_GPIO11R 45 /* not 8540 */
#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */
#define AB8500_INT_GPIO13R 47 /* not 8540 */
/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */
#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */
#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40R 54 /* not 8540 */
#define AB8500_INT_GPIO41R 55 /* not 8540 */
/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
#define AB8500_INT_GPIO10F 60
#define AB8500_INT_GPIO11F 61
#define AB8500_INT_GPIO12F 62 /* not 8505 */
#define AB8500_INT_GPIO13F 63
/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */
#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */
#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40F 70 /* not 8540 */
#define AB8500_INT_GPIO41F 71 /* not 8540 */
/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
#define AB8500_INT_ADP_SOURCE_ERROR 72
#define AB8500_INT_ADP_SINK_ERROR 73
#define AB8500_INT_ADP_PROBE_PLUG 74
#define AB8500_INT_ADP_PROBE_UNPLUG 75
#define AB8500_INT_ADP_SENSE_OFF 76
#define AB8500_INT_USB_PHY_POWER_ERR 78
#define AB8500_INT_USB_LINK_STATUS 79
/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
#define AB8500_INT_BTEMP_LOW 80
#define AB8500_INT_BTEMP_LOW_MEDIUM 81
#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
#define AB8500_INT_BTEMP_HIGH 83
/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
#define AB8500_INT_SRP_DETECT 88
#define AB8500_INT_USB_CHARGER_NOT_OKR 89
#define AB8500_INT_ID_WAKEUP_R 90
#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1R 92
#define AB8500_INT_ID_DET_R2R 93
#define AB8500_INT_ID_DET_R3R 94
#define AB8500_INT_ID_DET_R4R 95
/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */
#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */
#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */
#define AB8500_INT_CHSTOPBYSEC 103
/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
#define AB8500_INT_USB_CH_TH_PROT_F 104
#define AB8500_INT_USB_CH_TH_PROT_R 105
#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
#define AB8500_INT_CHCURLIMNOHSCHIRP 109
#define AB8500_INT_CHCURLIMHSCHIRP 110
#define AB8500_INT_XTAL32K_KO 111
/* Definitions for AB9540 / AB8505 */
/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
#define AB9540_INT_GPIO50R 113 /* not 8540 */
#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */
#define AB9540_INT_GPIO52R 115 /* not 8540 */
#define AB9540_INT_GPIO53R 116 /* not 8540 */
#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_R 118
/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
#define AB9540_INT_GPIO50F 121 /* not 8540 */
#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */
#define AB9540_INT_GPIO52F 123 /* not 8540 */
#define AB9540_INT_GPIO53F 124 /* not 8540 */
#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_F 126
/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
#define AB8505_INT_KEYSTUCK 128
#define AB8505_INT_IKR 129
#define AB8505_INT_IKP 130
#define AB8505_INT_KP 131
#define AB8505_INT_KEYDEGLITCH 132
#define AB8505_INT_MODPWRSTATUSF 134
#define AB8505_INT_MODPWRSTATUSR 135
/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
#define AB8500_INT_HOOK_DET_NEG_F 138
#define AB8500_INT_HOOK_DET_NEG_R 139
#define AB8500_INT_HOOK_DET_POS_F 140
#define AB8500_INT_HOOK_DET_POS_R 141
#define AB8500_INT_PLUG_DET_COMP_F 142
#define AB8500_INT_PLUG_DET_COMP_R 143
/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
#define AB8505_INT_COLL 144
#define AB8505_INT_RESERR 145
#define AB8505_INT_FRAERR 146
#define AB8505_INT_COMERR 147
#define AB8505_INT_SPDSET 148
#define AB8505_INT_DSENT 149
#define AB8505_INT_DREC 150
#define AB8505_INT_ACC_INT 151
/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
#define AB8505_INT_NOPINT 152
/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
#define AB8540_INT_IDPLUGDETCOMPF 160
#define AB8540_INT_IDPLUGDETCOMPR 161
#define AB8540_INT_FMDETCOMPLOF 162
#define AB8540_INT_FMDETCOMPLOR 163
#define AB8540_INT_FMDETCOMPHIF 164
#define AB8540_INT_FMDETCOMPHIR 165
#define AB8540_INT_ID5VDETCOMPF 166
#define AB8540_INT_ID5VDETCOMPR 167
/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
#define AB8540_INT_GPIO43F 168
#define AB8540_INT_GPIO43R 169
#define AB8540_INT_GPIO44F 170
#define AB8540_INT_GPIO44R 171
#define AB8540_INT_KEYPOSDETCOMPF 172
#define AB8540_INT_KEYPOSDETCOMPR 173
#define AB8540_INT_KEYNEGDETCOMPF 174
#define AB8540_INT_KEYNEGDETCOMPR 175
/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
#define AB8540_INT_GPIO1VBATF 176
#define AB8540_INT_GPIO1VBATR 177
#define AB8540_INT_GPIO2VBATF 178
#define AB8540_INT_GPIO2VBATR 179
#define AB8540_INT_GPIO3VBATF 180
#define AB8540_INT_GPIO3VBATR 181
#define AB8540_INT_GPIO4VBATF 182
#define AB8540_INT_GPIO4VBATR 183
/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
#define AB8540_INT_SYSCLKREQ2F 184
#define AB8540_INT_SYSCLKREQ2R 185
#define AB8540_INT_SYSCLKREQ3F 186
#define AB8540_INT_SYSCLKREQ3R 187
#define AB8540_INT_SYSCLKREQ4F 188
#define AB8540_INT_SYSCLKREQ4R 189
#define AB8540_INT_SYSCLKREQ5F 190
#define AB8540_INT_SYSCLKREQ5R 191
/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
#define AB8540_INT_PWMOUT1F 192
#define AB8540_INT_PWMOUT1R 193
#define AB8540_INT_PWMCTRL0F 194
#define AB8540_INT_PWMCTRL0R 195
#define AB8540_INT_PWMCTRL1F 196
#define AB8540_INT_PWMCTRL1R 197
#define AB8540_INT_SYSCLKREQ6F 198
#define AB8540_INT_SYSCLKREQ6R 199
/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
#define AB8540_INT_PWMEXTVIBRA1F 200
#define AB8540_INT_PWMEXTVIBRA1R 201
#define AB8540_INT_PWMEXTVIBRA2F 202
#define AB8540_INT_PWMEXTVIBRA2R 203
#define AB8540_INT_PWMOUT2F 204
#define AB8540_INT_PWMOUT2R 205
#define AB8540_INT_PWMOUT3F 206
#define AB8540_INT_PWMOUT3R 207
/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
#define AB8540_INT_ADDATA2F 208
#define AB8540_INT_ADDATA2R 209
#define AB8540_INT_DADATA2F 210
#define AB8540_INT_DADATA2R 211
#define AB8540_INT_FSYNC2F 212
#define AB8540_INT_FSYNC2R 213
#define AB8540_INT_BITCLK2F 214
#define AB8540_INT_BITCLK2R 215
/* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */
#define AB8540_INT_RTC_1S 216
/*
* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
* entire platform. This is a "compile time" constant so this must be set to
* the largest possible value that may be encountered with different AB SOCs.
* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
* which is larger.
*/
#define AB8500_NR_IRQS 112
#define AB8505_NR_IRQS 153
#define AB9540_NR_IRQS 153
#define AB8540_NR_IRQS 216
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS
#define AB8500_NUM_IRQ_REGS 14
#define AB9540_NUM_IRQ_REGS 20
#define AB8540_NUM_IRQ_REGS 27
/* Turn On Status Event */
#define AB8500_POR_ON_VBAT 0x01
#define AB8500_POW_KEY_1_ON 0x02
#define AB8500_POW_KEY_2_ON 0x04
#define AB8500_RTC_ALARM 0x08
#define AB8500_MAIN_CH_DET 0x10
#define AB8500_VBUS_DET 0x20
#define AB8500_USB_ID_DET 0x40
/**
* struct ab8500 - ab8500 internal structure
* @dev: parent device
* @lock: read/write operations lock
* @irq_lock: genirq bus lock
* @transfer_ongoing: 0 if no transfer ongoing
* @irq: irq line
* @irq_domain: irq domain
* @version: chip version id (e.g. ab8500 or ab9540)
* @chip_id: chip revision id
* @write: register write
* @write_masked: masked register write
* @read: register read
* @rx_buf: rx buf for SPI
* @tx_buf: tx buf for SPI
* @mask: cache of IRQ regs for bus lock
* @oldmask: cache of previous IRQ regs for bus lock
* @mask_size: Actual number of valid entries in mask[], oldmask[] and
* irq_reg_offset
* @irq_reg_offset: Array of offsets into IRQ registers
*/
struct ab8500 {
struct device *dev;
struct mutex lock;
struct mutex irq_lock;
atomic_t transfer_ongoing;
int irq;
struct irq_domain *domain;
enum ab8500_version version;
u8 chip_id;
int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
int (*read)(struct ab8500 *ab8500, u16 addr);
unsigned long tx_buf[4];
unsigned long rx_buf[4];
u8 *mask;
u8 *oldmask;
int mask_size;
const int *irq_reg_offset;
int it_latchhier_num;
};
struct ab8500_codec_platform_data;
struct ab8500_sysctrl_platform_data;
/**
* struct ab8500_platform_data - AB8500 platform data
* @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
* @init: board-specific initialization after detection of ab8500
*/
struct ab8500_platform_data {
void (*init) (struct ab8500 *);
struct ab8500_codec_platform_data *codec;
struct ab8500_sysctrl_platform_data *sysctrl;
};
extern int ab8500_suspend(struct ab8500 *ab8500);
static inline int is_ab8500(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8500;
}
static inline int is_ab8505(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8505;
}
static inline int is_ab9540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB9540;
}
static inline int is_ab8540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8540;
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
}
static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}
static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
static inline int is_ab8505_2p0(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
}
static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
static inline int is_ab9540_2p0(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
}
/*
* Be careful, the marketing name for this chip is 2.1
* but the value read from the chip is 3.0 (0x30)
*/
static inline int is_ab9540_3p0(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
}
static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
}
static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
}
static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
}
static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
}
static inline int is_ab8540_2p0(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
}
static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
}
static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
}
void ab8500_override_turn_on_stat(u8 mask, u8 set);
static inline void ab8500_dump_all_banks(struct device *dev) {}
static inline void ab8500_debug_register_interrupt(int line) {}
#endif /* MFD_AB8500_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/ac100.h
+175
View File
@@ -0,0 +1,175 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Functions and registers to access AC100 codec / RTC combo IC.
*
* Copyright (C) 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*/
#ifndef __LINUX_MFD_AC100_H
#define __LINUX_MFD_AC100_H
#include <linux/regmap.h>
struct ac100_dev {
struct device *dev;
struct regmap *regmap;
};
/* Audio codec related registers */
#define AC100_CHIP_AUDIO_RST 0x00
#define AC100_PLL_CTRL1 0x01
#define AC100_PLL_CTRL2 0x02
#define AC100_SYSCLK_CTRL 0x03
#define AC100_MOD_CLK_ENA 0x04
#define AC100_MOD_RST_CTRL 0x05
#define AC100_I2S_SR_CTRL 0x06
/* I2S1 interface */
#define AC100_I2S1_CLK_CTRL 0x10
#define AC100_I2S1_SND_OUT_CTRL 0x11
#define AC100_I2S1_SND_IN_CTRL 0x12
#define AC100_I2S1_MXR_SRC 0x13
#define AC100_I2S1_VOL_CTRL1 0x14
#define AC100_I2S1_VOL_CTRL2 0x15
#define AC100_I2S1_VOL_CTRL3 0x16
#define AC100_I2S1_VOL_CTRL4 0x17
#define AC100_I2S1_MXR_GAIN 0x18
/* I2S2 interface */
#define AC100_I2S2_CLK_CTRL 0x20
#define AC100_I2S2_SND_OUT_CTRL 0x21
#define AC100_I2S2_SND_IN_CTRL 0x22
#define AC100_I2S2_MXR_SRC 0x23
#define AC100_I2S2_VOL_CTRL1 0x24
#define AC100_I2S2_VOL_CTRL2 0x25
#define AC100_I2S2_VOL_CTRL3 0x26
#define AC100_I2S2_VOL_CTRL4 0x27
#define AC100_I2S2_MXR_GAIN 0x28
/* I2S3 interface */
#define AC100_I2S3_CLK_CTRL 0x30
#define AC100_I2S3_SND_OUT_CTRL 0x31
#define AC100_I2S3_SND_IN_CTRL 0x32
#define AC100_I2S3_SIG_PATH_CTRL 0x33
/* ADC digital controls */
#define AC100_ADC_DIG_CTRL 0x40
#define AC100_ADC_VOL_CTRL 0x41
/* HMIC plug sensing / key detection */
#define AC100_HMIC_CTRL1 0x44
#define AC100_HMIC_CTRL2 0x45
#define AC100_HMIC_STATUS 0x46
/* DAC digital controls */
#define AC100_DAC_DIG_CTRL 0x48
#define AC100_DAC_VOL_CTRL 0x49
#define AC100_DAC_MXR_SRC 0x4c
#define AC100_DAC_MXR_GAIN 0x4d
/* Analog controls */
#define AC100_ADC_APC_CTRL 0x50
#define AC100_ADC_SRC 0x51
#define AC100_ADC_SRC_BST_CTRL 0x52
#define AC100_OUT_MXR_DAC_A_CTRL 0x53
#define AC100_OUT_MXR_SRC 0x54
#define AC100_OUT_MXR_SRC_BST 0x55
#define AC100_HPOUT_CTRL 0x56
#define AC100_ERPOUT_CTRL 0x57
#define AC100_SPKOUT_CTRL 0x58
#define AC100_LINEOUT_CTRL 0x59
/* ADC digital audio processing (high pass filter & auto gain control */
#define AC100_ADC_DAP_L_STA 0x80
#define AC100_ADC_DAP_R_STA 0x81
#define AC100_ADC_DAP_L_CTRL 0x82
#define AC100_ADC_DAP_R_CTRL 0x83
#define AC100_ADC_DAP_L_T_L 0x84 /* Left Target Level */
#define AC100_ADC_DAP_R_T_L 0x85 /* Right Target Level */
#define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */
#define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */
#define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */
#define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */
#define AC100_ADC_DAP_L_D_T 0x8a /* Left Decay Time */
#define AC100_ADC_DAP_L_A_T 0x8b /* Left Attack Time */
#define AC100_ADC_DAP_R_D_T 0x8c /* Right Decay Time */
#define AC100_ADC_DAP_R_A_T 0x8d /* Right Attack Time */
#define AC100_ADC_DAP_N_TH 0x8e /* Noise Threshold */
#define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */
#define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */
#define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */
#define AC100_ADC_DAP_R_L_N_A_C 0x92 /* Right Low Noise Avg. Coef */
#define AC100_ADC_DAP_H_HPF_C 0x93 /* High High-Pass-Filter Coef */
#define AC100_ADC_DAP_L_HPF_C 0x94 /* Low High-Pass-Filter Coef */
#define AC100_ADC_DAP_OPT 0x95 /* AGC Optimum */
/* DAC digital audio processing (high pass filter & dynamic range control) */
#define AC100_DAC_DAP_CTRL 0xa0
#define AC100_DAC_DAP_H_HPF_C 0xa1 /* High High-Pass-Filter Coef */
#define AC100_DAC_DAP_L_HPF_C 0xa2 /* Low High-Pass-Filter Coef */
#define AC100_DAC_DAP_L_H_E_A_C 0xa3 /* Left High Energy Avg Coef */
#define AC100_DAC_DAP_L_L_E_A_C 0xa4 /* Left Low Energy Avg Coef */
#define AC100_DAC_DAP_R_H_E_A_C 0xa5 /* Right High Energy Avg Coef */
#define AC100_DAC_DAP_R_L_E_A_C 0xa6 /* Right Low Energy Avg Coef */
#define AC100_DAC_DAP_H_G_D_T_C 0xa7 /* High Gain Delay Time Coef */
#define AC100_DAC_DAP_L_G_D_T_C 0xa8 /* Low Gain Delay Time Coef */
#define AC100_DAC_DAP_H_G_A_T_C 0xa9 /* High Gain Attack Time Coef */
#define AC100_DAC_DAP_L_G_A_T_C 0xaa /* Low Gain Attack Time Coef */
#define AC100_DAC_DAP_H_E_TH 0xab /* High Energy Threshold */
#define AC100_DAC_DAP_L_E_TH 0xac /* Low Energy Threshold */
#define AC100_DAC_DAP_H_G_K 0xad /* High Gain K parameter */
#define AC100_DAC_DAP_L_G_K 0xae /* Low Gain K parameter */
#define AC100_DAC_DAP_H_G_OFF 0xaf /* High Gain offset */
#define AC100_DAC_DAP_L_G_OFF 0xb0 /* Low Gain offset */
#define AC100_DAC_DAP_OPT 0xb1 /* DRC optimum */
/* Digital audio processing enable */
#define AC100_ADC_DAP_ENA 0xb4
#define AC100_DAC_DAP_ENA 0xb5
/* SRC control */
#define AC100_SRC1_CTRL1 0xb8
#define AC100_SRC1_CTRL2 0xb9
#define AC100_SRC1_CTRL3 0xba
#define AC100_SRC1_CTRL4 0xbb
#define AC100_SRC2_CTRL1 0xbc
#define AC100_SRC2_CTRL2 0xbd
#define AC100_SRC2_CTRL3 0xbe
#define AC100_SRC2_CTRL4 0xbf
/* RTC clk control */
#define AC100_CLK32K_ANALOG_CTRL 0xc0
#define AC100_CLKOUT_CTRL1 0xc1
#define AC100_CLKOUT_CTRL2 0xc2
#define AC100_CLKOUT_CTRL3 0xc3
/* RTC module */
#define AC100_RTC_RST 0xc6
#define AC100_RTC_CTRL 0xc7
#define AC100_RTC_SEC 0xc8 /* second */
#define AC100_RTC_MIN 0xc9 /* minute */
#define AC100_RTC_HOU 0xca /* hour */
#define AC100_RTC_WEE 0xcb /* weekday */
#define AC100_RTC_DAY 0xcc /* day */
#define AC100_RTC_MON 0xcd /* month */
#define AC100_RTC_YEA 0xce /* year */
#define AC100_RTC_UPD 0xcf /* update trigger */
/* RTC alarm */
#define AC100_ALM_INT_ENA 0xd0
#define AC100_ALM_INT_STA 0xd1
#define AC100_ALM_SEC 0xd8
#define AC100_ALM_MIN 0xd9
#define AC100_ALM_HOU 0xda
#define AC100_ALM_WEE 0xdb
#define AC100_ALM_DAY 0xdc
#define AC100_ALM_MON 0xdd
#define AC100_ALM_YEA 0xde
#define AC100_ALM_UPD 0xdf
/* RTC general purpose register 0 ~ 15 */
#define AC100_RTC_GP(x) (0xe0 + (x))
#endif /* __LINUX_MFD_AC100_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/adp5520.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Definitions and platform data for Analog Devices
* ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
*
* Copyright 2009 Analog Devices Inc.
*/
#ifndef __LINUX_MFD_ADP5520_H
#define __LINUX_MFD_ADP5520_H
#define ID_ADP5520 5520
#define ID_ADP5501 5501
/*
* ADP5520/ADP5501 Register Map
*/
#define ADP5520_MODE_STATUS 0x00
#define ADP5520_INTERRUPT_ENABLE 0x01
#define ADP5520_BL_CONTROL 0x02
#define ADP5520_BL_TIME 0x03
#define ADP5520_BL_FADE 0x04
#define ADP5520_DAYLIGHT_MAX 0x05
#define ADP5520_DAYLIGHT_DIM 0x06
#define ADP5520_OFFICE_MAX 0x07
#define ADP5520_OFFICE_DIM 0x08
#define ADP5520_DARK_MAX 0x09
#define ADP5520_DARK_DIM 0x0A
#define ADP5520_BL_VALUE 0x0B
#define ADP5520_ALS_CMPR_CFG 0x0C
#define ADP5520_L2_TRIP 0x0D
#define ADP5520_L2_HYS 0x0E
#define ADP5520_L3_TRIP 0x0F
#define ADP5520_L3_HYS 0x10
#define ADP5520_LED_CONTROL 0x11
#define ADP5520_LED_TIME 0x12
#define ADP5520_LED_FADE 0x13
#define ADP5520_LED1_CURRENT 0x14
#define ADP5520_LED2_CURRENT 0x15
#define ADP5520_LED3_CURRENT 0x16
/*
* ADP5520 Register Map
*/
#define ADP5520_GPIO_CFG_1 0x17
#define ADP5520_GPIO_CFG_2 0x18
#define ADP5520_GPIO_IN 0x19
#define ADP5520_GPIO_OUT 0x1A
#define ADP5520_GPIO_INT_EN 0x1B
#define ADP5520_GPIO_INT_STAT 0x1C
#define ADP5520_GPIO_INT_LVL 0x1D
#define ADP5520_GPIO_DEBOUNCE 0x1E
#define ADP5520_GPIO_PULLUP 0x1F
#define ADP5520_KP_INT_STAT_1 0x20
#define ADP5520_KP_INT_STAT_2 0x21
#define ADP5520_KR_INT_STAT_1 0x22
#define ADP5520_KR_INT_STAT_2 0x23
#define ADP5520_KEY_STAT_1 0x24
#define ADP5520_KEY_STAT_2 0x25
/*
* MODE_STATUS bits
*/
#define ADP5520_nSTNBY (1 << 7)
#define ADP5520_BL_EN (1 << 6)
#define ADP5520_DIM_EN (1 << 5)
#define ADP5520_OVP_INT (1 << 4)
#define ADP5520_CMPR_INT (1 << 3)
#define ADP5520_GPI_INT (1 << 2)
#define ADP5520_KR_INT (1 << 1)
#define ADP5520_KP_INT (1 << 0)
/*
* INTERRUPT_ENABLE bits
*/
#define ADP5520_AUTO_LD_EN (1 << 4)
#define ADP5520_CMPR_IEN (1 << 3)
#define ADP5520_OVP_IEN (1 << 2)
#define ADP5520_KR_IEN (1 << 1)
#define ADP5520_KP_IEN (1 << 0)
/*
* BL_CONTROL bits
*/
#define ADP5520_BL_LVL ((x) << 5)
#define ADP5520_BL_LAW ((x) << 4)
#define ADP5520_BL_AUTO_ADJ (1 << 3)
#define ADP5520_OVP_EN (1 << 2)
#define ADP5520_FOVR (1 << 1)
#define ADP5520_KP_BL_EN (1 << 0)
/*
* ALS_CMPR_CFG bits
*/
#define ADP5520_L3_OUT (1 << 3)
#define ADP5520_L2_OUT (1 << 2)
#define ADP5520_L3_EN (1 << 1)
#define ADP5020_MAX_BRIGHTNESS 0x7F
#define FADE_VAL(in, out) ((0xF & (in)) | ((0xF & (out)) << 4))
#define BL_CTRL_VAL(law, auto) (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
#define ALS_CMPR_CFG_VAL(filt, l3_en) (((0x7 & filt) << 5) | l3_en)
/*
* LEDs subdevice bits and masks
*/
#define ADP5520_01_MAXLEDS 3
#define ADP5520_FLAG_LED_MASK 0x3
#define ADP5520_FLAG_OFFT_SHIFT 8
#define ADP5520_FLAG_OFFT_MASK 0x3
#define ADP5520_R3_MODE (1 << 5)
#define ADP5520_C3_MODE (1 << 4)
#define ADP5520_LED_LAW (1 << 3)
#define ADP5520_LED3_EN (1 << 2)
#define ADP5520_LED2_EN (1 << 1)
#define ADP5520_LED1_EN (1 << 0)
/*
* GPIO subdevice bits and masks
*/
#define ADP5520_MAXGPIOS 8
#define ADP5520_GPIO_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_GPIO_C2 (1 << 6)
#define ADP5520_GPIO_C1 (1 << 5)
#define ADP5520_GPIO_C0 (1 << 4)
#define ADP5520_GPIO_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_GPIO_R2 (1 << 2)
#define ADP5520_GPIO_R1 (1 << 1)
#define ADP5520_GPIO_R0 (1 << 0)
struct adp5520_gpio_platform_data {
unsigned gpio_start;
u8 gpio_en_mask;
u8 gpio_pullup_mask;
};
/*
* Keypad subdevice bits and masks
*/
#define ADP5520_MAXKEYS 16
#define ADP5520_COL_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_COL_C2 (1 << 6)
#define ADP5520_COL_C1 (1 << 5)
#define ADP5520_COL_C0 (1 << 4)
#define ADP5520_ROW_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_ROW_R2 (1 << 2)
#define ADP5520_ROW_R1 (1 << 1)
#define ADP5520_ROW_R0 (1 << 0)
#define ADP5520_KEY(row, col) (col + row * 4)
#define ADP5520_KEYMAPSIZE ADP5520_MAXKEYS
struct adp5520_keys_platform_data {
int rows_en_mask; /* Number of rows */
int cols_en_mask; /* Number of columns */
const unsigned short *keymap; /* Pointer to keymap */
unsigned short keymapsize; /* Keymap size */
unsigned repeat:1; /* Enable key repeat */
};
/*
* LEDs subdevice platform data
*/
#define FLAG_ID_ADP5520_LED1_ADP5501_LED0 1 /* ADP5520 PIN ILED */
#define FLAG_ID_ADP5520_LED2_ADP5501_LED1 2 /* ADP5520 PIN C3 */
#define FLAG_ID_ADP5520_LED3_ADP5501_LED2 3 /* ADP5520 PIN R3 */
#define ADP5520_LED_DIS_BLINK (0 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_600ms (1 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_800ms (2 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_ONT_200ms 0
#define ADP5520_LED_ONT_600ms 1
#define ADP5520_LED_ONT_800ms 2
#define ADP5520_LED_ONT_1200ms 3
struct adp5520_leds_platform_data {
int num_leds;
struct led_info *leds;
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 led_on_time;
};
/*
* Backlight subdevice platform data
*/
#define ADP5520_FADE_T_DIS 0 /* Fade Timer Disabled */
#define ADP5520_FADE_T_300ms 1 /* 0.3 Sec */
#define ADP5520_FADE_T_600ms 2
#define ADP5520_FADE_T_900ms 3
#define ADP5520_FADE_T_1200ms 4
#define ADP5520_FADE_T_1500ms 5
#define ADP5520_FADE_T_1800ms 6
#define ADP5520_FADE_T_2100ms 7
#define ADP5520_FADE_T_2400ms 8
#define ADP5520_FADE_T_2700ms 9
#define ADP5520_FADE_T_3000ms 10
#define ADP5520_FADE_T_3500ms 11
#define ADP5520_FADE_T_4000ms 12
#define ADP5520_FADE_T_4500ms 13
#define ADP5520_FADE_T_5000ms 14
#define ADP5520_FADE_T_5500ms 15 /* 5.5 Sec */
#define ADP5520_BL_LAW_LINEAR 0
#define ADP5520_BL_LAW_SQUARE 1
#define ADP5520_BL_LAW_CUBIC1 2
#define ADP5520_BL_LAW_CUBIC2 3
#define ADP5520_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
#define ADP5520_BL_AMBL_FILT_160ms 1
#define ADP5520_BL_AMBL_FILT_320ms 2
#define ADP5520_BL_AMBL_FILT_640ms 3
#define ADP5520_BL_AMBL_FILT_1280ms 4
#define ADP5520_BL_AMBL_FILT_2560ms 5
#define ADP5520_BL_AMBL_FILT_5120ms 6
#define ADP5520_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
/*
* Blacklight current 0..30mA
*/
#define ADP5520_BL_CUR_mA(I) ((I * 127) / 30)
/*
* L2 comparator current 0..1000uA
*/
#define ADP5520_L2_COMP_CURR_uA(I) ((I * 255) / 1000)
/*
* L3 comparator current 0..127uA
*/
#define ADP5520_L3_COMP_CURR_uA(I) ((I * 255) / 127)
struct adp5520_backlight_platform_data {
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 fade_led_law; /* fade-on/fade-off transfer characteristic */
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
u8 abml_filt; /* Light sensor filter time */
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
};
/*
* MFD chip platform data
*/
struct adp5520_platform_data {
struct adp5520_keys_platform_data *keys;
struct adp5520_gpio_platform_data *gpio;
struct adp5520_leds_platform_data *leds;
struct adp5520_backlight_platform_data *backlight;
};
/*
* MFD chip functions
*/
extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
extern int adp5520_write(struct device *dev, int reg, u8 val);
extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int adp5520_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
#endif /* __LINUX_MFD_ADP5520_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/adp5585.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Analog Devices ADP5585 I/O expander, PWM controller and keypad controller
*
* Copyright 2022 NXP
* Copyright 2024 Ideas on Board Oy
*/
#ifndef __MFD_ADP5585_H_
#define __MFD_ADP5585_H_
#include <linux/bits.h>
#include <linux/notifier.h>
#define ADP5585_ID 0x00
#define ADP5585_MAN_ID_VALUE 0x20
#define ADP5585_MAN_ID_MASK GENMASK(7, 4)
#define ADP5585_REV_ID_MASK GENMASK(3, 0)
#define ADP5585_INT_STATUS 0x01
#define ADP5585_OVRFLOW_INT BIT(2)
#define ADP5585_EVENT_INT BIT(0)
#define ADP5585_STATUS 0x02
#define ADP5585_EC_MASK GENMASK(4, 0)
#define ADP5585_FIFO_1 0x03
#define ADP5585_KEV_EV_PRESS_MASK BIT(7)
#define ADP5585_KEY_EVENT_MASK GENMASK(6, 0)
#define ADP5585_FIFO_2 0x04
#define ADP5585_FIFO_3 0x05
#define ADP5585_FIFO_4 0x06
#define ADP5585_FIFO_5 0x07
#define ADP5585_FIFO_6 0x08
#define ADP5585_FIFO_7 0x09
#define ADP5585_FIFO_8 0x0a
#define ADP5585_FIFO_9 0x0b
#define ADP5585_FIFO_10 0x0c
#define ADP5585_FIFO_11 0x0d
#define ADP5585_FIFO_12 0x0e
#define ADP5585_FIFO_13 0x0f
#define ADP5585_FIFO_14 0x10
#define ADP5585_FIFO_15 0x11
#define ADP5585_FIFO_16 0x12
#define ADP5585_EV_MAX (ADP5585_FIFO_16 - ADP5585_FIFO_1 + 1)
#define ADP5585_GPI_INT_STAT_A 0x13
#define ADP5585_GPI_INT_STAT_B 0x14
#define ADP5585_GPI_STATUS_A 0x15
#define ADP5585_GPI_STATUS_B 0x16
#define ADP5585_RPULL_CONFIG_A 0x17
#define ADP5585_RPULL_CONFIG_B 0x18
#define ADP5585_RPULL_CONFIG_C 0x19
#define ADP5585_RPULL_CONFIG_D 0x1a
#define ADP5585_Rx_PULL_CFG_PU_300K 0
#define ADP5585_Rx_PULL_CFG_PD_300K 1
#define ADP5585_Rx_PULL_CFG_PU_100K 2
#define ADP5585_Rx_PULL_CFG_DISABLE 3
#define ADP5585_Rx_PULL_CFG_MASK 3
#define ADP5585_GPI_INT_LEVEL_A 0x1b
#define ADP5585_GPI_INT_LEVEL_B 0x1c
#define ADP5585_GPI_EVENT_EN_A 0x1d
#define ADP5585_GPI_EVENT_EN_B 0x1e
#define ADP5585_GPI_INTERRUPT_EN_A 0x1f
#define ADP5585_GPI_INTERRUPT_EN_B 0x20
#define ADP5585_DEBOUNCE_DIS_A 0x21
#define ADP5585_DEBOUNCE_DIS_B 0x22
#define ADP5585_GPO_DATA_OUT_A 0x23
#define ADP5585_GPO_DATA_OUT_B 0x24
#define ADP5585_GPO_OUT_MODE_A 0x25
#define ADP5585_GPO_OUT_MODE_B 0x26
#define ADP5585_GPIO_DIRECTION_A 0x27
#define ADP5585_GPIO_DIRECTION_B 0x28
#define ADP5585_RESET1_EVENT_A 0x29
#define ADP5585_RESET_EV_PRESS BIT(7)
#define ADP5585_RESET1_EVENT_B 0x2a
#define ADP5585_RESET1_EVENT_C 0x2b
#define ADP5585_RESET2_EVENT_A 0x2c
#define ADP5585_RESET2_EVENT_B 0x2d
#define ADP5585_RESET_CFG 0x2e
#define ADP5585_PWM_OFFT_LOW 0x2f
#define ADP5585_PWM_OFFT_HIGH 0x30
#define ADP5585_PWM_ONT_LOW 0x31
#define ADP5585_PWM_ONT_HIGH 0x32
#define ADP5585_PWM_CFG 0x33
#define ADP5585_PWM_IN_AND BIT(2)
#define ADP5585_PWM_MODE BIT(1)
#define ADP5585_PWM_EN BIT(0)
#define ADP5585_LOGIC_CFG 0x34
#define ADP5585_LOGIC_FF_CFG 0x35
#define ADP5585_LOGIC_INT_EVENT_EN 0x36
#define ADP5585_POLL_PTIME_CFG 0x37
#define ADP5585_PIN_CONFIG_A 0x38
#define ADP5585_PIN_CONFIG_B 0x39
#define ADP5585_PIN_CONFIG_C 0x3a
#define ADP5585_PULL_SELECT BIT(7)
#define ADP5585_C4_EXTEND_CFG_GPIO11 (0U << 6)
#define ADP5585_C4_EXTEND_CFG_RESET2 (1U << 6)
#define ADP5585_C4_EXTEND_CFG_MASK GENMASK(6, 6)
#define ADP5585_R4_EXTEND_CFG_GPIO5 (0U << 5)
#define ADP5585_R4_EXTEND_CFG_RESET1 (1U << 5)
#define ADP5585_R4_EXTEND_CFG_MASK GENMASK(5, 5)
#define ADP5585_R3_EXTEND_CFG_GPIO4 (0U << 2)
#define ADP5585_R3_EXTEND_CFG_LC (1U << 2)
#define ADP5585_R3_EXTEND_CFG_PWM_OUT (2U << 2)
#define ADP5585_R3_EXTEND_CFG_MASK GENMASK(3, 2)
#define ADP5585_R0_EXTEND_CFG_GPIO1 (0U << 0)
#define ADP5585_R0_EXTEND_CFG_LY (1U << 0)
#define ADP5585_R0_EXTEND_CFG_MASK GENMASK(0, 0)
#define ADP5585_GENERAL_CFG 0x3b
#define ADP5585_OSC_EN BIT(7)
#define ADP5585_OSC_FREQ_50KHZ (0U << 5)
#define ADP5585_OSC_FREQ_100KHZ (1U << 5)
#define ADP5585_OSC_FREQ_200KHZ (2U << 5)
#define ADP5585_OSC_FREQ_500KHZ (3U << 5)
#define ADP5585_OSC_FREQ_MASK GENMASK(6, 5)
#define ADP5585_INT_CFG BIT(1)
#define ADP5585_RST_CFG BIT(0)
#define ADP5585_INT_EN 0x3c
#define ADP5585_OVRFLOW_IEN BIT(2)
#define ADP5585_EVENT_IEN BIT(0)
#define ADP5585_MAX_REG ADP5585_INT_EN
#define ADP5585_PIN_MAX 11
#define ADP5585_MAX_UNLOCK_TIME_SEC 7
#define ADP5585_KEY_EVENT_START 1
#define ADP5585_KEY_EVENT_END 25
#define ADP5585_GPI_EVENT_START 37
#define ADP5585_GPI_EVENT_END 47
#define ADP5585_ROW5_KEY_EVENT_START 1
#define ADP5585_ROW5_KEY_EVENT_END 30
#define ADP5585_PWM_OUT 3
#define ADP5585_RESET1_OUT 4
#define ADP5585_RESET2_OUT 9
#define ADP5585_ROW5 5
/* ADP5589 */
#define ADP5589_MAN_ID_VALUE 0x10
#define ADP5589_GPI_STATUS_A 0x16
#define ADP5589_GPI_STATUS_C 0x18
#define ADP5589_RPULL_CONFIG_A 0x19
#define ADP5589_GPI_INT_LEVEL_A 0x1e
#define ADP5589_GPI_EVENT_EN_A 0x21
#define ADP5589_DEBOUNCE_DIS_A 0x27
#define ADP5589_GPO_DATA_OUT_A 0x2a
#define ADP5589_GPO_OUT_MODE_A 0x2d
#define ADP5589_GPIO_DIRECTION_A 0x30
#define ADP5589_UNLOCK1 0x33
#define ADP5589_UNLOCK_EV_PRESS BIT(7)
#define ADP5589_UNLOCK_TIMERS 0x36
#define ADP5589_UNLOCK_TIMER GENMASK(2, 0)
#define ADP5589_LOCK_CFG 0x37
#define ADP5589_LOCK_EN BIT(0)
#define ADP5589_RESET1_EVENT_A 0x38
#define ADP5589_RESET2_EVENT_A 0x3B
#define ADP5589_RESET_CFG 0x3D
#define ADP5585_RESET2_POL BIT(7)
#define ADP5585_RESET1_POL BIT(6)
#define ADP5585_RST_PASSTHRU_EN BIT(5)
#define ADP5585_RESET_TRIG_TIME GENMASK(4, 2)
#define ADP5585_PULSE_WIDTH GENMASK(1, 0)
#define ADP5589_PWM_OFFT_LOW 0x3e
#define ADP5589_PWM_ONT_LOW 0x40
#define ADP5589_PWM_CFG 0x42
#define ADP5589_POLL_PTIME_CFG 0x48
#define ADP5589_PIN_CONFIG_A 0x49
#define ADP5589_PIN_CONFIG_D 0x4C
#define ADP5589_GENERAL_CFG 0x4d
#define ADP5589_INT_EN 0x4e
#define ADP5589_MAX_REG ADP5589_INT_EN
#define ADP5589_PIN_MAX 19
#define ADP5589_KEY_EVENT_START 1
#define ADP5589_KEY_EVENT_END 88
#define ADP5589_GPI_EVENT_START 97
#define ADP5589_GPI_EVENT_END 115
#define ADP5589_UNLOCK_WILDCARD 127
#define ADP5589_RESET2_OUT 12
struct regmap;
enum adp5585_variant {
ADP5585_00 = 1,
ADP5585_01,
ADP5585_02,
ADP5585_03,
ADP5585_04,
ADP5589_00,
ADP5589_01,
ADP5589_02,
ADP5585_MAX
};
struct adp5585_regs {
unsigned int gen_cfg;
unsigned int ext_cfg;
unsigned int int_en;
unsigned int poll_ptime_cfg;
unsigned int reset_cfg;
unsigned int reset1_event_a;
unsigned int reset2_event_a;
unsigned int pin_cfg_a;
};
struct adp5585_dev {
struct device *dev;
struct regmap *regmap;
const struct adp5585_regs *regs;
struct blocking_notifier_head event_notifier;
unsigned long *pin_usage;
unsigned int n_pins;
unsigned int reset2_out;
enum adp5585_variant variant;
unsigned int id;
bool has_unlock;
bool has_pin6;
int irq;
unsigned int ev_poll_time;
unsigned int unlock_time;
unsigned int unlock_keys[2];
unsigned int nkeys_unlock;
unsigned int reset1_keys[3];
unsigned int nkeys_reset1;
unsigned int reset2_keys[2];
unsigned int nkeys_reset2;
u8 reset_cfg;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/altera-a10sr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
*
* Declarations for Altera Arria10 MAX5 System Resource Chip
*
* Adapted from DA9052
*/
#ifndef __MFD_ALTERA_A10SR_H
#define __MFD_ALTERA_A10SR_H
#include <linux/completion.h>
#include <linux/list.h>
#include <linux/mfd/core.h>
#include <linux/regmap.h>
#include <linux/slab.h>
/* Write registers are always on even addresses */
#define WRITE_REG_MASK 0xFE
/* Odd registers are always on odd addresses */
#define READ_REG_MASK 0x01
#define ALTR_A10SR_BITS_PER_REGISTER 8
/*
* To find the correct register, we divide the input GPIO by
* the number of GPIO in each register. We then need to multiply
* by 2 because the reads are at odd addresses.
*/
#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER)
#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X))
/* Arria10 System Controller Register Defines */
#define ALTR_A10SR_NOP 0x00 /* No Change */
#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */
#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
/* LED register Bit Definitions */
#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT
#define ALTR_A10SR_OUT_VALID_RANGE_HI 7
#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
/* Pushbutton & DIP Switch Bit Definitions */
#define ALTR_A10SR_IN_VALID_RANGE_LO 8
#define ALTR_A10SR_IN_VALID_RANGE_HI 15
#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */
#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */
#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */
#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */
#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */
#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */
#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */
#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */
#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */
/**
* struct altr_a10sr - Altera Max5 MFD device private data structure
* @dev: : this device
* @regmap: the regmap assigned to the parent device.
*/
struct altr_a10sr {
struct device *dev;
struct regmap *regmap;
};
#endif /* __MFD_ALTERA_A10SR_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/altera-sysmgr.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2019 Intel Corporation
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*/
#ifndef __LINUX_MFD_ALTERA_SYSMGR_H__
#define __LINUX_MFD_ALTERA_SYSMGR_H__
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/firmware/intel/stratix10-smc.h>
struct device_node;
#ifdef CONFIG_MFD_ALTERA_SYSMGR
struct regmap *altr_sysmgr_regmap_lookup_by_phandle(struct device_node *np,
const char *property);
#else
static inline struct regmap *
altr_sysmgr_regmap_lookup_by_phandle(struct device_node *np,
const char *property)
{
return ERR_PTR(-ENOTSUPP);
}
#endif
#endif /* __LINUX_MFD_ALTERA_SYSMGR_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/arizona/core.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Arizona MFD internals
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*/
#ifndef _WM_ARIZONA_CORE_H
#define _WM_ARIZONA_CORE_H
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/arizona/pdata.h>
#define ARIZONA_MAX_CORE_SUPPLIES 2
enum {
ARIZONA_MCLK1,
ARIZONA_MCLK2,
ARIZONA_NUM_MCLK
};
enum arizona_type {
WM5102 = 1,
WM5110 = 2,
WM8997 = 3,
WM8280 = 4,
WM8998 = 5,
WM1814 = 6,
WM1831 = 7,
CS47L24 = 8,
};
#define ARIZONA_IRQ_GP1 0
#define ARIZONA_IRQ_GP2 1
#define ARIZONA_IRQ_GP3 2
#define ARIZONA_IRQ_GP4 3
#define ARIZONA_IRQ_GP5_FALL 4
#define ARIZONA_IRQ_GP5_RISE 5
#define ARIZONA_IRQ_JD_FALL 6
#define ARIZONA_IRQ_JD_RISE 7
#define ARIZONA_IRQ_DSP1_RAM_RDY 8
#define ARIZONA_IRQ_DSP2_RAM_RDY 9
#define ARIZONA_IRQ_DSP3_RAM_RDY 10
#define ARIZONA_IRQ_DSP4_RAM_RDY 11
#define ARIZONA_IRQ_DSP_IRQ1 12
#define ARIZONA_IRQ_DSP_IRQ2 13
#define ARIZONA_IRQ_DSP_IRQ3 14
#define ARIZONA_IRQ_DSP_IRQ4 15
#define ARIZONA_IRQ_DSP_IRQ5 16
#define ARIZONA_IRQ_DSP_IRQ6 17
#define ARIZONA_IRQ_DSP_IRQ7 18
#define ARIZONA_IRQ_DSP_IRQ8 19
#define ARIZONA_IRQ_SPK_OVERHEAT_WARN 20
#define ARIZONA_IRQ_SPK_OVERHEAT 21
#define ARIZONA_IRQ_MICDET 22
#define ARIZONA_IRQ_HPDET 23
#define ARIZONA_IRQ_WSEQ_DONE 24
#define ARIZONA_IRQ_DRC2_SIG_DET 25
#define ARIZONA_IRQ_DRC1_SIG_DET 26
#define ARIZONA_IRQ_ASRC2_LOCK 27
#define ARIZONA_IRQ_ASRC1_LOCK 28
#define ARIZONA_IRQ_UNDERCLOCKED 29
#define ARIZONA_IRQ_OVERCLOCKED 30
#define ARIZONA_IRQ_FLL2_LOCK 31
#define ARIZONA_IRQ_FLL1_LOCK 32
#define ARIZONA_IRQ_CLKGEN_ERR 33
#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 34
#define ARIZONA_IRQ_ASRC_CFG_ERR 35
#define ARIZONA_IRQ_AIF3_ERR 36
#define ARIZONA_IRQ_AIF2_ERR 37
#define ARIZONA_IRQ_AIF1_ERR 38
#define ARIZONA_IRQ_CTRLIF_ERR 39
#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 40
#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 41
#define ARIZONA_IRQ_SYSCLK_ENA_LOW 42
#define ARIZONA_IRQ_ISRC1_CFG_ERR 43
#define ARIZONA_IRQ_ISRC2_CFG_ERR 44
#define ARIZONA_IRQ_BOOT_DONE 45
#define ARIZONA_IRQ_DCS_DAC_DONE 46
#define ARIZONA_IRQ_DCS_HP_DONE 47
#define ARIZONA_IRQ_FLL2_CLOCK_OK 48
#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
#define ARIZONA_IRQ_HP3R_DONE 52
#define ARIZONA_IRQ_HP3L_DONE 53
#define ARIZONA_IRQ_HP2R_DONE 54
#define ARIZONA_IRQ_HP2L_DONE 55
#define ARIZONA_IRQ_HP1R_DONE 56
#define ARIZONA_IRQ_HP1L_DONE 57
#define ARIZONA_IRQ_ISRC3_CFG_ERR 58
#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 59
#define ARIZONA_IRQ_SPK_SHUTDOWN 60
#define ARIZONA_IRQ_SPK1R_SHORT 61
#define ARIZONA_IRQ_SPK1L_SHORT 62
#define ARIZONA_IRQ_HP3R_SC_NEG 63
#define ARIZONA_IRQ_HP3R_SC_POS 64
#define ARIZONA_IRQ_HP3L_SC_NEG 65
#define ARIZONA_IRQ_HP3L_SC_POS 66
#define ARIZONA_IRQ_HP2R_SC_NEG 67
#define ARIZONA_IRQ_HP2R_SC_POS 68
#define ARIZONA_IRQ_HP2L_SC_NEG 69
#define ARIZONA_IRQ_HP2L_SC_POS 70
#define ARIZONA_IRQ_HP1R_SC_NEG 71
#define ARIZONA_IRQ_HP1R_SC_POS 72
#define ARIZONA_IRQ_HP1L_SC_NEG 73
#define ARIZONA_IRQ_HP1L_SC_POS 74
#define ARIZONA_NUM_IRQ 75
struct snd_soc_dapm_context;
struct arizona {
struct regmap *regmap;
struct device *dev;
enum arizona_type type;
unsigned int rev;
int num_core_supplies;
struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
struct regulator *dcvdd;
bool has_fully_powered_off;
struct arizona_pdata pdata;
unsigned int external_dcvdd:1;
int irq;
struct irq_domain *virq;
struct regmap_irq_chip_data *aod_irq_chip;
struct regmap_irq_chip_data *irq_chip;
bool hpdet_clamp;
unsigned int hp_ena;
struct mutex clk_lock;
int clk32k_ref;
struct clk *mclk[ARIZONA_NUM_MCLK];
bool ctrlif_error;
struct snd_soc_dapm_context *dapm;
int tdm_width[ARIZONA_MAX_AIF];
int tdm_slots[ARIZONA_MAX_AIF];
uint16_t dac_comp_coeff;
uint8_t dac_comp_enabled;
struct mutex dac_comp_lock;
struct blocking_notifier_head notifier;
};
static inline int arizona_call_notifiers(struct arizona *arizona,
unsigned long event,
void *data)
{
return blocking_notifier_call_chain(&arizona->notifier, event, data);
}
int arizona_clk32k_enable(struct arizona *arizona);
int arizona_clk32k_disable(struct arizona *arizona);
int arizona_request_irq(struct arizona *arizona, int irq, char *name,
irq_handler_t handler, void *data);
void arizona_free_irq(struct arizona *arizona, int irq, void *data);
int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
#ifdef CONFIG_MFD_WM5102
int wm5102_patch(struct arizona *arizona);
#else
static inline int wm5102_patch(struct arizona *arizona)
{
return 0;
}
#endif
int wm5110_patch(struct arizona *arizona);
int cs47l24_patch(struct arizona *arizona);
int wm8997_patch(struct arizona *arizona);
int wm8998_patch(struct arizona *arizona);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/arizona/pdata.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Platform data for Arizona devices
*
* Copyright 2012 Wolfson Microelectronics. PLC.
*/
#ifndef _ARIZONA_PDATA_H
#define _ARIZONA_PDATA_H
#include <dt-bindings/mfd/arizona.h>
#include <linux/regulator/arizona-ldo1.h>
#include <linux/regulator/arizona-micsupp.h>
#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
#define ARIZONA_MAX_GPIO 5
#define ARIZONA_MAX_INPUT 4
#define ARIZONA_MAX_MICBIAS 3
#define ARIZONA_MAX_OUTPUT 6
#define ARIZONA_MAX_AIF 3
#define ARIZONA_HAP_ACT_ERM 0
#define ARIZONA_HAP_ACT_LRA 2
#define ARIZONA_MAX_PDM_SPK 2
struct regulator_init_data;
struct gpio_desc;
struct arizona_micbias {
int mV; /** Regulated voltage */
unsigned int ext_cap:1; /** External capacitor fitted */
unsigned int discharge:1; /** Actively discharge */
unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
unsigned int bypass:1; /** Use bypass mode */
};
struct arizona_micd_config {
unsigned int src;
unsigned int bias;
bool gpio;
};
struct arizona_micd_range {
int max; /** Ohms */
int key; /** Key to report to input layer */
};
struct arizona_pdata {
struct gpio_desc *reset; /** GPIO controlling /RESET, if any */
/** Regulator configuration for MICVDD */
struct arizona_micsupp_pdata micvdd;
/** Regulator configuration for LDO1 */
struct arizona_ldo1_pdata ldo1;
/** If a direct 32kHz clock is provided on an MCLK specify it here */
int clk32k_src;
/** Mode for primary IRQ (defaults to active low) */
unsigned int irq_flags;
/* Base GPIO */
int gpio_base;
/** Pin state for GPIO pins */
unsigned int gpio_defaults[ARIZONA_MAX_GPIO];
/**
* Maximum number of channels clocks will be generated for,
* useful for systems where and I2S bus with multiple data
* lines is mastered.
*/
unsigned int max_channels_clocked[ARIZONA_MAX_AIF];
/** GPIO5 is used for jack detection */
bool jd_gpio5;
/** Internal pull on GPIO5 is disabled when used for jack detection */
bool jd_gpio5_nopull;
/** set to true if jackdet contact opens on insert */
bool jd_invert;
/** Use the headphone detect circuit to identify the accessory */
bool hpdet_acc_id;
/** Check for line output with HPDET method */
bool hpdet_acc_id_line;
/** Channel to use for headphone detection */
unsigned int hpdet_channel;
/** Use software comparison to determine mic presence */
bool micd_software_compare;
/** Extra debounce timeout used during initial mic detection (ms) */
unsigned int micd_detect_debounce;
/** Mic detect ramp rate */
unsigned int micd_bias_start_time;
/** Mic detect sample rate */
unsigned int micd_rate;
/** Mic detect debounce level */
unsigned int micd_dbtime;
/** Mic detect timeout (ms) */
unsigned int micd_timeout;
/** Force MICBIAS on for mic detect */
bool micd_force_micbias;
/** Mic detect level parameters */
const struct arizona_micd_range *micd_ranges;
int num_micd_ranges;
/** Headset polarity configurations */
struct arizona_micd_config *micd_configs;
int num_micd_configs;
/** Reference voltage for DMIC inputs */
int dmic_ref[ARIZONA_MAX_INPUT];
/** MICBIAS configurations */
struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
/**
* Mode of input structures
* One of the ARIZONA_INMODE_xxx values
* wm5102/wm5110/wm8280/wm8997: [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4
* wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B
*/
int inmode[ARIZONA_MAX_INPUT];
/** Mode for outputs */
int out_mono[ARIZONA_MAX_OUTPUT];
/** Limit output volumes */
unsigned int out_vol_limit[2 * ARIZONA_MAX_OUTPUT];
/** PDM speaker mute setting */
unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
/** PDM speaker format */
unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
/** Haptic actuator type */
unsigned int hap_act;
#ifdef CONFIG_GPIOLIB_LEGACY
/** GPIO for primary IRQ (used for edge triggered emulation) */
int irq_gpio;
#endif
/** General purpose switch control */
unsigned int gpsw;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/arizona/registers.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/as3711.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AS3711 PMIC MFC driver header
*
* Copyright (C) 2012 Renesas Electronics Corporation
* Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de>
*/
#ifndef MFD_AS3711_H
#define MFD_AS3711_H
/*
* Client data
*/
/* Register addresses */
#define AS3711_SD_1_VOLTAGE 0 /* Digital Step-Down */
#define AS3711_SD_2_VOLTAGE 1
#define AS3711_SD_3_VOLTAGE 2
#define AS3711_SD_4_VOLTAGE 3
#define AS3711_LDO_1_VOLTAGE 4 /* Analog LDO */
#define AS3711_LDO_2_VOLTAGE 5
#define AS3711_LDO_3_VOLTAGE 6 /* Digital LDO */
#define AS3711_LDO_4_VOLTAGE 7
#define AS3711_LDO_5_VOLTAGE 8
#define AS3711_LDO_6_VOLTAGE 9
#define AS3711_LDO_7_VOLTAGE 0xa
#define AS3711_LDO_8_VOLTAGE 0xb
#define AS3711_SD_CONTROL 0x10
#define AS3711_GPIO_SIGNAL_OUT 0x20
#define AS3711_GPIO_SIGNAL_IN 0x21
#define AS3711_SD_CONTROL_1 0x30
#define AS3711_SD_CONTROL_2 0x31
#define AS3711_CURR_CONTROL 0x40
#define AS3711_CURR1_VALUE 0x43
#define AS3711_CURR2_VALUE 0x44
#define AS3711_CURR3_VALUE 0x45
#define AS3711_STEPUP_CONTROL_1 0x50
#define AS3711_STEPUP_CONTROL_2 0x51
#define AS3711_STEPUP_CONTROL_4 0x53
#define AS3711_STEPUP_CONTROL_5 0x54
#define AS3711_REG_STATUS 0x73
#define AS3711_INTERRUPT_STATUS_1 0x77
#define AS3711_INTERRUPT_STATUS_2 0x78
#define AS3711_INTERRUPT_STATUS_3 0x79
#define AS3711_CHARGER_STATUS_1 0x86
#define AS3711_CHARGER_STATUS_2 0x87
#define AS3711_ASIC_ID_1 0x90
#define AS3711_ASIC_ID_2 0x91
#define AS3711_MAX_REG AS3711_ASIC_ID_2
#define AS3711_NUM_REGS (AS3711_MAX_REG + 1)
/* Regulators */
enum {
AS3711_REGULATOR_SD_1,
AS3711_REGULATOR_SD_2,
AS3711_REGULATOR_SD_3,
AS3711_REGULATOR_SD_4,
AS3711_REGULATOR_LDO_1,
AS3711_REGULATOR_LDO_2,
AS3711_REGULATOR_LDO_3,
AS3711_REGULATOR_LDO_4,
AS3711_REGULATOR_LDO_5,
AS3711_REGULATOR_LDO_6,
AS3711_REGULATOR_LDO_7,
AS3711_REGULATOR_LDO_8,
AS3711_REGULATOR_MAX,
};
struct device;
struct regmap;
struct as3711 {
struct device *dev;
struct regmap *regmap;
};
#define AS3711_MAX_STEPDOWN 4
#define AS3711_MAX_STEPUP 2
#define AS3711_MAX_LDO 8
enum as3711_su2_feedback {
AS3711_SU2_VOLTAGE,
AS3711_SU2_CURR1,
AS3711_SU2_CURR2,
AS3711_SU2_CURR3,
AS3711_SU2_CURR_AUTO,
};
enum as3711_su2_fbprot {
AS3711_SU2_LX_SD4,
AS3711_SU2_GPIO2,
AS3711_SU2_GPIO3,
AS3711_SU2_GPIO4,
};
/*
* Platform data
*/
struct as3711_regulator_pdata {
struct regulator_init_data *init_data[AS3711_REGULATOR_MAX];
};
struct as3711_bl_pdata {
bool su1_fb;
int su1_max_uA;
bool su2_fb;
int su2_max_uA;
enum as3711_su2_feedback su2_feedback;
enum as3711_su2_fbprot su2_fbprot;
bool su2_auto_curr1;
bool su2_auto_curr2;
bool su2_auto_curr3;
};
struct as3711_platform_data {
struct as3711_regulator_pdata regulator;
struct as3711_bl_pdata backlight;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/as3722.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* as3722 definitions
*
* Copyright (C) 2013 ams
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
*
* Author: Florian Lobmaier <florian.lobmaier@ams.com>
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*/
#ifndef __LINUX_MFD_AS3722_H__
#define __LINUX_MFD_AS3722_H__
#include <linux/regmap.h>
/* AS3722 registers */
#define AS3722_SD0_VOLTAGE_REG 0x00
#define AS3722_SD1_VOLTAGE_REG 0x01
#define AS3722_SD2_VOLTAGE_REG 0x02
#define AS3722_SD3_VOLTAGE_REG 0x03
#define AS3722_SD4_VOLTAGE_REG 0x04
#define AS3722_SD5_VOLTAGE_REG 0x05
#define AS3722_SD6_VOLTAGE_REG 0x06
#define AS3722_GPIO0_CONTROL_REG 0x08
#define AS3722_GPIO1_CONTROL_REG 0x09
#define AS3722_GPIO2_CONTROL_REG 0x0A
#define AS3722_GPIO3_CONTROL_REG 0x0B
#define AS3722_GPIO4_CONTROL_REG 0x0C
#define AS3722_GPIO5_CONTROL_REG 0x0D
#define AS3722_GPIO6_CONTROL_REG 0x0E
#define AS3722_GPIO7_CONTROL_REG 0x0F
#define AS3722_LDO0_VOLTAGE_REG 0x10
#define AS3722_LDO1_VOLTAGE_REG 0x11
#define AS3722_LDO2_VOLTAGE_REG 0x12
#define AS3722_LDO3_VOLTAGE_REG 0x13
#define AS3722_LDO4_VOLTAGE_REG 0x14
#define AS3722_LDO5_VOLTAGE_REG 0x15
#define AS3722_LDO6_VOLTAGE_REG 0x16
#define AS3722_LDO7_VOLTAGE_REG 0x17
#define AS3722_LDO9_VOLTAGE_REG 0x19
#define AS3722_LDO10_VOLTAGE_REG 0x1A
#define AS3722_LDO11_VOLTAGE_REG 0x1B
#define AS3722_GPIO_DEB1_REG 0x1E
#define AS3722_GPIO_DEB2_REG 0x1F
#define AS3722_GPIO_SIGNAL_OUT_REG 0x20
#define AS3722_GPIO_SIGNAL_IN_REG 0x21
#define AS3722_REG_SEQU_MOD1_REG 0x22
#define AS3722_REG_SEQU_MOD2_REG 0x23
#define AS3722_REG_SEQU_MOD3_REG 0x24
#define AS3722_SD_PHSW_CTRL_REG 0x27
#define AS3722_SD_PHSW_STATUS 0x28
#define AS3722_SD0_CONTROL_REG 0x29
#define AS3722_SD1_CONTROL_REG 0x2A
#define AS3722_SDmph_CONTROL_REG 0x2B
#define AS3722_SD23_CONTROL_REG 0x2C
#define AS3722_SD4_CONTROL_REG 0x2D
#define AS3722_SD5_CONTROL_REG 0x2E
#define AS3722_SD6_CONTROL_REG 0x2F
#define AS3722_SD_DVM_REG 0x30
#define AS3722_RESET_REASON_REG 0x31
#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
#define AS3722_STARTUP_CONTROL_REG 0x33
#define AS3722_RESET_TIMER_REG 0x34
#define AS3722_REFERENCE_CONTROL_REG 0x35
#define AS3722_RESET_CONTROL_REG 0x36
#define AS3722_OVER_TEMP_CONTROL_REG 0x37
#define AS3722_WATCHDOG_CONTROL_REG 0x38
#define AS3722_REG_STANDBY_MOD1_REG 0x39
#define AS3722_REG_STANDBY_MOD2_REG 0x3A
#define AS3722_REG_STANDBY_MOD3_REG 0x3B
#define AS3722_ENABLE_CTRL1_REG 0x3C
#define AS3722_ENABLE_CTRL2_REG 0x3D
#define AS3722_ENABLE_CTRL3_REG 0x3E
#define AS3722_ENABLE_CTRL4_REG 0x3F
#define AS3722_ENABLE_CTRL5_REG 0x40
#define AS3722_PWM_CONTROL_L_REG 0x41
#define AS3722_PWM_CONTROL_H_REG 0x42
#define AS3722_WATCHDOG_TIMER_REG 0x46
#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
#define AS3722_IOVOLTAGE_REG 0x49
#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
#define AS3722_SD_CONTROL_REG 0x4D
#define AS3722_LDOCONTROL0_REG 0x4E
#define AS3722_LDOCONTROL1_REG 0x4F
#define AS3722_SD0_PROTECT_REG 0x50
#define AS3722_SD6_PROTECT_REG 0x51
#define AS3722_PWM_VCONTROL1_REG 0x52
#define AS3722_PWM_VCONTROL2_REG 0x53
#define AS3722_PWM_VCONTROL3_REG 0x54
#define AS3722_PWM_VCONTROL4_REG 0x55
#define AS3722_BB_CHARGER_REG 0x57
#define AS3722_CTRL_SEQU1_REG 0x58
#define AS3722_CTRL_SEQU2_REG 0x59
#define AS3722_OVCURRENT_REG 0x5A
#define AS3722_OVCURRENT_DEB_REG 0x5B
#define AS3722_SDLV_DEB_REG 0x5C
#define AS3722_OC_PG_CTRL_REG 0x5D
#define AS3722_OC_PG_CTRL2_REG 0x5E
#define AS3722_CTRL_STATUS 0x5F
#define AS3722_RTC_CONTROL_REG 0x60
#define AS3722_RTC_SECOND_REG 0x61
#define AS3722_RTC_MINUTE_REG 0x62
#define AS3722_RTC_HOUR_REG 0x63
#define AS3722_RTC_DAY_REG 0x64
#define AS3722_RTC_MONTH_REG 0x65
#define AS3722_RTC_YEAR_REG 0x66
#define AS3722_RTC_ALARM_SECOND_REG 0x67
#define AS3722_RTC_ALARM_MINUTE_REG 0x68
#define AS3722_RTC_ALARM_HOUR_REG 0x69
#define AS3722_RTC_ALARM_DAY_REG 0x6A
#define AS3722_RTC_ALARM_MONTH_REG 0x6B
#define AS3722_RTC_ALARM_YEAR_REG 0x6C
#define AS3722_SRAM_REG 0x6D
#define AS3722_RTC_ACCESS_REG 0x6F
#define AS3722_RTC_STATUS_REG 0x73
#define AS3722_INTERRUPT_MASK1_REG 0x74
#define AS3722_INTERRUPT_MASK2_REG 0x75
#define AS3722_INTERRUPT_MASK3_REG 0x76
#define AS3722_INTERRUPT_MASK4_REG 0x77
#define AS3722_INTERRUPT_STATUS1_REG 0x78
#define AS3722_INTERRUPT_STATUS2_REG 0x79
#define AS3722_INTERRUPT_STATUS3_REG 0x7A
#define AS3722_INTERRUPT_STATUS4_REG 0x7B
#define AS3722_TEMP_STATUS_REG 0x7D
#define AS3722_ADC0_CONTROL_REG 0x80
#define AS3722_ADC1_CONTROL_REG 0x81
#define AS3722_ADC0_MSB_RESULT_REG 0x82
#define AS3722_ADC0_LSB_RESULT_REG 0x83
#define AS3722_ADC1_MSB_RESULT_REG 0x84
#define AS3722_ADC1_LSB_RESULT_REG 0x85
#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
#define AS3722_ADC_CONFIGURATION_REG 0x8A
#define AS3722_ASIC_ID1_REG 0x90
#define AS3722_ASIC_ID2_REG 0x91
#define AS3722_LOCK_REG 0x9E
#define AS3722_FUSE7_REG 0xA7
#define AS3722_MAX_REGISTER 0xF4
#define AS3722_SD0_EXT_ENABLE_MASK 0x03
#define AS3722_SD1_EXT_ENABLE_MASK 0x0C
#define AS3722_SD2_EXT_ENABLE_MASK 0x30
#define AS3722_SD3_EXT_ENABLE_MASK 0xC0
#define AS3722_SD4_EXT_ENABLE_MASK 0x03
#define AS3722_SD5_EXT_ENABLE_MASK 0x0C
#define AS3722_SD6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO0_EXT_ENABLE_MASK 0x03
#define AS3722_LDO1_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO2_EXT_ENABLE_MASK 0x30
#define AS3722_LDO3_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO4_EXT_ENABLE_MASK 0x03
#define AS3722_LDO5_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO7_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO9_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO10_EXT_ENABLE_MASK 0x30
#define AS3722_LDO11_EXT_ENABLE_MASK 0xC0
#define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03
#define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60
#define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05
#define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03
/* AS3722 register bits and bit masks */
#define AS3722_LDO_ILIMIT_MASK BIT(7)
#define AS3722_LDO_ILIMIT_BIT BIT(7)
#define AS3722_LDO0_VSEL_MASK 0x1F
#define AS3722_LDO0_VSEL_MIN 0x01
#define AS3722_LDO0_VSEL_MAX 0x12
#define AS3722_LDO0_NUM_VOLT 0x12
#define AS3722_LDO3_VSEL_MASK 0x3F
#define AS3722_LDO3_VSEL_MIN 0x01
#define AS3722_LDO3_VSEL_MAX 0x2D
#define AS3722_LDO3_NUM_VOLT 0x2D
#define AS3722_LDO6_VSEL_BYPASS 0x3F
#define AS3722_LDO_VSEL_MASK 0x7F
#define AS3722_LDO_VSEL_MIN 0x01
#define AS3722_LDO_VSEL_MAX 0x7F
#define AS3722_LDO_VSEL_DNU_MIN 0x25
#define AS3722_LDO_VSEL_DNU_MAX 0x3F
#define AS3722_LDO_NUM_VOLT 0x80
#define AS3722_LDO0_CTRL BIT(0)
#define AS3722_LDO1_CTRL BIT(1)
#define AS3722_LDO2_CTRL BIT(2)
#define AS3722_LDO3_CTRL BIT(3)
#define AS3722_LDO4_CTRL BIT(4)
#define AS3722_LDO5_CTRL BIT(5)
#define AS3722_LDO6_CTRL BIT(6)
#define AS3722_LDO7_CTRL BIT(7)
#define AS3722_LDO9_CTRL BIT(1)
#define AS3722_LDO10_CTRL BIT(2)
#define AS3722_LDO11_CTRL BIT(3)
#define AS3722_LDO3_MODE_MASK (3 << 6)
#define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6)
#define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0)
#define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1)
#define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2)
#define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3)
#define AS3722_SD_VSEL_MASK 0x7F
#define AS3722_SD0_VSEL_MIN 0x01
#define AS3722_SD0_VSEL_MAX 0x5A
#define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E
#define AS3722_SD2_VSEL_MIN 0x01
#define AS3722_SD2_VSEL_MAX 0x7F
#define AS3722_SDn_CTRL(n) BIT(n)
#define AS3722_SD0_MODE_FAST BIT(4)
#define AS3722_SD1_MODE_FAST BIT(4)
#define AS3722_SD2_MODE_FAST BIT(2)
#define AS3722_SD3_MODE_FAST BIT(6)
#define AS3722_SD4_MODE_FAST BIT(2)
#define AS3722_SD5_MODE_FAST BIT(2)
#define AS3722_SD6_MODE_FAST BIT(4)
#define AS3722_POWER_OFF BIT(1)
#define AS3722_INTERRUPT_MASK1_LID BIT(0)
#define AS3722_INTERRUPT_MASK1_ACOK BIT(1)
#define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2)
#define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3)
#define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4)
#define AS3722_INTERRUPT_MASK1_ONKEY BIT(5)
#define AS3722_INTERRUPT_MASK1_OVTMP BIT(6)
#define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
#define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0)
#define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1)
#define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2)
#define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3)
#define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4)
#define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5)
#define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6)
#define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
#define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0)
#define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1)
#define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2)
#define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3)
#define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4)
#define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5)
#define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6)
#define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5)
#define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6)
#define AS3722_INTERRUPT_MASK4_ADC BIT(7)
#define AS3722_ADC1_INTERVAL_TIME BIT(0)
#define AS3722_ADC1_INT_MODE_ON BIT(1)
#define AS3722_ADC_BUF_ON BIT(2)
#define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5)
#define AS3722_ADC1_INTEVAL_SCAN BIT(6)
#define AS3722_ADC1_INT_MASK BIT(7)
#define AS3722_ADC_MSB_VAL_MASK 0x7F
#define AS3722_ADC_LSB_VAL_MASK 0x07
#define AS3722_ADC0_CONV_START BIT(7)
#define AS3722_ADC0_CONV_NOTREADY BIT(7)
#define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F
#define AS3722_ADC1_CONV_START BIT(7)
#define AS3722_ADC1_CONV_NOTREADY BIT(7)
#define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F
#define AS3722_CTRL_SEQU1_AC_OK_PWR_ON BIT(0)
/* GPIO modes */
#define AS3722_GPIO_MODE_MASK 0x07
#define AS3722_GPIO_MODE_INPUT 0x00
#define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02
#define AS3722_GPIO_MODE_ADC_IN 0x03
#define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04
#define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06
#define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07
#define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK)
#define AS3722_GPIO_INV BIT(7)
#define AS3722_GPIO_IOSF_MASK 0x78
#define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3)
#define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0)
#define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1)
#define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2)
#define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3)
#define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4)
#define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5)
#define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6)
#define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7)
#define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8)
#define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9)
#define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11)
#define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12)
#define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13)
#define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14)
#define AS3722_GPIOn_SIGNAL(n) BIT(n)
#define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n)
#define AS3722_I2C_PULL_UP BIT(4)
#define AS3722_INT_PULL_UP BIT(5)
#define AS3722_RTC_REP_WAKEUP_EN BIT(0)
#define AS3722_RTC_ALARM_WAKEUP_EN BIT(1)
#define AS3722_RTC_ON BIT(2)
#define AS3722_RTC_IRQMODE BIT(3)
#define AS3722_RTC_CLK32K_OUT_EN BIT(5)
#define AS3722_WATCHDOG_TIMER_MAX 0x7F
#define AS3722_WATCHDOG_ON BIT(0)
#define AS3722_WATCHDOG_SW_SIG BIT(0)
#define AS3722_EXT_CONTROL_ENABLE1 0x1
#define AS3722_EXT_CONTROL_ENABLE2 0x2
#define AS3722_EXT_CONTROL_ENABLE3 0x3
#define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4)
/* Interrupt IDs */
enum as3722_irq {
AS3722_IRQ_LID,
AS3722_IRQ_ACOK,
AS3722_IRQ_ENABLE1,
AS3722_IRQ_OCCUR_ALARM_SD0,
AS3722_IRQ_ONKEY_LONG_PRESS,
AS3722_IRQ_ONKEY,
AS3722_IRQ_OVTMP,
AS3722_IRQ_LOWBAT,
AS3722_IRQ_SD0_LV,
AS3722_IRQ_SD1_LV,
AS3722_IRQ_SD2_LV,
AS3722_IRQ_PWM1_OV_PROT,
AS3722_IRQ_PWM2_OV_PROT,
AS3722_IRQ_ENABLE2,
AS3722_IRQ_SD6_LV,
AS3722_IRQ_RTC_REP,
AS3722_IRQ_RTC_ALARM,
AS3722_IRQ_GPIO1,
AS3722_IRQ_GPIO2,
AS3722_IRQ_GPIO3,
AS3722_IRQ_GPIO4,
AS3722_IRQ_GPIO5,
AS3722_IRQ_WATCHDOG,
AS3722_IRQ_ENABLE3,
AS3722_IRQ_TEMP_SD0_SHUTDOWN,
AS3722_IRQ_TEMP_SD1_SHUTDOWN,
AS3722_IRQ_TEMP_SD2_SHUTDOWN,
AS3722_IRQ_TEMP_SD0_ALARM,
AS3722_IRQ_TEMP_SD1_ALARM,
AS3722_IRQ_TEMP_SD6_ALARM,
AS3722_IRQ_OCCUR_ALARM_SD6,
AS3722_IRQ_ADC,
AS3722_IRQ_MAX,
};
struct as3722 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
unsigned long irq_flags;
bool en_intern_int_pullup;
bool en_intern_i2c_pullup;
bool en_ac_ok_pwr_on;
struct regmap_irq_chip_data *irq_data;
};
static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)
{
return regmap_read(as3722->regmap, reg, dest);
}
static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value)
{
return regmap_write(as3722->regmap, reg, value);
}
static inline int as3722_block_read(struct as3722 *as3722, u32 reg,
int count, u8 *buf)
{
return regmap_bulk_read(as3722->regmap, reg, buf, count);
}
static inline int as3722_block_write(struct as3722 *as3722, u32 reg,
int count, u8 *data)
{
return regmap_bulk_write(as3722->regmap, reg, data, count);
}
static inline int as3722_update_bits(struct as3722 *as3722, u32 reg,
u32 mask, u8 val)
{
return regmap_update_bits(as3722->regmap, reg, mask, val);
}
static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq)
{
return regmap_irq_get_virq(as3722->irq_data, irq);
}
#endif /* __LINUX_MFD_AS3722_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/atc260x/atc2603c.h
+281
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@@ -0,0 +1,281 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ATC2603C PMIC register definitions
*
* Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
*/
#ifndef __LINUX_MFD_ATC260X_ATC2603C_H
#define __LINUX_MFD_ATC260X_ATC2603C_H
enum atc2603c_irq_def {
ATC2603C_IRQ_AUDIO = 0,
ATC2603C_IRQ_OV,
ATC2603C_IRQ_OC,
ATC2603C_IRQ_OT,
ATC2603C_IRQ_UV,
ATC2603C_IRQ_ALARM,
ATC2603C_IRQ_ONOFF,
ATC2603C_IRQ_SGPIO,
ATC2603C_IRQ_IR,
ATC2603C_IRQ_REMCON,
ATC2603C_IRQ_POWER_IN,
};
/* PMU Registers */
#define ATC2603C_PMU_SYS_CTL0 0x00
#define ATC2603C_PMU_SYS_CTL1 0x01
#define ATC2603C_PMU_SYS_CTL2 0x02
#define ATC2603C_PMU_SYS_CTL3 0x03
#define ATC2603C_PMU_SYS_CTL4 0x04
#define ATC2603C_PMU_SYS_CTL5 0x05
#define ATC2603C_PMU_SYS_CTL6 0x06
#define ATC2603C_PMU_SYS_CTL7 0x07
#define ATC2603C_PMU_SYS_CTL8 0x08
#define ATC2603C_PMU_SYS_CTL9 0x09
#define ATC2603C_PMU_BAT_CTL0 0x0A
#define ATC2603C_PMU_BAT_CTL1 0x0B
#define ATC2603C_PMU_VBUS_CTL0 0x0C
#define ATC2603C_PMU_VBUS_CTL1 0x0D
#define ATC2603C_PMU_WALL_CTL0 0x0E
#define ATC2603C_PMU_WALL_CTL1 0x0F
#define ATC2603C_PMU_SYS_PENDING 0x10
#define ATC2603C_PMU_DC1_CTL0 0x11
#define ATC2603C_PMU_DC1_CTL1 0x12 // Undocumented
#define ATC2603C_PMU_DC1_CTL2 0x13 // Undocumented
#define ATC2603C_PMU_DC2_CTL0 0x14
#define ATC2603C_PMU_DC2_CTL1 0x15 // Undocumented
#define ATC2603C_PMU_DC2_CTL2 0x16 // Undocumented
#define ATC2603C_PMU_DC3_CTL0 0x17
#define ATC2603C_PMU_DC3_CTL1 0x18 // Undocumented
#define ATC2603C_PMU_DC3_CTL2 0x19 // Undocumented
#define ATC2603C_PMU_DC4_CTL0 0x1A // Undocumented
#define ATC2603C_PMU_DC4_CTL1 0x1B // Undocumented
#define ATC2603C_PMU_DC5_CTL0 0x1C // Undocumented
#define ATC2603C_PMU_DC5_CTL1 0x1D // Undocumented
#define ATC2603C_PMU_LDO1_CTL 0x1E
#define ATC2603C_PMU_LDO2_CTL 0x1F
#define ATC2603C_PMU_LDO3_CTL 0x20
#define ATC2603C_PMU_LDO4_CTL 0x21 // Undocumented
#define ATC2603C_PMU_LDO5_CTL 0x22
#define ATC2603C_PMU_LDO6_CTL 0x23
#define ATC2603C_PMU_LDO7_CTL 0x24
#define ATC2603C_PMU_LDO8_CTL 0x25 // Undocumented
#define ATC2603C_PMU_LDO9_CTL 0x26 // Undocumented
#define ATC2603C_PMU_LDO10_CTL 0x27 // Undocumented
#define ATC2603C_PMU_LDO11_CTL 0x28
#define ATC2603C_PMU_SWITCH_CTL 0x29
#define ATC2603C_PMU_OV_CTL0 0x2A
#define ATC2603C_PMU_OV_CTL1 0x2B
#define ATC2603C_PMU_OV_STATUS 0x2C
#define ATC2603C_PMU_OV_EN 0x2D
#define ATC2603C_PMU_OV_INT_EN 0x2E
#define ATC2603C_PMU_OC_CTL 0x2F
#define ATC2603C_PMU_OC_STATUS 0x30
#define ATC2603C_PMU_OC_EN 0x31
#define ATC2603C_PMU_OC_INT_EN 0x32
#define ATC2603C_PMU_UV_CTL0 0x33
#define ATC2603C_PMU_UV_CTL1 0x34
#define ATC2603C_PMU_UV_STATUS 0x35
#define ATC2603C_PMU_UV_EN 0x36
#define ATC2603C_PMU_UV_INT_EN 0x37
#define ATC2603C_PMU_OT_CTL 0x38
#define ATC2603C_PMU_CHARGER_CTL0 0x39
#define ATC2603C_PMU_CHARGER_CTL1 0x3A
#define ATC2603C_PMU_CHARGER_CTL2 0x3B
#define ATC2603C_PMU_BAKCHARGER_CTL 0x3C // Undocumented
#define ATC2603C_PMU_APDS_CTL 0x3D
#define ATC2603C_PMU_AUXADC_CTL0 0x3E
#define ATC2603C_PMU_AUXADC_CTL1 0x3F
#define ATC2603C_PMU_BATVADC 0x40
#define ATC2603C_PMU_BATIADC 0x41
#define ATC2603C_PMU_WALLVADC 0x42
#define ATC2603C_PMU_WALLIADC 0x43
#define ATC2603C_PMU_VBUSVADC 0x44
#define ATC2603C_PMU_VBUSIADC 0x45
#define ATC2603C_PMU_SYSPWRADC 0x46
#define ATC2603C_PMU_REMCONADC 0x47
#define ATC2603C_PMU_SVCCADC 0x48
#define ATC2603C_PMU_CHGIADC 0x49
#define ATC2603C_PMU_IREFADC 0x4A
#define ATC2603C_PMU_BAKBATADC 0x4B
#define ATC2603C_PMU_ICTEMPADC 0x4C
#define ATC2603C_PMU_AUXADC0 0x4D
#define ATC2603C_PMU_AUXADC1 0x4E
#define ATC2603C_PMU_AUXADC2 0x4F
#define ATC2603C_PMU_ICMADC 0x50
#define ATC2603C_PMU_BDG_CTL 0x51 // Undocumented
#define ATC2603C_RTC_CTL 0x52
#define ATC2603C_RTC_MSALM 0x53
#define ATC2603C_RTC_HALM 0x54
#define ATC2603C_RTC_YMDALM 0x55
#define ATC2603C_RTC_MS 0x56
#define ATC2603C_RTC_H 0x57
#define ATC2603C_RTC_DC 0x58
#define ATC2603C_RTC_YMD 0x59
#define ATC2603C_EFUSE_DAT 0x5A // Undocumented
#define ATC2603C_EFUSECRTL1 0x5B // Undocumented
#define ATC2603C_EFUSECRTL2 0x5C // Undocumented
#define ATC2603C_PMU_FW_USE0 0x5D // Undocumented
#define ATC2603C_PMU_FW_USE1 0x5E // Undocumented
#define ATC2603C_PMU_FW_USE2 0x5F // Undocumented
#define ATC2603C_PMU_FW_USE3 0x60 // Undocumented
#define ATC2603C_PMU_FW_USE4 0x61 // Undocumented
#define ATC2603C_PMU_ABNORMAL_STATUS 0x62
#define ATC2603C_PMU_WALL_APDS_CTL 0x63
#define ATC2603C_PMU_REMCON_CTL0 0x64
#define ATC2603C_PMU_REMCON_CTL1 0x65
#define ATC2603C_PMU_MUX_CTL0 0x66
#define ATC2603C_PMU_SGPIO_CTL0 0x67
#define ATC2603C_PMU_SGPIO_CTL1 0x68
#define ATC2603C_PMU_SGPIO_CTL2 0x69
#define ATC2603C_PMU_SGPIO_CTL3 0x6A
#define ATC2603C_PMU_SGPIO_CTL4 0x6B
#define ATC2603C_PWMCLK_CTL 0x6C
#define ATC2603C_PWM0_CTL 0x6D
#define ATC2603C_PWM1_CTL 0x6E
#define ATC2603C_PMU_ADC_DBG0 0x70
#define ATC2603C_PMU_ADC_DBG1 0x71
#define ATC2603C_PMU_ADC_DBG2 0x72
#define ATC2603C_PMU_ADC_DBG3 0x73
#define ATC2603C_PMU_ADC_DBG4 0x74
#define ATC2603C_IRC_CTL 0x80
#define ATC2603C_IRC_STAT 0x81
#define ATC2603C_IRC_CC 0x82
#define ATC2603C_IRC_KDC 0x83
#define ATC2603C_IRC_WK 0x84
#define ATC2603C_IRC_RCC 0x85
#define ATC2603C_IRC_FILTER 0x86
/* AUDIO_OUT Registers */
#define ATC2603C_AUDIOINOUT_CTL 0xA0
#define ATC2603C_AUDIO_DEBUGOUTCTL 0xA1
#define ATC2603C_DAC_DIGITALCTL 0xA2
#define ATC2603C_DAC_VOLUMECTL0 0xA3
#define ATC2603C_DAC_ANALOG0 0xA4
#define ATC2603C_DAC_ANALOG1 0xA5
#define ATC2603C_DAC_ANALOG2 0xA6
#define ATC2603C_DAC_ANALOG3 0xA7
/* AUDIO_IN Registers */
#define ATC2603C_ADC_DIGITALCTL 0xA8
#define ATC2603C_ADC_HPFCTL 0xA9
#define ATC2603C_ADC_CTL 0xAA
#define ATC2603C_AGC_CTL0 0xAB
#define ATC2603C_AGC_CTL1 0xAC // Undocumented
#define ATC2603C_AGC_CTL2 0xAD
#define ATC2603C_ADC_ANALOG0 0xAE
#define ATC2603C_ADC_ANALOG1 0xAF
/* PCM_IF Registers */
#define ATC2603C_PCM0_CTL 0xB0 // Undocumented
#define ATC2603C_PCM1_CTL 0xB1 // Undocumented
#define ATC2603C_PCM2_CTL 0xB2 // Undocumented
#define ATC2603C_PCMIF_CTL 0xB3 // Undocumented
/* CMU_CONTROL Registers */
#define ATC2603C_CMU_DEVRST 0xC1 // Undocumented
/* INTS Registers */
#define ATC2603C_INTS_PD 0xC8
#define ATC2603C_INTS_MSK 0xC9
/* MFP Registers */
#define ATC2603C_MFP_CTL 0xD0
#define ATC2603C_PAD_VSEL 0xD1 // Undocumented
#define ATC2603C_GPIO_OUTEN 0xD2
#define ATC2603C_GPIO_INEN 0xD3
#define ATC2603C_GPIO_DAT 0xD4
#define ATC2603C_PAD_DRV 0xD5
#define ATC2603C_PAD_EN 0xD6
#define ATC2603C_DEBUG_SEL 0xD7 // Undocumented
#define ATC2603C_DEBUG_IE 0xD8 // Undocumented
#define ATC2603C_DEBUG_OE 0xD9 // Undocumented
#define ATC2603C_BIST_START 0x0A // Undocumented
#define ATC2603C_BIST_RESULT 0x0B // Undocumented
#define ATC2603C_CHIP_VER 0xDC
/* TWSI Registers */
#define ATC2603C_SADDR 0xFF
/* PMU_SYS_CTL0 Register Mask Bits */
#define ATC2603C_PMU_SYS_CTL0_IR_WK_EN BIT(5)
#define ATC2603C_PMU_SYS_CTL0_RESET_WK_EN BIT(6)
#define ATC2603C_PMU_SYS_CTL0_HDSW_WK_EN BIT(7)
#define ATC2603C_PMU_SYS_CTL0_ALARM_WK_EN BIT(8)
#define ATC2603C_PMU_SYS_CTL0_REM_CON_WK_EN BIT(9)
#define ATC2603C_PMU_SYS_CTL0_RESTART_EN BIT(10)
#define ATC2603C_PMU_SYS_CTL0_SGPIOIRQ_WK_EN BIT(11)
#define ATC2603C_PMU_SYS_CTL0_ONOFF_SHORT_WK_EN BIT(12)
#define ATC2603C_PMU_SYS_CTL0_ONOFF_LONG_WK_EN BIT(13)
#define ATC2603C_PMU_SYS_CTL0_WALL_WK_EN BIT(14)
#define ATC2603C_PMU_SYS_CTL0_USB_WK_EN BIT(15)
#define ATC2603C_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))
/* PMU_SYS_CTL1 Register Mask Bits */
#define ATC2603C_PMU_SYS_CTL1_EN_S1 BIT(0)
#define ATC2603C_PMU_SYS_CTL1_LB_S4_EN BIT(2)
#define ATC2603C_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3)
#define ATC2603C_PMU_SYS_CTL1_LB_S4_3_1V BIT(4)
#define ATC2603C_PMU_SYS_CTL1_IR_WK_FLAG BIT(5)
#define ATC2603C_PMU_SYS_CTL1_RESET_WK_FLAG BIT(6)
#define ATC2603C_PMU_SYS_CTL1_HDSW_WK_FLAG BIT(7)
#define ATC2603C_PMU_SYS_CTL1_ALARM_WK_FLAG BIT(8)
#define ATC2603C_PMU_SYS_CTL1_REM_CON_WK_FLAG BIT(9)
#define ATC2603C_PMU_SYS_CTL1_ONOFF_PRESS_RESET_IRQ_PD BIT(10)
#define ATC2603C_PMU_SYS_CTL1_SGPIOIRQ_WK_FLAG BIT(11)
#define ATC2603C_PMU_SYS_CTL1_ONOFF_SHORT_WK_FLAG BIT(12)
#define ATC2603C_PMU_SYS_CTL1_ONOFF_LONG_WK_FLAG BIT(13)
#define ATC2603C_PMU_SYS_CTL1_WALL_WK_FLAG BIT(14)
#define ATC2603C_PMU_SYS_CTL1_USB_WK_FLAG BIT(15)
/* PMU_SYS_CTL2 Register Mask Bits */
#define ATC2603C_PMU_SYS_CTL2_PMU_A_EN BIT(0)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_INT_EN BIT(1)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_PD BIT(2)
#define ATC2603C_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3)
#define ATC2603C_PMU_SYS_CTL2_S2_TIMER_EN BIT(6)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_RESET_EN BIT(9)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_INT_EN BIT(12)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_LONG_PRESS BIT(13)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_SHORT_PRESS BIT(14)
#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS BIT(15)
/* PMU_SYS_CTL3 Register Mask Bits */
#define ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7)
#define ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN BIT(9)
#define ATC2603C_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)
#define ATC2603C_PMU_SYS_CTL3_S3_TIMER_EN BIT(13)
#define ATC2603C_PMU_SYS_CTL3_EN_S3 BIT(14)
#define ATC2603C_PMU_SYS_CTL3_EN_S2 BIT(15)
/* PMU_SYS_CTL5 Register Mask Bits */
#define ATC2603C_PMU_SYS_CTL5_WALLWKDTEN BIT(7)
#define ATC2603C_PMU_SYS_CTL5_VBUSWKDTEN BIT(8)
#define ATC2603C_PMU_SYS_CTL5_REMCON_DECT_EN BIT(9)
#define ATC2603C_PMU_SYS_CTL5_ONOFF_8S_SEL BIT(10)
/* INTS_MSK Register Mask Bits */
#define ATC2603C_INTS_MSK_AUDIO BIT(0)
#define ATC2603C_INTS_MSK_OV BIT(1)
#define ATC2603C_INTS_MSK_OC BIT(2)
#define ATC2603C_INTS_MSK_OT BIT(3)
#define ATC2603C_INTS_MSK_UV BIT(4)
#define ATC2603C_INTS_MSK_ALARM BIT(5)
#define ATC2603C_INTS_MSK_ONOFF BIT(6)
#define ATC2603C_INTS_MSK_SGPIO BIT(7)
#define ATC2603C_INTS_MSK_IR BIT(8)
#define ATC2603C_INTS_MSK_REMCON BIT(9)
#define ATC2603C_INTS_MSK_POWERIN BIT(10)
/* CMU_DEVRST Register Mask Bits */
#define ATC2603C_CMU_DEVRST_MFP BIT(1)
#define ATC2603C_CMU_DEVRST_INTS BIT(2)
#define ATC2603C_CMU_DEVRST_AUDIO BIT(4)
/* PAD_EN Register Mask Bits */
#define ATC2603C_PAD_EN_EXTIRQ BIT(0)
#endif /* __LINUX_MFD_ATC260X_ATC2603C_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/atc260x/atc2609a.h
+308
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@@ -0,0 +1,308 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ATC2609A PMIC register definitions
*
* Copyright (C) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#ifndef __LINUX_MFD_ATC260X_ATC2609A_H
#define __LINUX_MFD_ATC260X_ATC2609A_H
enum atc2609a_irq_def {
ATC2609A_IRQ_AUDIO = 0,
ATC2609A_IRQ_OV,
ATC2609A_IRQ_OC,
ATC2609A_IRQ_OT,
ATC2609A_IRQ_UV,
ATC2609A_IRQ_ALARM,
ATC2609A_IRQ_ONOFF,
ATC2609A_IRQ_WKUP,
ATC2609A_IRQ_IR,
ATC2609A_IRQ_REMCON,
ATC2609A_IRQ_POWER_IN,
};
/* PMU Registers */
#define ATC2609A_PMU_SYS_CTL0 0x00
#define ATC2609A_PMU_SYS_CTL1 0x01
#define ATC2609A_PMU_SYS_CTL2 0x02
#define ATC2609A_PMU_SYS_CTL3 0x03
#define ATC2609A_PMU_SYS_CTL4 0x04
#define ATC2609A_PMU_SYS_CTL5 0x05
#define ATC2609A_PMU_SYS_CTL6 0x06
#define ATC2609A_PMU_SYS_CTL7 0x07
#define ATC2609A_PMU_SYS_CTL8 0x08
#define ATC2609A_PMU_SYS_CTL9 0x09
#define ATC2609A_PMU_BAT_CTL0 0x0A
#define ATC2609A_PMU_BAT_CTL1 0x0B
#define ATC2609A_PMU_VBUS_CTL0 0x0C
#define ATC2609A_PMU_VBUS_CTL1 0x0D
#define ATC2609A_PMU_WALL_CTL0 0x0E
#define ATC2609A_PMU_WALL_CTL1 0x0F
#define ATC2609A_PMU_SYS_PENDING 0x10
#define ATC2609A_PMU_APDS_CTL0 0x11
#define ATC2609A_PMU_APDS_CTL1 0x12
#define ATC2609A_PMU_APDS_CTL2 0x13
#define ATC2609A_PMU_CHARGER_CTL 0x14
#define ATC2609A_PMU_BAKCHARGER_CTL 0x15
#define ATC2609A_PMU_SWCHG_CTL0 0x16
#define ATC2609A_PMU_SWCHG_CTL1 0x17
#define ATC2609A_PMU_SWCHG_CTL2 0x18
#define ATC2609A_PMU_SWCHG_CTL3 0x19
#define ATC2609A_PMU_SWCHG_CTL4 0x1A
#define ATC2609A_PMU_DC_OSC 0x1B
#define ATC2609A_PMU_DC0_CTL0 0x1C
#define ATC2609A_PMU_DC0_CTL1 0x1D
#define ATC2609A_PMU_DC0_CTL2 0x1E
#define ATC2609A_PMU_DC0_CTL3 0x1F
#define ATC2609A_PMU_DC0_CTL4 0x20
#define ATC2609A_PMU_DC0_CTL5 0x21
#define ATC2609A_PMU_DC0_CTL6 0x22
#define ATC2609A_PMU_DC1_CTL0 0x23
#define ATC2609A_PMU_DC1_CTL1 0x24
#define ATC2609A_PMU_DC1_CTL2 0x25
#define ATC2609A_PMU_DC1_CTL3 0x26
#define ATC2609A_PMU_DC1_CTL4 0x27
#define ATC2609A_PMU_DC1_CTL5 0x28
#define ATC2609A_PMU_DC1_CTL6 0x29
#define ATC2609A_PMU_DC2_CTL0 0x2A
#define ATC2609A_PMU_DC2_CTL1 0x2B
#define ATC2609A_PMU_DC2_CTL2 0x2C
#define ATC2609A_PMU_DC2_CTL3 0x2D
#define ATC2609A_PMU_DC2_CTL4 0x2E
#define ATC2609A_PMU_DC2_CTL5 0x2F
#define ATC2609A_PMU_DC2_CTL6 0x30
#define ATC2609A_PMU_DC3_CTL0 0x31
#define ATC2609A_PMU_DC3_CTL1 0x32
#define ATC2609A_PMU_DC3_CTL2 0x33
#define ATC2609A_PMU_DC3_CTL3 0x34
#define ATC2609A_PMU_DC3_CTL4 0x35
#define ATC2609A_PMU_DC3_CTL5 0x36
#define ATC2609A_PMU_DC3_CTL6 0x37
#define ATC2609A_PMU_DC_ZR 0x38
#define ATC2609A_PMU_LDO0_CTL0 0x39
#define ATC2609A_PMU_LDO0_CTL1 0x3A
#define ATC2609A_PMU_LDO1_CTL0 0x3B
#define ATC2609A_PMU_LDO1_CTL1 0x3C
#define ATC2609A_PMU_LDO2_CTL0 0x3D
#define ATC2609A_PMU_LDO2_CTL1 0x3E
#define ATC2609A_PMU_LDO3_CTL0 0x3F
#define ATC2609A_PMU_LDO3_CTL1 0x40
#define ATC2609A_PMU_LDO4_CTL0 0x41
#define ATC2609A_PMU_LDO4_CTL1 0x42
#define ATC2609A_PMU_LDO5_CTL0 0x43
#define ATC2609A_PMU_LDO5_CTL1 0x44
#define ATC2609A_PMU_LDO6_CTL0 0x45
#define ATC2609A_PMU_LDO6_CTL1 0x46
#define ATC2609A_PMU_LDO7_CTL0 0x47
#define ATC2609A_PMU_LDO7_CTL1 0x48
#define ATC2609A_PMU_LDO8_CTL0 0x49
#define ATC2609A_PMU_LDO8_CTL1 0x4A
#define ATC2609A_PMU_LDO9_CTL 0x4B
#define ATC2609A_PMU_OV_INT_EN 0x4C
#define ATC2609A_PMU_OV_STATUS 0x4D
#define ATC2609A_PMU_UV_INT_EN 0x4E
#define ATC2609A_PMU_UV_STATUS 0x4F
#define ATC2609A_PMU_OC_INT_EN 0x50
#define ATC2609A_PMU_OC_STATUS 0x51
#define ATC2609A_PMU_OT_CTL 0x52
#define ATC2609A_PMU_CM_CTL0 0x53
#define ATC2609A_PMU_FW_USE0 0x54
#define ATC2609A_PMU_FW_USE1 0x55
#define ATC2609A_PMU_ADC12B_I 0x56
#define ATC2609A_PMU_ADC12B_V 0x57
#define ATC2609A_PMU_ADC12B_DUMMY 0x58
#define ATC2609A_PMU_AUXADC_CTL0 0x59
#define ATC2609A_PMU_AUXADC_CTL1 0x5A
#define ATC2609A_PMU_BATVADC 0x5B
#define ATC2609A_PMU_BATIADC 0x5C
#define ATC2609A_PMU_WALLVADC 0x5D
#define ATC2609A_PMU_WALLIADC 0x5E
#define ATC2609A_PMU_VBUSVADC 0x5F
#define ATC2609A_PMU_VBUSIADC 0x60
#define ATC2609A_PMU_SYSPWRADC 0x61
#define ATC2609A_PMU_REMCONADC 0x62
#define ATC2609A_PMU_SVCCADC 0x63
#define ATC2609A_PMU_CHGIADC 0x64
#define ATC2609A_PMU_IREFADC 0x65
#define ATC2609A_PMU_BAKBATADC 0x66
#define ATC2609A_PMU_ICTEMPADC 0x67
#define ATC2609A_PMU_AUXADC0 0x68
#define ATC2609A_PMU_AUXADC1 0x69
#define ATC2609A_PMU_AUXADC2 0x6A
#define ATC2609A_PMU_AUXADC3 0x6B
#define ATC2609A_PMU_ICTEMPADC_ADJ 0x6C
#define ATC2609A_PMU_BDG_CTL 0x6D
#define ATC2609A_RTC_CTL 0x6E
#define ATC2609A_RTC_MSALM 0x6F
#define ATC2609A_RTC_HALM 0x70
#define ATC2609A_RTC_YMDALM 0x71
#define ATC2609A_RTC_MS 0x72
#define ATC2609A_RTC_H 0x73
#define ATC2609A_RTC_DC 0x74
#define ATC2609A_RTC_YMD 0x75
#define ATC2609A_EFUSE_DAT 0x76
#define ATC2609A_EFUSECRTL1 0x77
#define ATC2609A_EFUSECRTL2 0x78
#define ATC2609A_PMU_DC4_CTL0 0x79
#define ATC2609A_PMU_DC4_CTL1 0x7A
#define ATC2609A_PMU_DC4_CTL2 0x7B
#define ATC2609A_PMU_DC4_CTL3 0x7C
#define ATC2609A_PMU_DC4_CTL4 0x7D
#define ATC2609A_PMU_DC4_CTL5 0x7E
#define ATC2609A_PMU_DC4_CTL6 0x7F
#define ATC2609A_PMU_PWR_STATUS 0x80
#define ATC2609A_PMU_S2_PWR 0x81
#define ATC2609A_CLMT_CTL0 0x82
#define ATC2609A_CLMT_DATA0 0x83
#define ATC2609A_CLMT_DATA1 0x84
#define ATC2609A_CLMT_DATA2 0x85
#define ATC2609A_CLMT_DATA3 0x86
#define ATC2609A_CLMT_ADD0 0x87
#define ATC2609A_CLMT_ADD1 0x88
#define ATC2609A_CLMT_OCV_TABLE 0x89
#define ATC2609A_CLMT_R_TABLE 0x8A
#define ATC2609A_PMU_PWRON_CTL0 0x8D
#define ATC2609A_PMU_PWRON_CTL1 0x8E
#define ATC2609A_PMU_PWRON_CTL2 0x8F
#define ATC2609A_IRC_CTL 0x90
#define ATC2609A_IRC_STAT 0x91
#define ATC2609A_IRC_CC 0x92
#define ATC2609A_IRC_KDC 0x93
#define ATC2609A_IRC_WK 0x94
#define ATC2609A_IRC_RCC 0x95
/* AUDIO_OUT Registers */
#define ATC2609A_AUDIOINOUT_CTL 0xA0
#define ATC2609A_AUDIO_DEBUGOUTCTL 0xA1
#define ATC2609A_DAC_DIGITALCTL 0xA2
#define ATC2609A_DAC_VOLUMECTL0 0xA3
#define ATC2609A_DAC_ANALOG0 0xA4
#define ATC2609A_DAC_ANALOG1 0xA5
#define ATC2609A_DAC_ANALOG2 0xA6
#define ATC2609A_DAC_ANALOG3 0xA7
/* AUDIO_IN Registers */
#define ATC2609A_ADC_DIGITALCTL 0xA8
#define ATC2609A_ADC_HPFCTL 0xA9
#define ATC2609A_ADC_CTL 0xAA
#define ATC2609A_AGC_CTL0 0xAB
#define ATC2609A_AGC_CTL1 0xAC
#define ATC2609A_AGC_CTL2 0xAD
#define ATC2609A_ADC_ANALOG0 0xAE
#define ATC2609A_ADC_ANALOG1 0xAF
/* PCM_IF Registers */
#define ATC2609A_PCM0_CTL 0xB0
#define ATC2609A_PCM1_CTL 0xB1
#define ATC2609A_PCM2_CTL 0xB2
#define ATC2609A_PCMIF_CTL 0xB3
/* CMU_CONTROL Registers */
#define ATC2609A_CMU_DEVRST 0xC1
/* INTS Registers */
#define ATC2609A_INTS_PD 0xC8
#define ATC2609A_INTS_MSK 0xC9
/* MFP Registers */
#define ATC2609A_MFP_CTL 0xD0
#define ATC2609A_PAD_VSEL 0xD1
#define ATC2609A_GPIO_OUTEN 0xD2
#define ATC2609A_GPIO_INEN 0xD3
#define ATC2609A_GPIO_DAT 0xD4
#define ATC2609A_PAD_DRV 0xD5
#define ATC2609A_PAD_EN 0xD6
#define ATC2609A_DEBUG_SEL 0xD7
#define ATC2609A_DEBUG_IE 0xD8
#define ATC2609A_DEBUG_OE 0xD9
#define ATC2609A_CHIP_VER 0xDC
/* PWSI Registers */
#define ATC2609A_PWSI_CTL 0xF0
#define ATC2609A_PWSI_STATUS 0xF1
/* TWSI Registers */
#define ATC2609A_SADDR 0xFF
/* PMU_SYS_CTL0 Register Mask Bits */
#define ATC2609A_PMU_SYS_CTL0_IR_WK_EN BIT(5)
#define ATC2609A_PMU_SYS_CTL0_RESET_WK_EN BIT(6)
#define ATC2609A_PMU_SYS_CTL0_HDSW_WK_EN BIT(7)
#define ATC2609A_PMU_SYS_CTL0_ALARM_WK_EN BIT(8)
#define ATC2609A_PMU_SYS_CTL0_REM_CON_WK_EN BIT(9)
#define ATC2609A_PMU_SYS_CTL0_RESTART_EN BIT(10)
#define ATC2609A_PMU_SYS_CTL0_WKIRQ_WK_EN BIT(11)
#define ATC2609A_PMU_SYS_CTL0_ONOFF_SHORT_WK_EN BIT(12)
#define ATC2609A_PMU_SYS_CTL0_ONOFF_LONG_WK_EN BIT(13)
#define ATC2609A_PMU_SYS_CTL0_WALL_WK_EN BIT(14)
#define ATC2609A_PMU_SYS_CTL0_USB_WK_EN BIT(15)
#define ATC2609A_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))
/* PMU_SYS_CTL1 Register Mask Bits */
#define ATC2609A_PMU_SYS_CTL1_EN_S1 BIT(0)
#define ATC2609A_PMU_SYS_CTL1_LB_S4_EN BIT(2)
#define ATC2609A_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3)
#define ATC2609A_PMU_SYS_CTL1_LB_S4_3_1V BIT(4)
#define ATC2609A_PMU_SYS_CTL1_IR_WK_FLAG BIT(5)
#define ATC2609A_PMU_SYS_CTL1_RESET_WK_FLAG BIT(6)
#define ATC2609A_PMU_SYS_CTL1_HDSW_WK_FLAG BIT(7)
#define ATC2609A_PMU_SYS_CTL1_ALARM_WK_FLAG BIT(8)
#define ATC2609A_PMU_SYS_CTL1_REM_CON_WK_FLAG BIT(9)
#define ATC2609A_PMU_SYS_CTL1_RESTART_WK_FLAG BIT(10)
#define ATC2609A_PMU_SYS_CTL1_WKIRQ_WK_FLAG BIT(11)
#define ATC2609A_PMU_SYS_CTL1_ONOFF_SHORT_WK_FLAG BIT(12)
#define ATC2609A_PMU_SYS_CTL1_ONOFF_LONG_WK_FLAG BIT(13)
#define ATC2609A_PMU_SYS_CTL1_WALL_WK_FLAG BIT(14)
#define ATC2609A_PMU_SYS_CTL1_USB_WK_FLAG BIT(15)
/* PMU_SYS_CTL2 Register Mask Bits */
#define ATC2609A_PMU_SYS_CTL2_PMU_A_EN BIT(0)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_INT_EN BIT(1)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_PD BIT(2)
#define ATC2609A_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3)
#define ATC2609A_PMU_SYS_CTL2_S2_TIMER_EN BIT(6)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_EN BIT(9)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_LSP_INT_EN BIT(12)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_LONG_PRESS BIT(13)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_SHORT_PRESS BIT(14)
#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS BIT(15)
/* PMU_SYS_CTL3 Register Mask Bits */
#define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7)
#define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN BIT(9)
#define ATC2609A_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)
#define ATC2609A_PMU_SYS_CTL3_S3_TIMER_EN BIT(13)
#define ATC2609A_PMU_SYS_CTL3_EN_S3 BIT(14)
#define ATC2609A_PMU_SYS_CTL3_EN_S2 BIT(15)
/* PMU_SYS_CTL5 Register Mask Bits */
#define ATC2609A_PMU_SYS_CTL5_WALLWKDTEN BIT(7)
#define ATC2609A_PMU_SYS_CTL5_VBUSWKDTEN BIT(8)
#define ATC2609A_PMU_SYS_CTL5_REMCON_DECT_EN BIT(9)
#define ATC2609A_PMU_SYS_CTL5_ONOFF_8S_SEL BIT(10)
/* INTS_MSK Register Mask Bits */
#define ATC2609A_INTS_MSK_AUDIO BIT(0)
#define ATC2609A_INTS_MSK_OV BIT(1)
#define ATC2609A_INTS_MSK_OC BIT(2)
#define ATC2609A_INTS_MSK_OT BIT(3)
#define ATC2609A_INTS_MSK_UV BIT(4)
#define ATC2609A_INTS_MSK_ALARM BIT(5)
#define ATC2609A_INTS_MSK_ONOFF BIT(6)
#define ATC2609A_INTS_MSK_WKUP BIT(7)
#define ATC2609A_INTS_MSK_IR BIT(8)
#define ATC2609A_INTS_MSK_REMCON BIT(9)
#define ATC2609A_INTS_MSK_POWERIN BIT(10)
/* CMU_DEVRST Register Mask Bits */
#define ATC2609A_CMU_DEVRST_AUDIO BIT(0)
#define ATC2609A_CMU_DEVRST_MFP BIT(1)
#define ATC2609A_CMU_DEVRST_INTS BIT(2)
/* PAD_EN Register Mask Bits */
#define ATC2609A_PAD_EN_EXTIRQ BIT(0)
#endif /* __LINUX_MFD_ATC260X_ATC2609A_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/atc260x/core.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Core MFD defines for ATC260x PMICs
*
* Copyright (C) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
*/
#ifndef __LINUX_MFD_ATC260X_CORE_H
#define __LINUX_MFD_ATC260X_CORE_H
#include <linux/mfd/atc260x/atc2603c.h>
#include <linux/mfd/atc260x/atc2609a.h>
enum atc260x_type {
ATC2603A = 0,
ATC2603C,
ATC2609A,
};
enum atc260x_ver {
ATC260X_A = 0,
ATC260X_B,
ATC260X_C,
ATC260X_D,
ATC260X_E,
ATC260X_F,
ATC260X_G,
ATC260X_H,
};
struct atc260x {
struct device *dev;
struct regmap *regmap;
const struct regmap_irq_chip *regmap_irq_chip;
struct regmap_irq_chip_data *irq_data;
struct mutex *regmap_mutex; /* mutex for custom regmap locking */
const struct mfd_cell *cells;
int nr_cells;
int irq;
enum atc260x_type ic_type;
enum atc260x_ver ic_ver;
const char *type_name;
unsigned int rev_reg;
const struct atc260x_init_regs *init_regs; /* regs for device init */
};
struct regmap_config;
int atc260x_match_device(struct atc260x *atc260x, struct regmap_config *regmap_cfg);
int atc260x_device_probe(struct atc260x *atc260x);
#endif /* __LINUX_MFD_ATC260X_CORE_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/atmel-hlcdc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Free Electrons
* Copyright (C) 2014 Atmel
*
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
*/
#ifndef __LINUX_MFD_HLCDC_H
#define __LINUX_MFD_HLCDC_H
#include <linux/clk.h>
#include <linux/regmap.h>
#define ATMEL_HLCDC_CFG(i) ((i) * 0x4)
#define ATMEL_HLCDC_SIG_CFG LCDCFG(5)
#define ATMEL_HLCDC_HSPOL BIT(0)
#define ATMEL_HLCDC_VSPOL BIT(1)
#define ATMEL_HLCDC_VSPDLYS BIT(2)
#define ATMEL_HLCDC_VSPDLYE BIT(3)
#define ATMEL_HLCDC_DISPPOL BIT(4)
#define ATMEL_HLCDC_DITHER BIT(6)
#define ATMEL_HLCDC_DISPDLY BIT(7)
#define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8)
#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8)
#define ATMEL_XLCDC_DPI BIT(11)
#define ATMEL_HLCDC_PP BIT(10)
#define ATMEL_HLCDC_VSPSU BIT(12)
#define ATMEL_HLCDC_VSPHO BIT(13)
#define ATMEL_HLCDC_GUARDTIME_MASK GENMASK(20, 16)
#define ATMEL_HLCDC_EN 0x20
#define ATMEL_HLCDC_DIS 0x24
#define ATMEL_HLCDC_SR 0x28
#define ATMEL_HLCDC_IER 0x2c
#define ATMEL_HLCDC_IDR 0x30
#define ATMEL_HLCDC_IMR 0x34
#define ATMEL_HLCDC_ISR 0x38
#define ATMEL_XLCDC_ATTRE 0x3c
#define ATMEL_XLCDC_BASE_UPDATE BIT(0)
#define ATMEL_XLCDC_OVR1_UPDATE BIT(1)
#define ATMEL_XLCDC_OVR3_UPDATE BIT(2)
#define ATMEL_XLCDC_HEO_UPDATE BIT(3)
#define ATMEL_HLCDC_CLKPOL BIT(0)
#define ATMEL_HLCDC_CLKSEL BIT(2)
#define ATMEL_HLCDC_CLKPWMSEL BIT(3)
#define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i))
#define ATMEL_HLCDC_CLKDIV_SHFT 16
#define ATMEL_HLCDC_CLKDIV_MASK GENMASK(23, 16)
#define ATMEL_HLCDC_CLKDIV(div) ((div - 2) << ATMEL_HLCDC_CLKDIV_SHFT)
#define ATMEL_HLCDC_PIXEL_CLK BIT(0)
#define ATMEL_HLCDC_SYNC BIT(1)
#define ATMEL_HLCDC_DISP BIT(2)
#define ATMEL_HLCDC_PWM BIT(3)
#define ATMEL_HLCDC_SIP BIT(4)
#define ATMEL_XLCDC_SD BIT(5)
#define ATMEL_XLCDC_CM BIT(6)
#define ATMEL_HLCDC_SOF BIT(0)
#define ATMEL_HLCDC_SYNCDIS BIT(1)
#define ATMEL_HLCDC_FIFOERR BIT(4)
#define ATMEL_HLCDC_LAYER_STATUS(x) BIT((x) + 8)
/**
* Structure shared by the MFD device and its subdevices.
*
* @regmap: register map used to access HLCDC IP registers
* @periph_clk: the hlcdc peripheral clock
* @sys_clk: the hlcdc system clock
* @slow_clk: the system slow clk
* @irq: the hlcdc irq
*/
struct atmel_hlcdc {
struct regmap *regmap;
struct clk *lvds_pll_clk;
struct clk *periph_clk;
struct clk *sys_clk;
struct clk *slow_clk;
int irq;
};
#endif /* __LINUX_MFD_HLCDC_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/axp20x.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/bcm2835-pm.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef BCM2835_MFD_PM_H
#define BCM2835_MFD_PM_H
#include <linux/regmap.h>
enum bcm2835_soc {
BCM2835_PM_SOC_BCM2835,
BCM2835_PM_SOC_BCM2711,
BCM2835_PM_SOC_BCM2712,
};
struct bcm2835_pm {
struct device *dev;
void __iomem *base;
void __iomem *asb;
void __iomem *rpivid_asb;
enum bcm2835_soc soc;
};
#endif /* BCM2835_MFD_PM_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/bcm590xx.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Broadcom BCM590xx PMU
*
* Copyright 2014 Linaro Limited
* Author: Matt Porter <mporter@linaro.org>
*/
#ifndef __LINUX_MFD_BCM590XX_H
#define __LINUX_MFD_BCM590XX_H
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
/* PMU ID register values; also used as device type */
#define BCM590XX_PMUID_BCM59054 0x54
#define BCM590XX_PMUID_BCM59056 0x56
/* Known chip revision IDs */
#define BCM59054_REV_DIGITAL_A1 1
#define BCM59054_REV_ANALOG_A1 2
#define BCM59056_REV_DIGITAL_A0 1
#define BCM59056_REV_ANALOG_A0 1
#define BCM59056_REV_DIGITAL_B0 2
#define BCM59056_REV_ANALOG_B0 2
/* regmap types */
enum bcm590xx_regmap_type {
BCM590XX_REGMAP_PRI,
BCM590XX_REGMAP_SEC,
};
/* max register address */
#define BCM590XX_MAX_REGISTER_PRI 0xe7
#define BCM590XX_MAX_REGISTER_SEC 0xf0
struct bcm590xx {
struct device *dev;
struct i2c_client *i2c_pri;
struct i2c_client *i2c_sec;
struct regmap *regmap_pri;
struct regmap *regmap_sec;
/* PMU ID value; also used as device type */
u8 pmu_id;
/* Chip revision, read from PMUREV reg */
u8 rev_digital;
u8 rev_analog;
};
#endif /* __LINUX_MFD_BCM590XX_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/bd9571mwv.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* ROHM BD9571MWV-M and BD9574MWF-M driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
* Copyright (C) 2020 Renesas Electronics Corporation
*
* Based on the TPS65086 driver
*/
#ifndef __LINUX_MFD_BD9571MWV_H
#define __LINUX_MFD_BD9571MWV_H
#include <linux/device.h>
#include <linux/regmap.h>
/* List of registers for BD9571MWV and BD9574MWF */
#define BD9571MWV_VENDOR_CODE 0x00
#define BD9571MWV_VENDOR_CODE_VAL 0xdb
#define BD9571MWV_PRODUCT_CODE 0x01
#define BD9571MWV_PRODUCT_CODE_BD9571MWV 0x60
#define BD9571MWV_PRODUCT_CODE_BD9574MWF 0x74
#define BD9571MWV_PRODUCT_REVISION 0x02
#define BD9571MWV_I2C_FUSA_MODE 0x10
#define BD9571MWV_I2C_MD2_E1_BIT_1 0x11
#define BD9571MWV_I2C_MD2_E1_BIT_2 0x12
#define BD9571MWV_BKUP_MODE_CNT 0x20
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK GENMASK(3, 0)
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0 BIT(0)
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1 BIT(1)
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C BIT(2)
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C BIT(3)
#define BD9571MWV_BKUP_MODE_STATUS 0x21
#define BD9571MWV_BKUP_RECOVERY_CNT 0x22
#define BD9571MWV_BKUP_CTRL_TIM_CNT 0x23
#define BD9571MWV_WAITBKUP_WDT_CNT 0x24
#define BD9571MWV_128H_TIM_CNT 0x26
#define BD9571MWV_QLLM_CNT 0x27
#define BD9571MWV_AVS_SET_MONI 0x31
#define BD9571MWV_AVS_SET_MONI_MASK 0x3
#define BD9571MWV_AVS_VD09_VID(n) (0x32 + (n))
#define BD9571MWV_AVS_DVFS_VID(n) (0x36 + (n))
#define BD9571MWV_VD18_VID 0x42
#define BD9571MWV_VD25_VID 0x43
#define BD9571MWV_VD33_VID 0x44
#define BD9571MWV_DVFS_VINIT 0x50
#define BD9574MWF_VD09_VINIT 0x51
#define BD9571MWV_DVFS_SETVMAX 0x52
#define BD9571MWV_DVFS_BOOSTVID 0x53
#define BD9571MWV_DVFS_SETVID 0x54
#define BD9571MWV_DVFS_MONIVDAC 0x55
#define BD9571MWV_DVFS_PGD_CNT 0x56
#define BD9571MWV_GPIO_DIR 0x60
#define BD9571MWV_GPIO_OUT 0x61
#define BD9571MWV_GPIO_IN 0x62
#define BD9571MWV_GPIO_DEB 0x63
#define BD9571MWV_GPIO_INT_SET 0x64
#define BD9571MWV_GPIO_INT 0x65
#define BD9571MWV_GPIO_INTMASK 0x66
#define BD9574MWF_GPIO_MUX 0x67
#define BD9571MWV_REG_KEEP(n) (0x70 + (n))
#define BD9571MWV_PMIC_INTERNAL_STATUS 0x80
#define BD9571MWV_PROT_ERROR_STATUS0 0x81
#define BD9571MWV_PROT_ERROR_STATUS1 0x82
#define BD9571MWV_PROT_ERROR_STATUS2 0x83
#define BD9571MWV_PROT_ERROR_STATUS3 0x84
#define BD9571MWV_PROT_ERROR_STATUS4 0x85
#define BD9574MWF_PROT_ERROR_STATUS5 0x86
#define BD9574MWF_SYSTEM_ERROR_STATUS 0x87
#define BD9571MWV_INT_INTREQ 0x90
#define BD9571MWV_INT_INTREQ_MD1_INT BIT(0)
#define BD9571MWV_INT_INTREQ_MD2_E1_INT BIT(1)
#define BD9571MWV_INT_INTREQ_MD2_E2_INT BIT(2)
#define BD9571MWV_INT_INTREQ_PROT_ERR_INT BIT(3)
#define BD9571MWV_INT_INTREQ_GP_INT BIT(4)
#define BD9571MWV_INT_INTREQ_128H_OF_INT BIT(5)
#define BD9571MWV_INT_INTREQ_WDT_OF_INT BIT(6)
#define BD9571MWV_INT_INTREQ_BKUP_TRG_INT BIT(7)
#define BD9571MWV_INT_INTMASK 0x91
#define BD9574MWF_SSCG_CNT 0xA0
#define BD9574MWF_POFFB_MRB 0xA1
#define BD9574MWF_SMRB_WR_PROT 0xA2
#define BD9574MWF_SMRB_ASSERT 0xA3
#define BD9574MWF_SMRB_STATUS 0xA4
#define BD9571MWV_ACCESS_KEY 0xff
/* Define the BD9571MWV IRQ numbers */
enum bd9571mwv_irqs {
BD9571MWV_IRQ_MD1,
BD9571MWV_IRQ_MD2_E1,
BD9571MWV_IRQ_MD2_E2,
BD9571MWV_IRQ_PROT_ERR,
BD9571MWV_IRQ_GP,
BD9571MWV_IRQ_128H_OF, /* BKUP_HOLD on BD9574MWF */
BD9571MWV_IRQ_WDT_OF,
BD9571MWV_IRQ_BKUP_TRG,
};
#endif /* __LINUX_MFD_BD9571MWV_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/bq257xx.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Register definitions for TI BQ257XX
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
*/
#define BQ25703_CHARGE_OPTION_0 0x00
#define BQ25703_CHARGE_CURRENT 0x02
#define BQ25703_MAX_CHARGE_VOLT 0x04
#define BQ25703_OTG_VOLT 0x06
#define BQ25703_OTG_CURRENT 0x08
#define BQ25703_INPUT_VOLTAGE 0x0a
#define BQ25703_MIN_VSYS 0x0c
#define BQ25703_IIN_HOST 0x0e
#define BQ25703_CHARGER_STATUS 0x20
#define BQ25703_PROCHOT_STATUS 0x22
#define BQ25703_IIN_DPM 0x24
#define BQ25703_ADCIBAT_CHG 0x28
#define BQ25703_ADCIINCMPIN 0x2a
#define BQ25703_ADCVSYSVBAT 0x2c
#define BQ25703_MANUFACT_DEV_ID 0x2e
#define BQ25703_CHARGE_OPTION_1 0x30
#define BQ25703_CHARGE_OPTION_2 0x32
#define BQ25703_CHARGE_OPTION_3 0x34
#define BQ25703_ADC_OPTION 0x3a
#define BQ25703_EN_LWPWR BIT(15)
#define BQ25703_WDTMR_ADJ_MASK GENMASK(14, 13)
#define BQ25703_WDTMR_DISABLE 0
#define BQ25703_WDTMR_5_SEC 1
#define BQ25703_WDTMR_88_SEC 2
#define BQ25703_WDTMR_175_SEC 3
#define BQ25703_ICHG_MASK GENMASK(12, 6)
#define BQ25703_ICHG_STEP_UA 64000
#define BQ25703_ICHG_MIN_UA 64000
#define BQ25703_ICHG_MAX_UA 8128000
#define BQ25703_MAX_CHARGE_VOLT_MASK GENMASK(15, 4)
#define BQ25703_VBATREG_STEP_UV 16000
#define BQ25703_VBATREG_MIN_UV 1024000
#define BQ25703_VBATREG_MAX_UV 19200000
#define BQ25703_OTG_VOLT_MASK GENMASK(13, 6)
#define BQ25703_OTG_VOLT_STEP_UV 64000
#define BQ25703_OTG_VOLT_MIN_UV 4480000
#define BQ25703_OTG_VOLT_MAX_UV 20800000
#define BQ25703_OTG_VOLT_NUM_VOLT 256
#define BQ25703_OTG_CUR_MASK GENMASK(14, 8)
#define BQ25703_OTG_CUR_STEP_UA 50000
#define BQ25703_OTG_CUR_MAX_UA 6350000
#define BQ25703_MINVSYS_MASK GENMASK(13, 8)
#define BQ25703_MINVSYS_STEP_UV 256000
#define BQ25703_MINVSYS_MIN_UV 1024000
#define BQ25703_MINVSYS_MAX_UV 16128000
#define BQ25703_STS_AC_STAT BIT(15)
#define BQ25703_STS_IN_FCHRG BIT(10)
#define BQ25703_STS_IN_PCHRG BIT(9)
#define BQ25703_STS_FAULT_ACOV BIT(7)
#define BQ25703_STS_FAULT_BATOC BIT(6)
#define BQ25703_STS_FAULT_ACOC BIT(5)
#define BQ25703_IINDPM_MASK GENMASK(14, 8)
#define BQ25703_IINDPM_STEP_UA 50000
#define BQ25703_IINDPM_MIN_UA 50000
#define BQ25703_IINDPM_MAX_UA 6400000
#define BQ25703_IINDPM_DEFAULT_UA 3300000
#define BQ25703_IINDPM_OFFSET_UA 50000
#define BQ25703_ADCIBAT_DISCHG_MASK GENMASK(6, 0)
#define BQ25703_ADCIBAT_CHG_MASK GENMASK(14, 8)
#define BQ25703_ADCIBAT_CHG_STEP_UA 64000
#define BQ25703_ADCIBAT_DIS_STEP_UA 256000
#define BQ25703_ADCIIN GENMASK(15, 8)
#define BQ25703_ADCIINCMPIN_STEP 50000
#define BQ25703_ADCVSYS_MASK GENMASK(15, 8)
#define BQ25703_ADCVBAT_MASK GENMASK(7, 0)
#define BQ25703_ADCVSYSVBAT_OFFSET_UV 2880000
#define BQ25703_ADCVSYSVBAT_STEP 64000
#define BQ25703_ADC_CH_MASK GENMASK(7, 0)
#define BQ25703_ADC_CONV_EN BIT(15)
#define BQ25703_ADC_START BIT(14)
#define BQ25703_ADC_FULL_SCALE BIT(13)
#define BQ25703_ADC_CMPIN_EN BIT(7)
#define BQ25703_ADC_VBUS_EN BIT(6)
#define BQ25703_ADC_PSYS_EN BIT(5)
#define BQ25703_ADC_IIN_EN BIT(4)
#define BQ25703_ADC_IDCHG_EN BIT(3)
#define BQ25703_ADC_ICHG_EN BIT(2)
#define BQ25703_ADC_VSYS_EN BIT(1)
#define BQ25703_ADC_VBAT_EN BIT(0)
#define BQ25703_EN_OTG_MASK BIT(12)
struct bq257xx_device {
struct i2c_client *client;
struct regmap *regmap;
};
local/recipes/gpu/amdgpu-source/include/linux/mfd/cgbc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Congatec Board Controller driver definitions
*
* Copyright (C) 2024 Bootlin
* Author: Thomas Richard <thomas.richard@bootlin.com>
*/
#ifndef _LINUX_MFD_CGBC_H_
/**
* struct cgbc_version - Board Controller device version structure
* @feature: Board Controller feature number
* @major: Board Controller major revision
* @minor: Board Controller minor revision
*/
struct cgbc_version {
unsigned char feature;
unsigned char major;
unsigned char minor;
};
/**
* struct cgbc_device_data - Internal representation of the Board Controller device
* @io_session: Pointer to the session IO memory
* @io_cmd: Pointer to the command IO memory
* @session: Session id returned by the Board Controller
* @dev: Pointer to kernel device structure
* @version: Board Controller version structure
* @lock: Board Controller mutex
*/
struct cgbc_device_data {
void __iomem *io_session;
void __iomem *io_cmd;
u8 session;
struct device *dev;
struct cgbc_version version;
struct mutex lock;
};
int cgbc_command(struct cgbc_device_data *cgbc, void *cmd, unsigned int cmd_size,
void *data, unsigned int data_size, u8 *status);
#endif /*_LINUX_MFD_CGBC_H_*/
local/recipes/gpu/amdgpu-source/include/linux/mfd/core.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* drivers/mfd/mfd-core.h
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007 Dmitry Baryshkov
*/
#ifndef MFD_CORE_H
#define MFD_CORE_H
#include <linux/platform_device.h>
#define MFD_RES_SIZE(arr) (sizeof(arr) / sizeof(struct resource))
#define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \
{ \
.name = (_name), \
.resources = (_res), \
.num_resources = MFD_RES_SIZE((_res)), \
.platform_data = (_pdata), \
.pdata_size = (_pdsize), \
.of_compatible = (_compat), \
.of_reg = (_of_reg), \
.use_of_reg = (_use_of_reg), \
.acpi_match = (_match), \
.id = (_id), \
}
#define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
#define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
#define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
#define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, NULL)
#define MFD_CELL_RES(_name, _res) \
MFD_CELL_ALL(_name, _res, NULL, 0, 0, NULL, 0, false, NULL)
#define MFD_CELL_NAME(_name) \
MFD_CELL_ALL(_name, NULL, NULL, 0, 0, NULL, 0, false, NULL)
#define MFD_DEP_LEVEL_NORMAL 0
#define MFD_DEP_LEVEL_HIGH 1
struct irq_domain;
struct software_node;
/* Matches ACPI PNP id, either _HID or _CID, or ACPI _ADR */
struct mfd_cell_acpi_match {
const char *pnpid;
const unsigned long long adr;
};
/*
* This struct describes the MFD part ("cell").
* After registration the copy of this structure will become the platform data
* of the resulting platform_device
*/
struct mfd_cell {
const char *name;
int id;
int level;
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
/* platform data passed to the sub devices drivers */
const void *platform_data;
size_t pdata_size;
/* Matches ACPI */
const struct mfd_cell_acpi_match *acpi_match;
/* Software node for the device. */
const struct software_node *swnode;
/*
* Device Tree compatible string
* See: Documentation/devicetree/usage-model.rst Chapter 2.2 for details
*/
const char *of_compatible;
/*
* Address as defined in Device Tree. Used to complement 'of_compatible'
* (above) when matching OF nodes with devices that have identical
* compatible strings
*/
u64 of_reg;
/* Set to 'true' to use 'of_reg' (above) - allows for of_reg=0 */
bool use_of_reg;
/*
* These resources can be specified relative to the parent device.
* For accessing hardware you should use resources from the platform dev
*/
int num_resources;
const struct resource *resources;
/* don't check for resource conflicts */
bool ignore_resource_conflicts;
/*
* Disable runtime PM callbacks for this subdevice - see
* pm_runtime_no_callbacks().
*/
bool pm_runtime_no_callbacks;
/* A list of regulator supplies that should be mapped to the MFD
* device rather than the child device when requested
*/
int num_parent_supplies;
const char * const *parent_supplies;
};
/*
* Given a platform device that's been created by mfd_add_devices(), fetch
* the mfd_cell that created it.
*/
static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
{
return pdev->mfd_cell;
}
extern int mfd_add_devices(struct device *parent, int id,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *irq_domain);
static inline int mfd_add_hotplug_devices(struct device *parent,
const struct mfd_cell *cells, int n_devs)
{
return mfd_add_devices(parent, PLATFORM_DEVID_AUTO, cells, n_devs,
NULL, 0, NULL);
}
extern void mfd_remove_devices(struct device *parent);
extern void mfd_remove_devices_late(struct device *parent);
extern int devm_mfd_add_devices(struct device *dev, int id,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *irq_domain);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/cs40l50.h
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/* SPDX-License-Identifier: GPL-2.0
*
* CS40L50 Advanced Haptic Driver with waveform memory,
* integrated DSP, and closed-loop algorithms
*
* Copyright 2024 Cirrus Logic, Inc.
*
* Author: James Ogletree <james.ogletree@cirrus.com>
*/
#ifndef __MFD_CS40L50_H__
#define __MFD_CS40L50_H__
#include <linux/firmware/cirrus/cs_dsp.h>
#include <linux/gpio/consumer.h>
#include <linux/pm.h>
#include <linux/regmap.h>
/* Power Supply Configuration */
#define CS40L50_BLOCK_ENABLES2 0x201C
#define CS40L50_ERR_RLS 0x2034
#define CS40L50_BST_LPMODE_SEL 0x3810
#define CS40L50_DCM_LOW_POWER 0x1
#define CS40L50_OVERTEMP_WARN 0x4000010
/* Interrupts */
#define CS40L50_IRQ1_INT_1 0xE010
#define CS40L50_IRQ1_BASE CS40L50_IRQ1_INT_1
#define CS40L50_IRQ1_INT_2 0xE014
#define CS40L50_IRQ1_INT_8 0xE02C
#define CS40L50_IRQ1_INT_9 0xE030
#define CS40L50_IRQ1_INT_10 0xE034
#define CS40L50_IRQ1_INT_18 0xE054
#define CS40L50_IRQ1_MASK_1 0xE090
#define CS40L50_IRQ1_MASK_2 0xE094
#define CS40L50_IRQ1_MASK_20 0xE0DC
#define CS40L50_IRQ1_INT_1_OFFSET (CS40L50_IRQ1_INT_1 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_2_OFFSET (CS40L50_IRQ1_INT_2 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_8_OFFSET (CS40L50_IRQ1_INT_8 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_9_OFFSET (CS40L50_IRQ1_INT_9 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_10_OFFSET (CS40L50_IRQ1_INT_10 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_18_OFFSET (CS40L50_IRQ1_INT_18 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ_MASK_2_OVERRIDE 0xFFDF7FFF
#define CS40L50_IRQ_MASK_20_OVERRIDE 0x15C01000
#define CS40L50_AMP_SHORT_MASK BIT(31)
#define CS40L50_DSP_QUEUE_MASK BIT(21)
#define CS40L50_TEMP_ERR_MASK BIT(31)
#define CS40L50_BST_UVP_MASK BIT(6)
#define CS40L50_BST_SHORT_MASK BIT(7)
#define CS40L50_BST_ILIMIT_MASK BIT(18)
#define CS40L50_UVLO_VDDBATT_MASK BIT(16)
#define CS40L50_GLOBAL_ERROR_MASK BIT(15)
enum cs40l50_irq_list {
CS40L50_DSP_QUEUE_IRQ,
CS40L50_GLOBAL_ERROR_IRQ,
CS40L50_UVLO_VDDBATT_IRQ,
CS40L50_BST_ILIMIT_IRQ,
CS40L50_BST_SHORT_IRQ,
CS40L50_BST_UVP_IRQ,
CS40L50_TEMP_ERR_IRQ,
CS40L50_AMP_SHORT_IRQ,
};
/* DSP */
#define CS40L50_XMEM_PACKED_0 0x2000000
#define CS40L50_XMEM_UNPACKED24_0 0x2800000
#define CS40L50_SYS_INFO_ID 0x25E0000
#define CS40L50_DSP_QUEUE_WT 0x28042C8
#define CS40L50_DSP_QUEUE_RD 0x28042CC
#define CS40L50_NUM_WAVES 0x2805C18
#define CS40L50_CORE_BASE 0x2B80000
#define CS40L50_YMEM_PACKED_0 0x2C00000
#define CS40L50_YMEM_UNPACKED24_0 0x3400000
#define CS40L50_PMEM_0 0x3800000
#define CS40L50_DSP_POLL_US 1000
#define CS40L50_DSP_TIMEOUT_COUNT 100
#define CS40L50_RESET_PULSE_US 2200
#define CS40L50_CP_READY_US 3100
#define CS40L50_AUTOSUSPEND_MS 2000
#define CS40L50_PM_ALGO 0x9F206
#define CS40L50_GLOBAL_ERR_RLS_SET BIT(11)
#define CS40L50_GLOBAL_ERR_RLS_CLEAR 0
enum cs40l50_wseqs {
CS40L50_PWR_ON,
CS40L50_STANDBY,
CS40L50_ACTIVE,
CS40L50_NUM_WSEQS,
};
/* DSP Queue */
#define CS40L50_DSP_QUEUE_BASE 0x11004
#define CS40L50_DSP_QUEUE_END 0x1101C
#define CS40L50_DSP_QUEUE 0x11020
#define CS40L50_PREVENT_HIBER 0x2000003
#define CS40L50_ALLOW_HIBER 0x2000004
#define CS40L50_SHUTDOWN 0x2000005
#define CS40L50_SYSTEM_RESET 0x2000007
#define CS40L50_START_I2S 0x3000002
#define CS40L50_OWT_PUSH 0x3000008
#define CS40L50_STOP_PLAYBACK 0x5000000
#define CS40L50_OWT_DELETE 0xD000000
/* Firmware files */
#define CS40L50_FW "cs40l50.wmfw"
#define CS40L50_WT "cs40l50.bin"
/* Device */
#define CS40L50_DEVID 0x0
#define CS40L50_REVID 0x4
#define CS40L50_DEVID_A 0x40A50
#define CS40L50_REVID_B0 0xB0
struct cs40l50 {
struct device *dev;
struct regmap *regmap;
struct mutex lock;
struct cs_dsp dsp;
struct gpio_desc *reset_gpio;
struct regmap_irq_chip_data *irq_data;
const struct firmware *fw;
const struct firmware *bin;
struct cs_dsp_wseq wseqs[CS40L50_NUM_WSEQS];
int irq;
u32 devid;
u32 revid;
};
int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val);
int cs40l50_probe(struct cs40l50 *cs40l50);
int cs40l50_remove(struct cs40l50 *cs40l50);
extern const struct regmap_config cs40l50_regmap;
extern const struct dev_pm_ops cs40l50_pm_ops;
#endif /* __MFD_CS40L50_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/cs42l43-regs.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/cs42l43.h
+104
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* CS42L43 core driver external data
*
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#ifndef CS42L43_CORE_EXT_H
#define CS42L43_CORE_EXT_H
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/workqueue.h>
#define CS42L43_N_SUPPLIES 3
struct device;
struct gpio_desc;
struct sdw_slave;
enum cs42l43_irq_numbers {
CS42L43_PLL_LOST_LOCK,
CS42L43_PLL_READY,
CS42L43_HP_STARTUP_DONE,
CS42L43_HP_SHUTDOWN_DONE,
CS42L43_HSDET_DONE,
CS42L43_TIPSENSE_UNPLUG_DB,
CS42L43_TIPSENSE_PLUG_DB,
CS42L43_RINGSENSE_UNPLUG_DB,
CS42L43_RINGSENSE_PLUG_DB,
CS42L43_TIPSENSE_UNPLUG_PDET,
CS42L43_TIPSENSE_PLUG_PDET,
CS42L43_RINGSENSE_UNPLUG_PDET,
CS42L43_RINGSENSE_PLUG_PDET,
CS42L43_HS2_BIAS_SENSE,
CS42L43_HS1_BIAS_SENSE,
CS42L43_DC_DETECT1_FALSE,
CS42L43_DC_DETECT1_TRUE,
CS42L43_HSBIAS_CLAMPED,
CS42L43_HS3_4_BIAS_SENSE,
CS42L43_AMP2_CLK_STOP_FAULT,
CS42L43_AMP1_CLK_STOP_FAULT,
CS42L43_AMP2_VDDSPK_FAULT,
CS42L43_AMP1_VDDSPK_FAULT,
CS42L43_AMP2_SHUTDOWN_DONE,
CS42L43_AMP1_SHUTDOWN_DONE,
CS42L43_AMP2_STARTUP_DONE,
CS42L43_AMP1_STARTUP_DONE,
CS42L43_AMP2_THERM_SHDN,
CS42L43_AMP1_THERM_SHDN,
CS42L43_AMP2_THERM_WARN,
CS42L43_AMP1_THERM_WARN,
CS42L43_AMP2_SCDET,
CS42L43_AMP1_SCDET,
CS42L43_GPIO3_FALL,
CS42L43_GPIO3_RISE,
CS42L43_GPIO2_FALL,
CS42L43_GPIO2_RISE,
CS42L43_GPIO1_FALL,
CS42L43_GPIO1_RISE,
CS42L43_HP_ILIMIT,
CS42L43_HP_LOADDET_DONE,
};
struct cs42l43 {
struct device *dev;
struct regmap *regmap;
struct sdw_slave *sdw;
struct regulator *vdd_p;
struct regulator *vdd_d;
struct regulator_bulk_data core_supplies[CS42L43_N_SUPPLIES];
struct gpio_desc *reset;
int irq;
struct regmap_irq_chip irq_chip;
struct regmap_irq_chip_data *irq_data;
struct work_struct boot_work;
struct completion device_attach;
struct completion device_detach;
struct completion firmware_download;
int firmware_error;
unsigned int sdw_freq;
/* Lock to gate control of the PLL and its sources. */
struct mutex pll_lock;
bool sdw_pll_active;
bool attached;
bool hw_lock;
long variant_id;
};
#endif /* CS42L43_CORE_EXT_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da8xx-cfgchip.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
*
* Copyright (C) 2016 David Lechner <david@lechnology.com>
*/
#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
#define __LINUX_MFD_DA8XX_CFGCHIP_H
#include <linux/bitops.h>
/* register offset (32-bit registers) */
#define CFGCHIP(n) ((n) * 4)
/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
#define CFGCHIP1_HPIBYTEAD BIT(16)
#define CFGCHIP1_HPIENA BIT(15)
#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
#define CFGCHIP1_TBCLKSYNC BIT(12)
#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
/* CFGCHIP2 (USB PHY) register bits */
#define CFGCHIP2_PHYCLKGD BIT(17)
#define CFGCHIP2_VBUSSENSE BIT(16)
#define CFGCHIP2_RESET BIT(15)
#define CFGCHIP2_OTGMODE(n) ((n) << 13)
#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
#define CFGCHIP2_PHYPWRDN BIT(10)
#define CFGCHIP2_OTGPWRDN BIT(9)
#define CFGCHIP2_DATPOL BIT(8)
#define CFGCHIP2_USB1SUSPENDM BIT(7)
#define CFGCHIP2_PHY_PLLON BIT(6)
#define CFGCHIP2_SESENDEN BIT(5)
#define CFGCHIP2_VBDTCTEN BIT(4)
#define CFGCHIP2_REFFREQ(n) ((n) << 0)
#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
#define CFGCHIP3_RMII_SEL BIT(8)
#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
#define CFGCHIP3_PRUEVTSEL BIT(3)
#define CFGCHIP3_DIV45PENA BIT(2)
#define CFGCHIP3_EMA_CLKSRC BIT(1)
/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
#define CFGCHIP4_AMUTECLR0 BIT(0)
#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da903x.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_PMIC_DA903X_H
#define __LINUX_PMIC_DA903X_H
/* Unified sub device IDs for DA9030/DA9034/DA9035 */
enum {
DA9030_ID_LED_1,
DA9030_ID_LED_2,
DA9030_ID_LED_3,
DA9030_ID_LED_4,
DA9030_ID_LED_PC,
DA9030_ID_VIBRA,
DA9030_ID_WLED,
DA9030_ID_BUCK1,
DA9030_ID_BUCK2,
DA9030_ID_LDO1,
DA9030_ID_LDO2,
DA9030_ID_LDO3,
DA9030_ID_LDO4,
DA9030_ID_LDO5,
DA9030_ID_LDO6,
DA9030_ID_LDO7,
DA9030_ID_LDO8,
DA9030_ID_LDO9,
DA9030_ID_LDO10,
DA9030_ID_LDO11,
DA9030_ID_LDO12,
DA9030_ID_LDO13,
DA9030_ID_LDO14,
DA9030_ID_LDO15,
DA9030_ID_LDO16,
DA9030_ID_LDO17,
DA9030_ID_LDO18,
DA9030_ID_LDO19,
DA9030_ID_LDO_INT, /* LDO Internal */
DA9030_ID_BAT, /* battery charger */
DA9034_ID_LED_1,
DA9034_ID_LED_2,
DA9034_ID_VIBRA,
DA9034_ID_WLED,
DA9034_ID_TOUCH,
DA9034_ID_BUCK1,
DA9034_ID_BUCK2,
DA9034_ID_LDO1,
DA9034_ID_LDO2,
DA9034_ID_LDO3,
DA9034_ID_LDO4,
DA9034_ID_LDO5,
DA9034_ID_LDO6,
DA9034_ID_LDO7,
DA9034_ID_LDO8,
DA9034_ID_LDO9,
DA9034_ID_LDO10,
DA9034_ID_LDO11,
DA9034_ID_LDO12,
DA9034_ID_LDO13,
DA9034_ID_LDO14,
DA9034_ID_LDO15,
DA9035_ID_BUCK3,
};
/*
* DA9030/DA9034 LEDs sub-devices uses generic "struct led_info"
* as the platform_data
*/
/* DA9030 flags for "struct led_info"
*/
#define DA9030_LED_RATE_ON (0 << 5)
#define DA9030_LED_RATE_052S (1 << 5)
#define DA9030_LED_DUTY_1_16 (0 << 3)
#define DA9030_LED_DUTY_1_8 (1 << 3)
#define DA9030_LED_DUTY_1_4 (2 << 3)
#define DA9030_LED_DUTY_1_2 (3 << 3)
#define DA9030_VIBRA_MODE_1P3V (0 << 1)
#define DA9030_VIBRA_MODE_2P7V (1 << 1)
#define DA9030_VIBRA_FREQ_1HZ (0 << 2)
#define DA9030_VIBRA_FREQ_2HZ (1 << 2)
#define DA9030_VIBRA_FREQ_4HZ (2 << 2)
#define DA9030_VIBRA_FREQ_8HZ (3 << 2)
#define DA9030_VIBRA_DUTY_ON (0 << 4)
#define DA9030_VIBRA_DUTY_75P (1 << 4)
#define DA9030_VIBRA_DUTY_50P (2 << 4)
#define DA9030_VIBRA_DUTY_25P (3 << 4)
/* DA9034 flags for "struct led_info" */
#define DA9034_LED_RAMP (1 << 7)
/* DA9034 touch screen platform data */
struct da9034_touch_pdata {
int interval_ms; /* sampling interval while pen down */
int x_inverted;
int y_inverted;
};
struct da9034_backlight_pdata {
int output_current; /* output current of WLED, from 0-31 (in mA) */
};
/* DA9030 battery charger data */
struct power_supply_info;
struct da9030_battery_info {
/* battery parameters */
struct power_supply_info *battery_info;
/* current and voltage to use for battery charging */
unsigned int charge_milliamp;
unsigned int charge_millivolt;
/* voltage thresholds (in millivolts) */
int vbat_low;
int vbat_crit;
int vbat_charge_start;
int vbat_charge_stop;
int vbat_charge_restart;
/* battery nominal minimal and maximal voltages in millivolts */
int vcharge_min;
int vcharge_max;
/* Temperature thresholds. These are DA9030 register values
"as is" and should be measured for each battery type */
int tbat_low;
int tbat_high;
int tbat_restart;
/* battery monitor interval (seconds) */
unsigned int batmon_interval;
/* platform callbacks for battery low and critical events */
void (*battery_low)(void);
void (*battery_critical)(void);
};
struct da903x_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct da903x_platform_data {
int num_subdevs;
struct da903x_subdev_info *subdevs;
};
/* bit definitions for DA9030 events */
#define DA9030_EVENT_ONKEY (1 << 0)
#define DA9030_EVENT_PWREN (1 << 1)
#define DA9030_EVENT_EXTON (1 << 2)
#define DA9030_EVENT_CHDET (1 << 3)
#define DA9030_EVENT_TBAT (1 << 4)
#define DA9030_EVENT_VBATMON (1 << 5)
#define DA9030_EVENT_VBATMON_TXON (1 << 6)
#define DA9030_EVENT_CHIOVER (1 << 7)
#define DA9030_EVENT_TCTO (1 << 8)
#define DA9030_EVENT_CCTO (1 << 9)
#define DA9030_EVENT_ADC_READY (1 << 10)
#define DA9030_EVENT_VBUS_4P4 (1 << 11)
#define DA9030_EVENT_VBUS_4P0 (1 << 12)
#define DA9030_EVENT_SESS_VALID (1 << 13)
#define DA9030_EVENT_SRP_DETECT (1 << 14)
#define DA9030_EVENT_WATCHDOG (1 << 15)
#define DA9030_EVENT_LDO15 (1 << 16)
#define DA9030_EVENT_LDO16 (1 << 17)
#define DA9030_EVENT_LDO17 (1 << 18)
#define DA9030_EVENT_LDO18 (1 << 19)
#define DA9030_EVENT_LDO19 (1 << 20)
#define DA9030_EVENT_BUCK2 (1 << 21)
/* bit definitions for DA9034 events */
#define DA9034_EVENT_ONKEY (1 << 0)
#define DA9034_EVENT_EXTON (1 << 2)
#define DA9034_EVENT_CHDET (1 << 3)
#define DA9034_EVENT_TBAT (1 << 4)
#define DA9034_EVENT_VBATMON (1 << 5)
#define DA9034_EVENT_REV_IOVER (1 << 6)
#define DA9034_EVENT_CH_IOVER (1 << 7)
#define DA9034_EVENT_CH_TCTO (1 << 8)
#define DA9034_EVENT_CH_CCTO (1 << 9)
#define DA9034_EVENT_USB_DEV (1 << 10)
#define DA9034_EVENT_OTGCP_IOVER (1 << 11)
#define DA9034_EVENT_VBUS_4P55 (1 << 12)
#define DA9034_EVENT_VBUS_3P8 (1 << 13)
#define DA9034_EVENT_SESS_1P8 (1 << 14)
#define DA9034_EVENT_SRP_READY (1 << 15)
#define DA9034_EVENT_ADC_MAN (1 << 16)
#define DA9034_EVENT_ADC_AUTO4 (1 << 17)
#define DA9034_EVENT_ADC_AUTO5 (1 << 18)
#define DA9034_EVENT_ADC_AUTO6 (1 << 19)
#define DA9034_EVENT_PEN_DOWN (1 << 20)
#define DA9034_EVENT_TSI_READY (1 << 21)
#define DA9034_EVENT_UART_TX (1 << 22)
#define DA9034_EVENT_UART_RX (1 << 23)
#define DA9034_EVENT_HEADSET (1 << 25)
#define DA9034_EVENT_HOOKSWITCH (1 << 26)
#define DA9034_EVENT_WATCHDOG (1 << 27)
extern int da903x_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int da903x_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
/* Status Query Interface */
#define DA9030_STATUS_ONKEY (1 << 0)
#define DA9030_STATUS_PWREN1 (1 << 1)
#define DA9030_STATUS_EXTON (1 << 2)
#define DA9030_STATUS_CHDET (1 << 3)
#define DA9030_STATUS_TBAT (1 << 4)
#define DA9030_STATUS_VBATMON (1 << 5)
#define DA9030_STATUS_VBATMON_TXON (1 << 6)
#define DA9030_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_ONKEY (1 << 0)
#define DA9034_STATUS_EXTON (1 << 2)
#define DA9034_STATUS_CHDET (1 << 3)
#define DA9034_STATUS_TBAT (1 << 4)
#define DA9034_STATUS_VBATMON (1 << 5)
#define DA9034_STATUS_PEN_DOWN (1 << 6)
#define DA9034_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_USB_DEV (1 << 8)
#define DA9034_STATUS_HEADSET (1 << 9)
#define DA9034_STATUS_HOOKSWITCH (1 << 10)
#define DA9034_STATUS_REMCON (1 << 11)
#define DA9034_STATUS_VBUS_VALID_4P55 (1 << 12)
#define DA9034_STATUS_VBUS_VALID_3P8 (1 << 13)
#define DA9034_STATUS_SESS_VALID_1P8 (1 << 14)
#define DA9034_STATUS_SRP_READY (1 << 15)
extern int da903x_query_status(struct device *dev, unsigned int status);
/* NOTE: the functions below are not intended for use outside
* of the DA903x sub-device drivers
*/
extern int da903x_write(struct device *dev, int reg, uint8_t val);
extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_read(struct device *dev, int reg, uint8_t *val);
extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
#endif /* __LINUX_PMIC_DA903X_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9052/da9052.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* da9052 declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*/
#ifndef __MFD_DA9052_DA9052_H
#define __MFD_DA9052_DA9052_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/list.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9052/reg.h>
/* Common - HWMON Channel Definations */
#define DA9052_ADC_VDDOUT 0
#define DA9052_ADC_ICH 1
#define DA9052_ADC_TBAT 2
#define DA9052_ADC_VBAT 3
#define DA9052_ADC_IN4 4
#define DA9052_ADC_IN5 5
#define DA9052_ADC_IN6 6
#define DA9052_ADC_TSI 7
#define DA9052_ADC_TJUNC 8
#define DA9052_ADC_VBBAT 9
/* TSI channel has its own 4 channel mux */
#define DA9052_ADC_TSI_XP 70
#define DA9052_ADC_TSI_XN 71
#define DA9052_ADC_TSI_YP 72
#define DA9052_ADC_TSI_YN 73
#define DA9052_IRQ_DCIN 0
#define DA9052_IRQ_VBUS 1
#define DA9052_IRQ_DCINREM 2
#define DA9052_IRQ_VBUSREM 3
#define DA9052_IRQ_VDDLOW 4
#define DA9052_IRQ_ALARM 5
#define DA9052_IRQ_SEQRDY 6
#define DA9052_IRQ_COMP1V2 7
#define DA9052_IRQ_NONKEY 8
#define DA9052_IRQ_IDFLOAT 9
#define DA9052_IRQ_IDGND 10
#define DA9052_IRQ_CHGEND 11
#define DA9052_IRQ_TBAT 12
#define DA9052_IRQ_ADC_EOM 13
#define DA9052_IRQ_PENDOWN 14
#define DA9052_IRQ_TSIREADY 15
#define DA9052_IRQ_GPI0 16
#define DA9052_IRQ_GPI1 17
#define DA9052_IRQ_GPI2 18
#define DA9052_IRQ_GPI3 19
#define DA9052_IRQ_GPI4 20
#define DA9052_IRQ_GPI5 21
#define DA9052_IRQ_GPI6 22
#define DA9052_IRQ_GPI7 23
#define DA9052_IRQ_GPI8 24
#define DA9052_IRQ_GPI9 25
#define DA9052_IRQ_GPI10 26
#define DA9052_IRQ_GPI11 27
#define DA9052_IRQ_GPI12 28
#define DA9052_IRQ_GPI13 29
#define DA9052_IRQ_GPI14 30
#define DA9052_IRQ_GPI15 31
enum da9052_chip_id {
DA9052,
DA9053_AA,
DA9053_BA,
DA9053_BB,
DA9053_BC,
};
struct da9052_pdata;
struct da9052 {
struct device *dev;
struct regmap *regmap;
struct mutex auxadc_lock;
struct completion done;
int irq_base;
struct regmap_irq_chip_data *irq_data;
u8 chip_id;
int chip_irq;
int fault_log;
/* SOC I/O transfer related fixes for DA9052/53 */
int (*fix_io) (struct da9052 *da9052, unsigned char reg);
};
/* ADC API */
int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
int da9052_adc_read_temp(struct da9052 *da9052);
/* Device I/O API */
static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9052->regmap, reg, &val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return val;
}
static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
unsigned char val)
{
int ret;
ret = regmap_write(da9052->regmap, reg, val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret;
unsigned int tmp;
int i;
for (i = 0; i < reg_cnt; i++) {
ret = regmap_read(da9052->regmap, reg + i, &tmp);
val[i] = (unsigned char)tmp;
if (ret < 0)
return ret;
}
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret = 0;
int i;
for (i = 0; i < reg_cnt; i++) {
ret = regmap_write(da9052->regmap, reg + i, val[i]);
if (ret < 0)
return ret;
}
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
int ret;
ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
int da9052_device_init(struct da9052 *da9052, u8 chip_id);
void da9052_device_exit(struct da9052 *da9052);
extern const struct regmap_config da9052_regmap_config;
int da9052_irq_init(struct da9052 *da9052);
int da9052_irq_exit(struct da9052 *da9052);
int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
irq_handler_t handler, void *data);
void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
int da9052_enable_irq(struct da9052 *da9052, int irq);
int da9052_disable_irq(struct da9052 *da9052, int irq);
int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
#endif /* __MFD_DA9052_DA9052_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9052/pdata.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Platform data declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*/
#ifndef __MFD_DA9052_PDATA_H__
#define __MFD_DA9052_PDATA_H__
#define DA9052_MAX_REGULATORS 14
struct da9052;
struct da9052_pdata {
struct led_platform_data *pled;
int (*init) (struct da9052 *da9052);
int irq_base;
int gpio_base;
int use_for_apm;
struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9052/reg.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Register declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*/
#ifndef __LINUX_MFD_DA9052_REG_H
#define __LINUX_MFD_DA9052_REG_H
/* PAGE REGISTERS */
#define DA9052_PAGE0_CON_REG 0
#define DA9052_PAGE1_CON_REG 128
/* STATUS REGISTERS */
#define DA9052_STATUS_A_REG 1
#define DA9052_STATUS_B_REG 2
#define DA9052_STATUS_C_REG 3
#define DA9052_STATUS_D_REG 4
/* PARK REGISTER */
#define DA9052_PARK_REGISTER DA9052_STATUS_D_REG
/* EVENT REGISTERS */
#define DA9052_EVENT_A_REG 5
#define DA9052_EVENT_B_REG 6
#define DA9052_EVENT_C_REG 7
#define DA9052_EVENT_D_REG 8
#define DA9052_FAULTLOG_REG 9
/* IRQ REGISTERS */
#define DA9052_IRQ_MASK_A_REG 10
#define DA9052_IRQ_MASK_B_REG 11
#define DA9052_IRQ_MASK_C_REG 12
#define DA9052_IRQ_MASK_D_REG 13
/* CONTROL REGISTERS */
#define DA9052_CONTROL_A_REG 14
#define DA9052_CONTROL_B_REG 15
#define DA9052_CONTROL_C_REG 16
#define DA9052_CONTROL_D_REG 17
#define DA9052_PDDIS_REG 18
#define DA9052_INTERFACE_REG 19
#define DA9052_RESET_REG 20
/* GPIO REGISTERS */
#define DA9052_GPIO_0_1_REG 21
#define DA9052_GPIO_2_3_REG 22
#define DA9052_GPIO_4_5_REG 23
#define DA9052_GPIO_6_7_REG 24
#define DA9052_GPIO_8_9_REG 25
#define DA9052_GPIO_10_11_REG 26
#define DA9052_GPIO_12_13_REG 27
#define DA9052_GPIO_14_15_REG 28
/* POWER SEQUENCER CONTROL REGISTERS */
#define DA9052_ID_0_1_REG 29
#define DA9052_ID_2_3_REG 30
#define DA9052_ID_4_5_REG 31
#define DA9052_ID_6_7_REG 32
#define DA9052_ID_8_9_REG 33
#define DA9052_ID_10_11_REG 34
#define DA9052_ID_12_13_REG 35
#define DA9052_ID_14_15_REG 36
#define DA9052_ID_16_17_REG 37
#define DA9052_ID_18_19_REG 38
#define DA9052_ID_20_21_REG 39
#define DA9052_SEQ_STATUS_REG 40
#define DA9052_SEQ_A_REG 41
#define DA9052_SEQ_B_REG 42
#define DA9052_SEQ_TIMER_REG 43
/* LDO AND BUCK REGISTERS */
#define DA9052_BUCKA_REG 44
#define DA9052_BUCKB_REG 45
#define DA9052_BUCKCORE_REG 46
#define DA9052_BUCKPRO_REG 47
#define DA9052_BUCKMEM_REG 48
#define DA9052_BUCKPERI_REG 49
#define DA9052_LDO1_REG 50
#define DA9052_LDO2_REG 51
#define DA9052_LDO3_REG 52
#define DA9052_LDO4_REG 53
#define DA9052_LDO5_REG 54
#define DA9052_LDO6_REG 55
#define DA9052_LDO7_REG 56
#define DA9052_LDO8_REG 57
#define DA9052_LDO9_REG 58
#define DA9052_LDO10_REG 59
#define DA9052_SUPPLY_REG 60
#define DA9052_PULLDOWN_REG 61
#define DA9052_CHGBUCK_REG 62
#define DA9052_WAITCONT_REG 63
#define DA9052_ISET_REG 64
#define DA9052_BATCHG_REG 65
/* BATTERY CONTROL REGISTRS */
#define DA9052_CHG_CONT_REG 66
#define DA9052_INPUT_CONT_REG 67
#define DA9052_CHG_TIME_REG 68
#define DA9052_BBAT_CONT_REG 69
/* LED CONTROL REGISTERS */
#define DA9052_BOOST_REG 70
#define DA9052_LED_CONT_REG 71
#define DA9052_LEDMIN123_REG 72
#define DA9052_LED1_CONF_REG 73
#define DA9052_LED2_CONF_REG 74
#define DA9052_LED3_CONF_REG 75
#define DA9052_LED1CONT_REG 76
#define DA9052_LED2CONT_REG 77
#define DA9052_LED3CONT_REG 78
#define DA9052_LED_CONT_4_REG 79
#define DA9052_LED_CONT_5_REG 80
/* ADC CONTROL REGISTERS */
#define DA9052_ADC_MAN_REG 81
#define DA9052_ADC_CONT_REG 82
#define DA9052_ADC_RES_L_REG 83
#define DA9052_ADC_RES_H_REG 84
#define DA9052_VDD_RES_REG 85
#define DA9052_VDD_MON_REG 86
#define DA9052_ICHG_AV_REG 87
#define DA9052_ICHG_THD_REG 88
#define DA9052_ICHG_END_REG 89
#define DA9052_TBAT_RES_REG 90
#define DA9052_TBAT_HIGHP_REG 91
#define DA9052_TBAT_HIGHN_REG 92
#define DA9052_TBAT_LOW_REG 93
#define DA9052_T_OFFSET_REG 94
#define DA9052_ADCIN4_RES_REG 95
#define DA9052_AUTO4_HIGH_REG 96
#define DA9052_AUTO4_LOW_REG 97
#define DA9052_ADCIN5_RES_REG 98
#define DA9052_AUTO5_HIGH_REG 99
#define DA9052_AUTO5_LOW_REG 100
#define DA9052_ADCIN6_RES_REG 101
#define DA9052_AUTO6_HIGH_REG 102
#define DA9052_AUTO6_LOW_REG 103
#define DA9052_TJUNC_RES_REG 104
/* TSI CONTROL REGISTERS */
#define DA9052_TSI_CONT_A_REG 105
#define DA9052_TSI_CONT_B_REG 106
#define DA9052_TSI_X_MSB_REG 107
#define DA9052_TSI_Y_MSB_REG 108
#define DA9052_TSI_LSB_REG 109
#define DA9052_TSI_Z_MSB_REG 110
/* RTC COUNT REGISTERS */
#define DA9052_COUNT_S_REG 111
#define DA9052_COUNT_MI_REG 112
#define DA9052_COUNT_H_REG 113
#define DA9052_COUNT_D_REG 114
#define DA9052_COUNT_MO_REG 115
#define DA9052_COUNT_Y_REG 116
/* RTC CONTROL REGISTERS */
#define DA9052_ALARM_MI_REG 117
#define DA9052_ALARM_H_REG 118
#define DA9052_ALARM_D_REG 119
#define DA9052_ALARM_MO_REG 120
#define DA9052_ALARM_Y_REG 121
#define DA9052_SECOND_A_REG 122
#define DA9052_SECOND_B_REG 123
#define DA9052_SECOND_C_REG 124
#define DA9052_SECOND_D_REG 125
/* PAGE CONFIGURATION BIT */
#define DA9052_PAGE_CONF 0X80
/* STATUS REGISTER A BITS */
#define DA9052_STATUSA_VDATDET 0X80
#define DA9052_STATUSA_VBUSSEL 0X40
#define DA9052_STATUSA_DCINSEL 0X20
#define DA9052_STATUSA_VBUSDET 0X10
#define DA9052_STATUSA_DCINDET 0X08
#define DA9052_STATUSA_IDGND 0X04
#define DA9052_STATUSA_IDFLOAT 0X02
#define DA9052_STATUSA_NONKEY 0X01
/* STATUS REGISTER B BITS */
#define DA9052_STATUSB_COMPDET 0X80
#define DA9052_STATUSB_SEQUENCING 0X40
#define DA9052_STATUSB_GPFB2 0X20
#define DA9052_STATUSB_CHGTO 0X10
#define DA9052_STATUSB_CHGEND 0X08
#define DA9052_STATUSB_CHGLIM 0X04
#define DA9052_STATUSB_CHGPRE 0X02
#define DA9052_STATUSB_CHGATT 0X01
/* STATUS REGISTER C BITS */
#define DA9052_STATUSC_GPI7 0X80
#define DA9052_STATUSC_GPI6 0X40
#define DA9052_STATUSC_GPI5 0X20
#define DA9052_STATUSC_GPI4 0X10
#define DA9052_STATUSC_GPI3 0X08
#define DA9052_STATUSC_GPI2 0X04
#define DA9052_STATUSC_GPI1 0X02
#define DA9052_STATUSC_GPI0 0X01
/* STATUS REGISTER D BITS */
#define DA9052_STATUSD_GPI15 0X80
#define DA9052_STATUSD_GPI14 0X40
#define DA9052_STATUSD_GPI13 0X20
#define DA9052_STATUSD_GPI12 0X10
#define DA9052_STATUSD_GPI11 0X08
#define DA9052_STATUSD_GPI10 0X04
#define DA9052_STATUSD_GPI9 0X02
#define DA9052_STATUSD_GPI8 0X01
/* EVENT REGISTER A BITS */
#define DA9052_EVENTA_ECOMP1V2 0X80
#define DA9052_EVENTA_ESEQRDY 0X40
#define DA9052_EVENTA_EALRAM 0X20
#define DA9052_EVENTA_EVDDLOW 0X10
#define DA9052_EVENTA_EVBUSREM 0X08
#define DA9052_EVENTA_EDCINREM 0X04
#define DA9052_EVENTA_EVBUSDET 0X02
#define DA9052_EVENTA_EDCINDET 0X01
/* EVENT REGISTER B BITS */
#define DA9052_EVENTB_ETSIREADY 0X80
#define DA9052_EVENTB_EPENDOWN 0X40
#define DA9052_EVENTB_EADCEOM 0X20
#define DA9052_EVENTB_ETBAT 0X10
#define DA9052_EVENTB_ECHGEND 0X08
#define DA9052_EVENTB_EIDGND 0X04
#define DA9052_EVENTB_EIDFLOAT 0X02
#define DA9052_EVENTB_ENONKEY 0X01
/* EVENT REGISTER C BITS */
#define DA9052_EVENTC_EGPI7 0X80
#define DA9052_EVENTC_EGPI6 0X40
#define DA9052_EVENTC_EGPI5 0X20
#define DA9052_EVENTC_EGPI4 0X10
#define DA9052_EVENTC_EGPI3 0X08
#define DA9052_EVENTC_EGPI2 0X04
#define DA9052_EVENTC_EGPI1 0X02
#define DA9052_EVENTC_EGPI0 0X01
/* EVENT REGISTER D BITS */
#define DA9052_EVENTD_EGPI15 0X80
#define DA9052_EVENTD_EGPI14 0X40
#define DA9052_EVENTD_EGPI13 0X20
#define DA9052_EVENTD_EGPI12 0X10
#define DA9052_EVENTD_EGPI11 0X08
#define DA9052_EVENTD_EGPI10 0X04
#define DA9052_EVENTD_EGPI9 0X02
#define DA9052_EVENTD_EGPI8 0X01
/* IRQ MASK REGISTERS BITS */
#define DA9052_M_NONKEY 0X0100
/* TSI EVENT REGISTERS BITS */
#define DA9052_E_PEN_DOWN 0X4000
#define DA9052_E_TSI_READY 0X8000
/* FAULT LOG REGISTER BITS */
#define DA9052_FAULTLOG_WAITSET 0X80
#define DA9052_FAULTLOG_NSDSET 0X40
#define DA9052_FAULTLOG_KEYSHUT 0X20
#define DA9052_FAULTLOG_TEMPOVER 0X08
#define DA9052_FAULTLOG_VDDSTART 0X04
#define DA9052_FAULTLOG_VDDFAULT 0X02
#define DA9052_FAULTLOG_TWDERROR 0X01
/* CONTROL REGISTER A BITS */
#define DA9052_CONTROLA_GPIV 0X80
#define DA9052_CONTROLA_PMOTYPE 0X20
#define DA9052_CONTROLA_PMOV 0X10
#define DA9052_CONTROLA_PMIV 0X08
#define DA9052_CONTROLA_PMIFV 0X08
#define DA9052_CONTROLA_PWR1EN 0X04
#define DA9052_CONTROLA_PWREN 0X02
#define DA9052_CONTROLA_SYSEN 0X01
/* CONTROL REGISTER B BITS */
#define DA9052_CONTROLB_SHUTDOWN 0X80
#define DA9052_CONTROLB_DEEPSLEEP 0X40
#define DA9052_CONTROL_B_WRITEMODE 0X20
#define DA9052_CONTROLB_BBATEN 0X10
#define DA9052_CONTROLB_OTPREADEN 0X08
#define DA9052_CONTROLB_AUTOBOOT 0X04
#define DA9052_CONTROLB_ACTDIODE 0X02
#define DA9052_CONTROLB_BUCKMERGE 0X01
/* CONTROL REGISTER C BITS */
#define DA9052_CONTROLC_BLINKDUR 0X80
#define DA9052_CONTROLC_BLINKFRQ 0X60
#define DA9052_CONTROLC_DEBOUNCING 0X1C
#define DA9052_CONTROLC_PMFB2PIN 0X02
#define DA9052_CONTROLC_PMFB1PIN 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_CONTROLD_WATCHDOG 0X80
#define DA9052_CONTROLD_ACCDETEN 0X40
#define DA9052_CONTROLD_GPI1415SD 0X20
#define DA9052_CONTROLD_NONKEYSD 0X10
#define DA9052_CONTROLD_KEEPACTEN 0X08
#define DA9052_CONTROLD_TWDSCALE 0X07
/* POWER DOWN DISABLE REGISTER BITS */
#define DA9052_PDDIS_PMCONTPD 0X80
#define DA9052_PDDIS_OUT32KPD 0X40
#define DA9052_PDDIS_CHGBBATPD 0X20
#define DA9052_PDDIS_CHGPD 0X10
#define DA9052_PDDIS_HS2WIREPD 0X08
#define DA9052_PDDIS_PMIFPD 0X04
#define DA9052_PDDIS_GPADCPD 0X02
#define DA9052_PDDIS_GPIOPD 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_INTERFACE_IFBASEADDR 0XE0
#define DA9052_INTERFACE_NCSPOL 0X10
#define DA9052_INTERFACE_RWPOL 0X08
#define DA9052_INTERFACE_CPHA 0X04
#define DA9052_INTERFACE_CPOL 0X02
#define DA9052_INTERFACE_IFTYPE 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_RESET_RESETEVENT 0XC0
#define DA9052_RESET_RESETTIMER 0X3F
/* GPIO REGISTERS */
/* GPIO CONTROL REGISTER BITS */
#define DA9052_GPIO_EVEN_PORT_PIN 0X03
#define DA9052_GPIO_EVEN_PORT_TYPE 0X04
#define DA9052_GPIO_EVEN_PORT_MODE 0X08
#define DA9052_GPIO_ODD_PORT_PIN 0X30
#define DA9052_GPIO_ODD_PORT_TYPE 0X40
#define DA9052_GPIO_ODD_PORT_MODE 0X80
/*POWER SEQUENCER REGISTER BITS */
/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
#define DA9052_ID01_LDO1STEP 0XF0
#define DA9052_ID01_SYSPRE 0X04
#define DA9052_ID01_DEFSUPPLY 0X02
#define DA9052_ID01_NRESMODE 0X01
/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
#define DA9052_ID23_LDO3STEP 0XF0
#define DA9052_ID23_LDO2STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
#define DA9052_ID45_LDO5STEP 0XF0
#define DA9052_ID45_LDO4STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
#define DA9052_ID67_LDO7STEP 0XF0
#define DA9052_ID67_LDO6STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
#define DA9052_ID89_LDO9STEP 0XF0
#define DA9052_ID89_LDO8STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
#define DA9052_ID1011_PDDISSTEP 0XF0
#define DA9052_ID1011_LDO10STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
#define DA9052_ID1213_VMEMSWSTEP 0XF0
#define DA9052_ID1213_VPERISWSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
#define DA9052_ID1415_BUCKPROSTEP 0XF0
#define DA9052_ID1415_BUCKCORESTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
#define DA9052_ID1617_BUCKPERISTEP 0XF0
#define DA9052_ID1617_BUCKMEMSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
#define DA9052_ID1819_GPRISE2STEP 0XF0
#define DA9052_ID1819_GPRISE1STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
#define DA9052_ID2021_GPFALL2STEP 0XF0
#define DA9052_ID2021_GPFALL1STEP 0X0F
/* POWER SEQ STATUS REGISTER BITS */
#define DA9052_SEQSTATUS_SEQPOINTER 0XF0
#define DA9052_SEQSTATUS_WAITSTEP 0X0F
/* POWER SEQ A REGISTER BITS */
#define DA9052_SEQA_POWEREND 0XF0
#define DA9052_SEQA_SYSTEMEND 0X0F
/* POWER SEQ B REGISTER BITS */
#define DA9052_SEQB_PARTDOWN 0XF0
#define DA9052_SEQB_MAXCOUNT 0X0F
/* POWER SEQ TIMER REGISTER BITS */
#define DA9052_SEQTIMER_SEQDUMMY 0XF0
#define DA9052_SEQTIMER_SEQTIME 0X0F
/*POWER SUPPLY CONTROL REGISTER BITS */
/* BUCK REGISTER A BITS */
#define DA9052_BUCKA_BPROILIM 0XC0
#define DA9052_BUCKA_BPROMODE 0X30
#define DA9052_BUCKA_BCOREILIM 0X0C
#define DA9052_BUCKA_BCOREMODE 0X03
/* BUCK REGISTER B BITS */
#define DA9052_BUCKB_BERIILIM 0XC0
#define DA9052_BUCKB_BPERIMODE 0X30
#define DA9052_BUCKB_BMEMILIM 0X0C
#define DA9052_BUCKB_BMEMMODE 0X03
/* BUCKCORE REGISTER BITS */
#define DA9052_BUCKCORE_BCORECONF 0X80
#define DA9052_BUCKCORE_BCOREEN 0X40
#define DA9052_BUCKCORE_VBCORE 0X3F
/* BUCKPRO REGISTER BITS */
#define DA9052_BUCKPRO_BPROCONF 0X80
#define DA9052_BUCKPRO_BPROEN 0X40
#define DA9052_BUCKPRO_VBPRO 0X3F
/* BUCKMEM REGISTER BITS */
#define DA9052_BUCKMEM_BMEMCONF 0X80
#define DA9052_BUCKMEM_BMEMEN 0X40
#define DA9052_BUCKMEM_VBMEM 0X3F
/* BUCKPERI REGISTER BITS */
#define DA9052_BUCKPERI_BPERICONF 0X80
#define DA9052_BUCKPERI_BPERIEN 0X40
#define DA9052_BUCKPERI_BPERIHS 0X20
#define DA9052_BUCKPERI_VBPERI 0X1F
/* LDO1 REGISTER BITS */
#define DA9052_LDO1_LDO1CONF 0X80
#define DA9052_LDO1_LDO1EN 0X40
#define DA9052_LDO1_VLDO1 0X1F
/* LDO2 REGISTER BITS */
#define DA9052_LDO2_LDO2CONF 0X80
#define DA9052_LDO2_LDO2EN 0X40
#define DA9052_LDO2_VLDO2 0X3F
/* LDO3 REGISTER BITS */
#define DA9052_LDO3_LDO3CONF 0X80
#define DA9052_LDO3_LDO3EN 0X40
#define DA9052_LDO3_VLDO3 0X3F
/* LDO4 REGISTER BITS */
#define DA9052_LDO4_LDO4CONF 0X80
#define DA9052_LDO4_LDO4EN 0X40
#define DA9052_LDO4_VLDO4 0X3F
/* LDO5 REGISTER BITS */
#define DA9052_LDO5_LDO5CONF 0X80
#define DA9052_LDO5_LDO5EN 0X40
#define DA9052_LDO5_VLDO5 0X3F
/* LDO6 REGISTER BITS */
#define DA9052_LDO6_LDO6CONF 0X80
#define DA9052_LDO6_LDO6EN 0X40
#define DA9052_LDO6_VLDO6 0X3F
/* LDO7 REGISTER BITS */
#define DA9052_LDO7_LDO7CONF 0X80
#define DA9052_LDO7_LDO7EN 0X40
#define DA9052_LDO7_VLDO7 0X3F
/* LDO8 REGISTER BITS */
#define DA9052_LDO8_LDO8CONF 0X80
#define DA9052_LDO8_LDO8EN 0X40
#define DA9052_LDO8_VLDO8 0X3F
/* LDO9 REGISTER BITS */
#define DA9052_LDO9_LDO9CONF 0X80
#define DA9052_LDO9_LDO9EN 0X40
#define DA9052_LDO9_VLDO9 0X3F
/* LDO10 REGISTER BITS */
#define DA9052_LDO10_LDO10CONF 0X80
#define DA9052_LDO10_LDO10EN 0X40
#define DA9052_LDO10_VLDO10 0X3F
/* SUPPLY REGISTER BITS */
#define DA9052_SUPPLY_VLOCK 0X80
#define DA9052_SUPPLY_VMEMSWEN 0X40
#define DA9052_SUPPLY_VPERISWEN 0X20
#define DA9052_SUPPLY_VLDO3GO 0X10
#define DA9052_SUPPLY_VLDO2GO 0X08
#define DA9052_SUPPLY_VBMEMGO 0X04
#define DA9052_SUPPLY_VBPROGO 0X02
#define DA9052_SUPPLY_VBCOREGO 0X01
/* PULLDOWN REGISTER BITS */
#define DA9052_PULLDOWN_LDO5PDDIS 0X20
#define DA9052_PULLDOWN_LDO2PDDIS 0X10
#define DA9052_PULLDOWN_LDO1PDDIS 0X08
#define DA9052_PULLDOWN_MEMPDDIS 0X04
#define DA9052_PULLDOWN_PROPDDIS 0X02
#define DA9052_PULLDOWN_COREPDDIS 0X01
/* BAT CHARGER REGISTER BITS */
/* CHARGER BUCK REGISTER BITS */
#define DA9052_CHGBUCK_CHGTEMP 0X80
#define DA9052_CHGBUCK_CHGUSBILIM 0X40
#define DA9052_CHGBUCK_CHGBUCKLP 0X20
#define DA9052_CHGBUCK_CHGBUCKEN 0X10
#define DA9052_CHGBUCK_ISETBUCK 0X0F
/* WAIT COUNTER REGISTER BITS */
#define DA9052_WAITCONT_WAITDIR 0X80
#define DA9052_WAITCONT_RTCCLOCK 0X40
#define DA9052_WAITCONT_WAITMODE 0X20
#define DA9052_WAITCONT_EN32KOUT 0X10
#define DA9052_WAITCONT_DELAYTIME 0X0F
/* ISET CONTROL REGISTER BITS */
#define DA9052_ISET_ISETDCIN 0XF0
#define DA9052_ISET_ISETVBUS 0X0F
/* BATTERY CHARGER CONTROL REGISTER BITS */
#define DA9052_BATCHG_ICHGPRE 0XC0
#define DA9052_BATCHG_ICHGBAT 0X3F
/* CHARGER COUNTER REGISTER BITS */
#define DA9052_CHG_CONT_VCHG_BAT 0XF8
#define DA9052_CHG_CONT_TCTR 0X07
/* INPUT CONTROL REGISTER BITS */
#define DA9052_INPUT_CONT_TCTR_MODE 0X80
#define DA9052_INPUT_CONT_VBUS_SUSP 0X10
#define DA9052_INPUT_CONT_DCIN_SUSP 0X08
/* CHARGING TIME REGISTER BITS */
#define DA9052_CHGTIME_CHGTIME 0XFF
/* BACKUP BATTERY CONTROL REGISTER BITS */
#define DA9052_BBATCONT_BCHARGERISET 0XF0
#define DA9052_BBATCONT_BCHARGERVSET 0X0F
/* LED REGISTERS BITS */
/* LED BOOST REGISTER BITS */
#define DA9052_BOOST_EBFAULT 0X80
#define DA9052_BOOST_MBFAULT 0X40
#define DA9052_BOOST_BOOSTFRQ 0X20
#define DA9052_BOOST_BOOSTILIM 0X10
#define DA9052_BOOST_LED3INEN 0X08
#define DA9052_BOOST_LED2INEN 0X04
#define DA9052_BOOST_LED1INEN 0X02
#define DA9052_BOOST_BOOSTEN 0X01
/* LED CONTROL REGISTER BITS */
#define DA9052_LEDCONT_SELLEDMODE 0X80
#define DA9052_LEDCONT_LED3ICONT 0X40
#define DA9052_LEDCONT_LED3RAMP 0X20
#define DA9052_LEDCONT_LED3EN 0X10
#define DA9052_LEDCONT_LED2RAMP 0X08
#define DA9052_LEDCONT_LED2EN 0X04
#define DA9052_LEDCONT_LED1RAMP 0X02
#define DA9052_LEDCONT_LED1EN 0X01
/* LEDMIN123 REGISTER BIT */
#define DA9052_LEDMIN123_LEDMINCURRENT 0XFF
/* LED1CONF REGISTER BIT */
#define DA9052_LED1CONF_LED1CURRENT 0XFF
/* LED2CONF REGISTER BIT */
#define DA9052_LED2CONF_LED2CURRENT 0XFF
/* LED3CONF REGISTER BIT */
#define DA9052_LED3CONF_LED3CURRENT 0XFF
/* LED COUNT REGISTER BIT */
#define DA9052_LED_CONT_DIM 0X80
/* ADC MAN REGISTERS BITS */
#define DA9052_ADC_MAN_MAN_CONV 0X10
#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00
#define DA9052_ADC_MAN_MUXSEL_ICH 0X01
#define DA9052_ADC_MAN_MUXSEL_TBAT 0X02
#define DA9052_ADC_MAN_MUXSEL_VBAT 0X03
#define DA9052_ADC_MAN_MUXSEL_AD4 0X04
#define DA9052_ADC_MAN_MUXSEL_AD5 0X05
#define DA9052_ADC_MAN_MUXSEL_AD6 0X06
#define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09
/* ADC CONTROL REGSISTERS BITS */
#define DA9052_ADCCONT_COMP1V2EN 0X80
#define DA9052_ADCCONT_ADCMODE 0X40
#define DA9052_ADCCONT_TBATISRCEN 0X20
#define DA9052_ADCCONT_AD4ISRCEN 0X10
#define DA9052_ADCCONT_AUTOAD6EN 0X08
#define DA9052_ADCCONT_AUTOAD5EN 0X04
#define DA9052_ADCCONT_AUTOAD4EN 0X02
#define DA9052_ADCCONT_AUTOVDDEN 0X01
/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
#define DA9052_ADC_RES_LSB 0X03
/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
#define DA9052_ADCRESH_ADCRESMSB 0XFF
/* VDD RES REGSISTER BIT*/
#define DA9052_VDDRES_VDDOUTRES 0XFF
/* VDD MON REGSISTER BIT */
#define DA9052_VDDMON_VDDOUTMON 0XFF
/* ICHG_AV REGSISTER BIT */
#define DA9052_ICHGAV_ICHGAV 0XFF
/* ICHG_THD REGSISTER BIT */
#define DA9052_ICHGTHD_ICHGTHD 0XFF
/* ICHG_END REGSISTER BIT */
#define DA9052_ICHGEND_ICHGEND 0XFF
/* TBAT_RES REGSISTER BIT */
#define DA9052_TBATRES_TBATRES 0XFF
/* TBAT_HIGHP REGSISTER BIT */
#define DA9052_TBATHIGHP_TBATHIGHP 0XFF
/* TBAT_HIGHN REGSISTER BIT */
#define DA9052_TBATHIGHN_TBATHIGHN 0XFF
/* TBAT_LOW REGSISTER BIT */
#define DA9052_TBATLOW_TBATLOW 0XFF
/* T_OFFSET REGSISTER BIT */
#define DA9052_TOFFSET_TOFFSET 0XFF
/* ADCIN4_RES REGSISTER BIT */
#define DA9052_ADCIN4RES_ADCIN4RES 0XFF
/* ADCIN4_HIGH REGSISTER BIT */
#define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF
/* ADCIN4_LOW REGSISTER BIT */
#define DA9052_AUTO4LOW_AUTO4LOW 0XFF
/* ADCIN5_RES REGSISTER BIT */
#define DA9052_ADCIN5RES_ADCIN5RES 0XFF
/* ADCIN5_HIGH REGSISTER BIT */
#define DA9052_AUTO5HIGH_AUTOHIGH 0XFF
/* ADCIN5_LOW REGSISTER BIT */
#define DA9052_AUTO5LOW_AUTO5LOW 0XFF
/* ADCIN6_RES REGSISTER BIT */
#define DA9052_ADCIN6RES_ADCIN6RES 0XFF
/* ADCIN6_HIGH REGSISTER BIT */
#define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF
/* ADCIN6_LOW REGSISTER BIT */
#define DA9052_AUTO6LOW_AUTO6LOW 0XFF
/* TJUNC_RES REGSISTER BIT*/
#define DA9052_TJUNCRES_TJUNCRES 0XFF
/* TSI REGISTER */
/* TSI CONTROL REGISTER A BITS */
#define DA9052_TSICONTA_TSIDELAY 0XC0
#define DA9052_TSICONTA_TSISKIP 0X38
#define DA9052_TSICONTA_TSIMODE 0X04
#define DA9052_TSICONTA_PENDETEN 0X02
#define DA9052_TSICONTA_AUTOTSIEN 0X01
/* TSI CONTROL REGISTER B BITS */
#define DA9052_TSICONTB_ADCREF 0X80
#define DA9052_TSICONTB_TSIMAN 0X40
#define DA9052_TSICONTB_TSIMUX_XP 0X00
#define DA9052_TSICONTB_TSIMUX_YP 0X10
#define DA9052_TSICONTB_TSIMUX_XN 0X20
#define DA9052_TSICONTB_TSIMUX_YN 0X30
#define DA9052_TSICONTB_TSISEL3 0X08
#define DA9052_TSICONTB_TSISEL2 0X04
#define DA9052_TSICONTB_TSISEL1 0X02
#define DA9052_TSICONTB_TSISEL0 0X01
/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIXMSB_TSIXM 0XFF
/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIYMSB_TSIYM 0XFF
/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
#define DA9052_TSILSB_PENDOWN 0X40
#define DA9052_TSILSB_TSIZL 0X30
#define DA9052_TSILSB_TSIZL_SHIFT 4
#define DA9052_TSILSB_TSIZL_BITS 2
#define DA9052_TSILSB_TSIYL 0X0C
#define DA9052_TSILSB_TSIYL_SHIFT 2
#define DA9052_TSILSB_TSIYL_BITS 2
#define DA9052_TSILSB_TSIXL 0X03
#define DA9052_TSILSB_TSIXL_SHIFT 0
#define DA9052_TSILSB_TSIXL_BITS 2
/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
#define DA9052_TSIZMSB_TSIZM 0XFF
/* RTC REGISTER */
/* RTC TIMER SECONDS REGISTER BITS */
#define DA9052_COUNTS_MONITOR 0X40
#define DA9052_RTC_SEC 0X3F
/* RTC TIMER MINUTES REGISTER BIT */
#define DA9052_RTC_MIN 0X3F
/* RTC TIMER HOUR REGISTER BIT */
#define DA9052_RTC_HOUR 0X1F
/* RTC TIMER DAYS REGISTER BIT */
#define DA9052_RTC_DAY 0X1F
/* RTC TIMER MONTHS REGISTER BIT */
#define DA9052_RTC_MONTH 0X0F
/* RTC TIMER YEARS REGISTER BIT */
#define DA9052_RTC_YEAR 0X3F
/* RTC ALARM MINUTES REGISTER BITS */
#define DA9052_ALARMM_I_TICK_TYPE 0X80
#define DA9052_ALARMMI_ALARMTYPE 0X40
/* RTC ALARM YEARS REGISTER BITS */
#define DA9052_ALARM_Y_TICK_ON 0X80
#define DA9052_ALARM_Y_ALARM_ON 0X40
/* RTC SECONDS REGISTER A BITS */
#define DA9052_SECONDA_SECONDSA 0XFF
/* RTC SECONDS REGISTER B BITS */
#define DA9052_SECONDB_SECONDSB 0XFF
/* RTC SECONDS REGISTER C BITS */
#define DA9052_SECONDC_SECONDSC 0XFF
/* RTC SECONDS REGISTER D BITS */
#define DA9052_SECONDD_SECONDSD 0XFF
#endif
/* __LINUX_MFD_DA9052_REG_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9055/core.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* da9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*/
#ifndef __DA9055_CORE_H
#define __DA9055_CORE_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
/*
* PMIC IRQ
*/
#define DA9055_IRQ_ALARM 0x01
#define DA9055_IRQ_TICK 0x02
#define DA9055_IRQ_NONKEY 0x00
#define DA9055_IRQ_REGULATOR 0x0B
#define DA9055_IRQ_HWMON 0x03
struct da9055_pdata;
struct da9055 {
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
struct device *dev;
struct i2c_client *i2c_client;
int irq_base;
int chip_irq;
};
/* Device I/O */
static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9055->regmap, reg, &val);
if (ret < 0)
return ret;
return val;
}
static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
unsigned char val)
{
return regmap_write(da9055->regmap, reg, val);
}
static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
}
/* Generic Device API */
int da9055_device_init(struct da9055 *da9055);
void da9055_device_exit(struct da9055 *da9055);
extern const struct regmap_config da9055_regmap_config;
#endif /* __DA9055_CORE_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9055/pdata.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (C) 2012 Dialog Semiconductor Ltd.
*/
#ifndef __DA9055_PDATA_H
#define __DA9055_PDATA_H
#define DA9055_MAX_REGULATORS 8
struct da9055;
enum gpio_select {
NO_GPIO = 0,
GPIO_1,
GPIO_2
};
struct da9055_pdata {
int (*init) (struct da9055 *da9055);
int irq_base;
int gpio_base;
struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
/* Enable RTC in RESET Mode */
bool reset_enable;
/*
* Regulator mode control bits value (GPI offset) that
* controls the regulator state, 0 if not available.
*/
enum gpio_select *reg_ren;
/*
* Regulator mode control bits value (GPI offset) that
* controls the regulator set A/B, 0 if not available.
*/
enum gpio_select *reg_rsel;
};
#endif /* __DA9055_PDATA_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9055/reg.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* DA9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*/
#ifndef __DA9055_REG_H
#define __DA9055_REG_H
/*
* PMIC registers
*/
/* PAGE0 */
#define DA9055_REG_PAGE_CON 0x00
/* System Control and Event Registers */
#define DA9055_REG_STATUS_A 0x01
#define DA9055_REG_STATUS_B 0x02
#define DA9055_REG_FAULT_LOG 0x03
#define DA9055_REG_EVENT_A 0x04
#define DA9055_REG_EVENT_B 0x05
#define DA9055_REG_EVENT_C 0x06
#define DA9055_REG_IRQ_MASK_A 0x07
#define DA9055_REG_IRQ_MASK_B 0x08
#define DA9055_REG_IRQ_MASK_C 0x09
#define DA9055_REG_CONTROL_A 0x0A
#define DA9055_REG_CONTROL_B 0x0B
#define DA9055_REG_CONTROL_C 0x0C
#define DA9055_REG_CONTROL_D 0x0D
#define DA9055_REG_CONTROL_E 0x0E
#define DA9055_REG_PD_DIS 0x0F
/* GPIO Control Registers */
#define DA9055_REG_GPIO0_1 0x10
#define DA9055_REG_GPIO2 0x11
#define DA9055_REG_GPIO_MODE0_2 0x12
/* Regulator Control Registers */
#define DA9055_REG_BCORE_CONT 0x13
#define DA9055_REG_BMEM_CONT 0x14
#define DA9055_REG_LDO1_CONT 0x15
#define DA9055_REG_LDO2_CONT 0x16
#define DA9055_REG_LDO3_CONT 0x17
#define DA9055_REG_LDO4_CONT 0x18
#define DA9055_REG_LDO5_CONT 0x19
#define DA9055_REG_LDO6_CONT 0x1A
/* GP-ADC Control Registers */
#define DA9055_REG_ADC_MAN 0x1B
#define DA9055_REG_ADC_CONT 0x1C
#define DA9055_REG_VSYS_MON 0x1D
#define DA9055_REG_ADC_RES_L 0x1E
#define DA9055_REG_ADC_RES_H 0x1F
#define DA9055_REG_VSYS_RES 0x20
#define DA9055_REG_ADCIN1_RES 0x21
#define DA9055_REG_ADCIN2_RES 0x22
#define DA9055_REG_ADCIN3_RES 0x23
/* Sequencer Control Registers */
#define DA9055_REG_EN_32K 0x35
/* Regulator Setting Registers */
#define DA9055_REG_BUCK_LIM 0x37
#define DA9055_REG_BCORE_MODE 0x38
#define DA9055_REG_VBCORE_A 0x39
#define DA9055_REG_VBMEM_A 0x3A
#define DA9055_REG_VLDO1_A 0x3B
#define DA9055_REG_VLDO2_A 0x3C
#define DA9055_REG_VLDO3_A 0x3D
#define DA9055_REG_VLDO4_A 0x3E
#define DA9055_REG_VLDO5_A 0x3F
#define DA9055_REG_VLDO6_A 0x40
#define DA9055_REG_VBCORE_B 0x41
#define DA9055_REG_VBMEM_B 0x42
#define DA9055_REG_VLDO1_B 0x43
#define DA9055_REG_VLDO2_B 0x44
#define DA9055_REG_VLDO3_B 0x45
#define DA9055_REG_VLDO4_B 0x46
#define DA9055_REG_VLDO5_B 0x47
#define DA9055_REG_VLDO6_B 0x48
/* GP-ADC Threshold Registers */
#define DA9055_REG_AUTO1_HIGH 0x49
#define DA9055_REG_AUTO1_LOW 0x4A
#define DA9055_REG_AUTO2_HIGH 0x4B
#define DA9055_REG_AUTO2_LOW 0x4C
#define DA9055_REG_AUTO3_HIGH 0x4D
#define DA9055_REG_AUTO3_LOW 0x4E
/* OTP */
#define DA9055_REG_OPT_COUNT 0x50
#define DA9055_REG_OPT_ADDR 0x51
#define DA9055_REG_OPT_DATA 0x52
/* RTC Calendar and Alarm Registers */
#define DA9055_REG_COUNT_S 0x53
#define DA9055_REG_COUNT_MI 0x54
#define DA9055_REG_COUNT_H 0x55
#define DA9055_REG_COUNT_D 0x56
#define DA9055_REG_COUNT_MO 0x57
#define DA9055_REG_COUNT_Y 0x58
#define DA9055_REG_ALARM_MI 0x59
#define DA9055_REG_ALARM_H 0x5A
#define DA9055_REG_ALARM_D 0x5B
#define DA9055_REG_ALARM_MO 0x5C
#define DA9055_REG_ALARM_Y 0x5D
#define DA9055_REG_SECOND_A 0x5E
#define DA9055_REG_SECOND_B 0x5F
#define DA9055_REG_SECOND_C 0x60
#define DA9055_REG_SECOND_D 0x61
/* Customer Trim and Configuration */
#define DA9055_REG_T_OFFSET 0x63
#define DA9055_REG_INTERFACE 0x64
#define DA9055_REG_CONFIG_A 0x65
#define DA9055_REG_CONFIG_B 0x66
#define DA9055_REG_CONFIG_C 0x67
#define DA9055_REG_CONFIG_D 0x68
#define DA9055_REG_CONFIG_E 0x69
#define DA9055_REG_TRIM_CLDR 0x6F
/* General Purpose Registers */
#define DA9055_REG_GP_ID_0 0x70
#define DA9055_REG_GP_ID_1 0x71
#define DA9055_REG_GP_ID_2 0x72
#define DA9055_REG_GP_ID_3 0x73
#define DA9055_REG_GP_ID_4 0x74
#define DA9055_REG_GP_ID_5 0x75
#define DA9055_REG_GP_ID_6 0x76
#define DA9055_REG_GP_ID_7 0x77
#define DA9055_REG_GP_ID_8 0x78
#define DA9055_REG_GP_ID_9 0x79
#define DA9055_REG_GP_ID_10 0x7A
#define DA9055_REG_GP_ID_11 0x7B
#define DA9055_REG_GP_ID_12 0x7C
#define DA9055_REG_GP_ID_13 0x7D
#define DA9055_REG_GP_ID_14 0x7E
#define DA9055_REG_GP_ID_15 0x7F
#define DA9055_REG_GP_ID_16 0x80
#define DA9055_REG_GP_ID_17 0x81
#define DA9055_REG_GP_ID_18 0x82
#define DA9055_REG_GP_ID_19 0x83
#define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19
/*
* PMIC registers bits
*/
/* DA9055_REG_PAGE_CON (addr=0x00) */
#define DA9055_PAGE_WRITE_MODE (0<<6)
#define DA9055_REPEAT_WRITE_MODE (1<<6)
/* DA9055_REG_STATUS_A (addr=0x01) */
#define DA9055_NOKEY_STS 0x01
#define DA9055_WAKE_STS 0x02
#define DA9055_DVC_BUSY_STS 0x04
#define DA9055_COMP1V2_STS 0x08
#define DA9055_NJIG_STS 0x10
#define DA9055_LDO5_LIM_STS 0x20
#define DA9055_LDO6_LIM_STS 0x40
/* DA9055_REG_STATUS_B (addr=0x02) */
#define DA9055_GPI0_STS 0x01
#define DA9055_GPI1_STS 0x02
#define DA9055_GPI2_STS 0x04
/* DA9055_REG_FAULT_LOG (addr=0x03) */
#define DA9055_TWD_ERROR_FLG 0x01
#define DA9055_POR_FLG 0x02
#define DA9055_VDD_FAULT_FLG 0x04
#define DA9055_VDD_START_FLG 0x08
#define DA9055_TEMP_CRIT_FLG 0x10
#define DA9055_KEY_RESET_FLG 0x20
#define DA9055_WAIT_SHUT_FLG 0x80
/* DA9055_REG_EVENT_A (addr=0x04) */
#define DA9055_NOKEY_EINT 0x01
#define DA9055_ALARM_EINT 0x02
#define DA9055_TICK_EINT 0x04
#define DA9055_ADC_RDY_EINT 0x08
#define DA9055_SEQ_RDY_EINT 0x10
#define DA9055_EVENTS_B_EINT 0x20
#define DA9055_EVENTS_C_EINT 0x40
/* DA9055_REG_EVENT_B (addr=0x05) */
#define DA9055_E_WAKE_EINT 0x01
#define DA9055_E_TEMP_EINT 0x02
#define DA9055_E_COMP1V2_EINT 0x04
#define DA9055_E_LDO_LIM_EINT 0x08
#define DA9055_E_NJIG_EINT 0x20
#define DA9055_E_VDD_MON_EINT 0x40
#define DA9055_E_VDD_WARN_EINT 0x80
/* DA9055_REG_EVENT_C (addr=0x06) */
#define DA9055_E_GPI0_EINT 0x01
#define DA9055_E_GPI1_EINT 0x02
#define DA9055_E_GPI2_EINT 0x04
/* DA9055_REG_IRQ_MASK_A (addr=0x07) */
#define DA9055_M_NONKEY_EINT 0x01
#define DA9055_M_ALARM_EINT 0x02
#define DA9055_M_TICK_EINT 0x04
#define DA9055_M_ADC_RDY_EINT 0x08
#define DA9055_M_SEQ_RDY_EINT 0x10
/* DA9055_REG_IRQ_MASK_B (addr=0x08) */
#define DA9055_M_WAKE_EINT 0x01
#define DA9055_M_TEMP_EINT 0x02
#define DA9055_M_COMP_1V2_EINT 0x04
#define DA9055_M_LDO_LIM_EINT 0x08
#define DA9055_M_NJIG_EINT 0x20
#define DA9055_M_VDD_MON_EINT 0x40
#define DA9055_M_VDD_WARN_EINT 0x80
/* DA9055_REG_IRQ_MASK_C (addr=0x09) */
#define DA9055_M_GPI0_EINT 0x01
#define DA9055_M_GPI1_EINT 0x02
#define DA9055_M_GPI2_EINT 0x04
/* DA9055_REG_CONTROL_A (addr=0xA) */
#define DA9055_DEBOUNCING_SHIFT 0x00
#define DA9055_DEBOUNCING_MASK 0x07
#define DA9055_NRES_MODE_SHIFT 0x03
#define DA9055_NRES_MODE_MASK 0x08
#define DA9055_SLEW_RATE_SHIFT 0x04
#define DA9055_SLEW_RATE_MASK 0x30
#define DA9055_NOKEY_LOCK_SHIFT 0x06
#define DA9055_NOKEY_LOCK_MASK 0x40
/* DA9055_REG_CONTROL_B (addr=0xB) */
#define DA9055_RTC_MODE_PD 0x01
#define DA9055_RTC_MODE_SD_SHIFT 0x01
#define DA9055_RTC_MODE_SD 0x02
#define DA9055_RTC_EN 0x04
#define DA9055_ECO_MODE_SHIFT 0x03
#define DA9055_ECO_MODE_MASK 0x08
#define DA9055_TWDSCALE_SHIFT 4
#define DA9055_TWDSCALE_MASK 0x70
#define DA9055_V_LOCK_SHIFT 0x07
#define DA9055_V_LOCK_MASK 0x80
/* DA9055_REG_CONTROL_C (addr=0xC) */
#define DA9055_SYSTEM_EN_SHIFT 0x00
#define DA9055_SYSTEM_EN_MASK 0x01
#define DA9055_POWERN_EN_SHIFT 0x01
#define DA9055_POWERN_EN_MASK 0x02
#define DA9055_POWER1_EN_SHIFT 0x02
#define DA9055_POWER1_EN_MASK 0x04
/* DA9055_REG_CONTROL_D (addr=0xD) */
#define DA9055_STANDBY_SHIFT 0x02
#define DA9055_STANDBY_MASK 0x08
#define DA9055_AUTO_BOOT_SHIFT 0x03
#define DA9055_AUTO_BOOT_MASK 0x04
/* DA9055_REG_CONTROL_E (addr=0xE) */
#define DA9055_WATCHDOG_SHIFT 0x00
#define DA9055_WATCHDOG_MASK 0x01
#define DA9055_SHUTDOWN_SHIFT 0x01
#define DA9055_SHUTDOWN_MASK 0x02
#define DA9055_WAKE_UP_SHIFT 0x02
#define DA9055_WAKE_UP_MASK 0x04
/* DA9055_REG_GPIO (addr=0x10/0x11) */
#define DA9055_GPIO0_PIN_SHIFT 0x00
#define DA9055_GPIO0_PIN_MASK 0x03
#define DA9055_GPIO0_TYPE_SHIFT 0x02
#define DA9055_GPIO0_TYPE_MASK 0x04
#define DA9055_GPIO0_WEN_SHIFT 0x03
#define DA9055_GPIO0_WEN_MASK 0x08
#define DA9055_GPIO1_PIN_SHIFT 0x04
#define DA9055_GPIO1_PIN_MASK 0x30
#define DA9055_GPIO1_TYPE_SHIFT 0x06
#define DA9055_GPIO1_TYPE_MASK 0x40
#define DA9055_GPIO1_WEN_SHIFT 0x07
#define DA9055_GPIO1_WEN_MASK 0x80
#define DA9055_GPIO2_PIN_SHIFT 0x00
#define DA9055_GPIO2_PIN_MASK 0x30
#define DA9055_GPIO2_TYPE_SHIFT 0x02
#define DA9055_GPIO2_TYPE_MASK 0x04
#define DA9055_GPIO2_WEN_SHIFT 0x03
#define DA9055_GPIO2_WEN_MASK 0x08
/* DA9055_REG_GPIO_MODE (addr=0x12) */
#define DA9055_GPIO0_MODE_SHIFT 0x00
#define DA9055_GPIO0_MODE_MASK 0x01
#define DA9055_GPIO1_MODE_SHIFT 0x01
#define DA9055_GPIO1_MODE_MASK 0x02
#define DA9055_GPIO2_MODE_SHIFT 0x02
#define DA9055_GPIO2_MODE_MASK 0x04
/* DA9055_REG_BCORE_CONT (addr=0x13) */
#define DA9055_BCORE_EN_SHIFT 0x00
#define DA9055_BCORE_EN_MASK 0x01
#define DA9055_BCORE_GPI_SHIFT 0x01
#define DA9055_BCORE_GPI_MASK 0x02
#define DA9055_BCORE_PD_DIS_SHIFT 0x03
#define DA9055_BCORE_PD_DIS_MASK 0x04
#define DA9055_VBCORE_SEL_SHIFT 0x04
#define DA9055_SEL_REG_A 0x0
#define DA9055_SEL_REG_B 0x10
#define DA9055_VBCORE_SEL_MASK 0x10
#define DA9055_V_GPI_MASK 0x60
#define DA9055_V_GPI_SHIFT 0x05
#define DA9055_E_GPI_MASK 0x06
#define DA9055_E_GPI_SHIFT 0x01
#define DA9055_VBCORE_GPI_SHIFT 0x05
#define DA9055_VBCORE_GPI_MASK 0x60
#define DA9055_BCORE_CONF_SHIFT 0x07
#define DA9055_BCORE_CONF_MASK 0x80
/* DA9055_REG_BMEM_CONT (addr=0x14) */
#define DA9055_BMEM_EN_SHIFT 0x00
#define DA9055_BMEM_EN_MASK 0x01
#define DA9055_BMEM_GPI_SHIFT 0x01
#define DA9055_BMEM_GPI_MASK 0x06
#define DA9055_BMEM_PD_DIS_SHIFT 0x03
#define DA9055_BMEM_PD_DIS_MASK 0x08
#define DA9055_VBMEM_SEL_SHIT 0x04
#define DA9055_VBMEM_SEL_VBMEM_A (0<<4)
#define DA9055_VBMEM_SEL_VBMEM_B (1<<4)
#define DA9055_VBMEM_SEL_MASK 0x10
#define DA9055_VBMEM_GPI_SHIFT 0x05
#define DA9055_VBMEM_GPI_MASK 0x60
#define DA9055_BMEM_CONF_SHIFT 0x07
#define DA9055_BMEM_CONF_MASK 0x80
/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
#define DA9055_LDO_EN_SHIFT 0x00
#define DA9055_LDO_EN_MASK 0x01
#define DA9055_LDO_GPI_SHIFT 0x01
#define DA9055_LDO_GPI_MASK 0x06
#define DA9055_LDO_PD_DIS_SHIFT 0x03
#define DA9055_LDO_PD_DIS_MASK 0x08
#define DA9055_VLDO_SEL_SHIFT 0x04
#define DA9055_VLDO_SEL_MASK 0x10
#define DA9055_VLDO_SEL_VLDO_A 0x00
#define DA9055_VLDO_SEL_VLDO_B 0x01
#define DA9055_VLDO_GPI_SHIFT 0x05
#define DA9055_VLDO_GPI_MASK 0x60
#define DA9055_LDO_CONF_SHIFT 0x07
#define DA9055_LDO_CONF_MASK 0x80
#define DA9055_REGUALTOR_SET_A 0x00
#define DA9055_REGUALTOR_SET_B 0x10
/* DA9055_REG_ADC_MAN (addr=0x1B) */
#define DA9055_ADC_MUX_SHIFT 0
#define DA9055_ADC_MUX_MASK 0xF
#define DA9055_ADC_MUX_VSYS 0x0
#define DA9055_ADC_MUX_ADCIN1 0x01
#define DA9055_ADC_MUX_ADCIN2 0x02
#define DA9055_ADC_MUX_ADCIN3 0x03
#define DA9055_ADC_MUX_T_SENSE 0x04
#define DA9055_ADC_MAN_SHIFT 0x04
#define DA9055_ADC_MAN_CONV 0x10
#define DA9055_ADC_LSB_MASK 0X03
#define DA9055_ADC_MODE_MASK 0x20
#define DA9055_ADC_MODE_SHIFT 5
#define DA9055_ADC_MODE_1MS (1<<5)
#define DA9055_COMP1V2_EN_SHIFT 7
/* DA9055_REG_ADC_CONT (addr=0x1C) */
#define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0
#define DA9055_ADC_AUTO_AD1_EN_SHIFT 1
#define DA9055_ADC_AUTO_AD2_EN_SHIFT 2
#define DA9055_ADC_AUTO_AD3_EN_SHIFT 3
#define DA9055_ADC_ISRC_EN_SHIFT 4
#define DA9055_ADC_ADCIN1_DEB_SHIFT 5
#define DA9055_ADC_ADCIN2_DEB_SHIFT 6
#define DA9055_ADC_ADCIN3_DEB_SHIFT 7
#define DA9055_AD1_ISRC_MASK 0x10
#define DA9055_AD1_ISRC_SHIFT 4
/* DA9055_REG_VSYS_MON (addr=0x1D) */
#define DA9055_VSYS_VAL_SHIFT 0
#define DA9055_VSYS_VAL_MASK 0xFF
#define DA9055_VSYS_VAL_BASE 0x00
#define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK
#define DA9055_VSYS_VOLT_BASE 2500
#define DA9055_VSYS_VOLT_INC 10
#define DA9055_VSYS_STEPS 255
#define DA9055_VSYS_VOLT_MIN 2500
/* DA9044_REG_XXX_RES (addr=0x20-0x23) */
#define DA9055_ADC_VAL_SHIFT 0
#define DA9055_ADC_VAL_MASK 0xFF
#define DA9055_ADC_VAL_BASE 0x00
#define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK
#define DA9055_ADC_VOLT_BASE 0
#define DA9055_ADC_VSYS_VOLT_BASE 2500
#define DA9055_ADC_VOLT_INC 10
#define DA9055_ADC_VSYS_VOLT_INC 12
#define DA9055_ADC_STEPS 255
/* DA9055_REG_EN_32K (addr=0x35)*/
#define DA9055_STARTUP_TIME_MASK 0x07
#define DA9055_STARTUP_TIME_0S 0x0
#define DA9055_STARTUP_TIME_0_52S 0x1
#define DA9055_STARTUP_TIME_1S 0x2
#define DA9055_CRYSTAL_EN 0x08
#define DA9055_DELAY_MODE_EN 0x10
#define DA9055_OUT_CLCK_GATED 0x20
#define DA9055_RTC_CLOCK_GATED 0x40
#define DA9055_EN_32KOUT_BUF 0x80
/* DA9055_REG_RESET (addr=0x36) */
/* Timer up to 31.744 ms */
#define DA9055_RESET_TIMER_VAL_SHIFT 0
#define DA9055_RESET_LOW_VAL_MASK 0x3F
#define DA9055_RESET_LOW_VAL_BASE 0
#define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK
#define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */
#define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */
#define DA9055_RESET_US_LOW_STEP 30
/* Timer up to 1048.576ms */
#define DA9055_RESET_HIGH_VAL_MASK 0x3F
#define DA9055_RESET_HIGH_VAL_BASE 0
#define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK
#define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */
#define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */
#define DA9055_RESET_US_HIGH_STEP 31
/* DA9055_REG_BUCK_ILIM (addr=0x37)*/
#define DA9055_BMEM_ILIM_SHIFT 0
#define DA9055_ILIM_MASK 0x3
#define DA9055_ILIM_500MA 0x0
#define DA9055_ILIM_600MA 0x1
#define DA9055_ILIM_700MA 0x2
#define DA9055_ILIM_800MA 0x3
#define DA9055_BCORE_ILIM_SHIFT 2
/* DA9055_REG_BCORE_MODE (addr=0x38) */
#define DA9055_BMEM_MODE_SHIFT 0
#define DA9055_MODE_MASK 0x3
#define DA9055_MODE_AB 0x0
#define DA9055_MODE_SLEEP 0x1
#define DA9055_MODE_SYNCHRO 0x2
#define DA9055_MODE_AUTO 0x3
#define DA9055_BCORE_MODE_SHIFT 2
/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
#define DA9055_VBCORE_VAL_SHIFT 0
#define DA9055_VBCORE_VAL_MASK 0x3F
#define DA9055_VBCORE_VAL_BASE 0x09
#define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK
#define DA9055_VBCORE_VOLT_BASE 750
#define DA9055_VBCORE_VOLT_INC 25
#define DA9055_VBCORE_STEPS 53
#define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE
#define DA9055_BCORE_SL_SYNCHRO (0<<7)
#define DA9055_BCORE_SL_SLEEP (1<<7)
/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
#define DA9055_VBMEM_VAL_SHIFT 0
#define DA9055_VBMEM_VAL_MASK 0x3F
#define DA9055_VBMEM_VAL_BASE 0x00
#define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK
#define DA9055_VBMEM_VOLT_BASE 925
#define DA9055_VBMEM_VOLT_INC 25
#define DA9055_VBMEM_STEPS 63
#define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE
#define DA9055_BCMEM_SL_SYNCHRO (0<<7)
#define DA9055_BCMEM_SL_SLEEP (1<<7)
/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
#define DA9055_VLDO_VAL_SHIFT 0
#define DA9055_VLDO_VAL_MASK 0x3F
#define DA9055_VLDO6_VAL_MASK 0x7F
#define DA9055_VLDO_VAL_BASE 0x02
#define DA9055_VLDO2_VAL_BASE 0x03
#define DA9055_VLDO6_VAL_BASE 0x00
#define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK
#define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK
#define DA9055_VLDO_VOLT_BASE 900
#define DA9055_VLDO_VOLT_INC 50
#define DA9055_VLDO6_VOLT_INC 20
#define DA9055_VLDO_STEPS 48
#define DA9055_VLDO5_STEPS 37
#define DA9055_VLDO6_STEPS 120
#define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE
#define DA9055_LDO_MODE_SHIFT 7
#define DA9055_LDO_SL_NORMAL 0
#define DA9055_LDO_SL_SLEEP 1
/* DA9055_REG_OTP_CONT (addr=0x50) */
#define DA9055_OTP_TIM_NORMAL (0<<0)
#define DA9055_OTP_TIM_MARGINAL (1<<0)
#define DA9055_OTP_GP_RD_SHIFT 1
#define DA9055_OTP_APPS_RD_SHIFT 2
#define DA9055_PC_DONE_SHIFT 3
#define DA9055_OTP_GP_LOCK_SHIFT 4
#define DA9055_OTP_APPS_LOCK_SHIFT 5
#define DA9055_OTP_CONF_LOCK_SHIFT 6
#define DA9055_OTP_WRITE_DIS_SHIFT 7
/* DA9055_REG_COUNT_S (addr=0x53) */
#define DA9055_RTC_SEC 0x3F
#define DA9055_RTC_MONITOR_EN 0x40
#define DA9055_RTC_READ 0x80
/* DA9055_REG_COUNT_MI (addr=0x54) */
#define DA9055_RTC_MIN 0x3F
/* DA9055_REG_COUNT_H (addr=0x55) */
#define DA9055_RTC_HOUR 0x1F
/* DA9055_REG_COUNT_D (addr=0x56) */
#define DA9055_RTC_DAY 0x1F
/* DA9055_REG_COUNT_MO (addr=0x57) */
#define DA9055_RTC_MONTH 0x0F
/* DA9055_REG_COUNT_Y (addr=0x58) */
#define DA9055_RTC_YEAR 0x3F
#define DA9055_RTC_YEAR_BASE 2000
/* DA9055_REG_ALARM_MI (addr=0x59) */
#define DA9055_RTC_ALM_MIN 0x3F
#define DA9055_ALARM_STATUS_SHIFT 6
#define DA9055_ALARM_STATUS_MASK 0x3
#define DA9055_ALARM_STATUS_NO_ALARM 0x0
#define DA9055_ALARM_STATUS_TICK 0x1
#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
#define DA9055_ALARM_STATUS_BOTH 0x3
/* DA9055_REG_ALARM_H (addr=0x5A) */
#define DA9055_RTC_ALM_HOUR 0x1F
/* DA9055_REG_ALARM_D (addr=0x5B) */
#define DA9055_RTC_ALM_DAY 0x1F
/* DA9055_REG_ALARM_MO (addr=0x5C) */
#define DA9055_RTC_ALM_MONTH 0x0F
#define DA9055_RTC_TICK_WAKE_MASK 0x20
#define DA9055_RTC_TICK_WAKE_SHIFT 5
#define DA9055_RTC_TICK_TYPE 0x10
#define DA9055_RTC_TICK_TYPE_SHIFT 0x4
#define DA9055_RTC_TICK_SEC 0x0
#define DA9055_RTC_TICK_MIN 0x1
#define DA9055_ALARAM_TICK_WAKE 0x20
/* DA9055_REG_ALARM_Y (addr=0x5D) */
#define DA9055_RTC_TICK_EN 0x80
#define DA9055_RTC_ALM_EN 0x40
#define DA9055_RTC_TICK_ALM_MASK 0xC0
#define DA9055_RTC_ALM_YEAR 0x3F
/* DA9055_REG_TRIM_CLDR (addr=0x62) */
#define DA9055_TRIM_32K_SHIFT 0
#define DA9055_TRIM_32K_MASK 0x7F
#define DA9055_TRIM_DECREMENT (1<<7)
#define DA9055_TRIM_INCREMENT (0<<7)
#define DA9055_TRIM_VAL_BASE 0x0
#define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */
#define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */
#define DA9055_TRIM_STEPS 127
/* DA9055_REG_CONFIG_A (addr=0x65) */
#define DA9055_PM_I_V_VDDCORE (0<<0)
#define DA9055_PM_I_V_VDD_IO (1<<0)
#define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1)
#define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1)
#define DA9055_PM_O_TYPE_PUSH_PULL (0<<2)
#define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2)
#define DA9055_IRQ_TYPE_ACT_LOW (0<<3)
#define DA9055_IRQ_TYPE_ACT_HIGH (1<<3)
#define DA9055_NIRQ_MODE_IMM (0<<4)
#define DA9055_NIRQ_MODE_ACTIVE (1<<4)
#define DA9055_GPI_V_VDDCORE (0<<5)
#define DA9055_GPI_V_VDD_IO (1<<5)
#define DA9055_PM_IF_V_VDDCORE (0<<6)
#define DA9055_PM_IF_V_VDD_IO (1<<6)
/* DA9055_REG_CONFIG_B (addr=0x66) */
#define DA9055_VDD_FAULT_VAL_SHIFT 0
#define DA9055_VDD_FAULT_VAL_MASK 0xF
#define DA9055_VDD_FAULT_VAL_BASE 0x0
#define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK
#define DA9055_VDD_FAULT_VOLT_BASE 2500
#define DA9055_VDD_FAULT_VOLT_INC 50
#define DA9055_VDD_FAULT_STEPS 15
#define DA9055_VDD_HYST_VAL_SHIFT 4
#define DA9055_VDD_HYST_VAL_MASK 0x7
#define DA9055_VDD_HYST_VAL_BASE 0x0
#define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK
#define DA9055_VDD_HYST_VOLT_BASE 100
#define DA9055_VDD_HYST_VOLT_INC 50
#define DA9055_VDD_HYST_STEPS 7
#define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE
#define DA9055_VDD_FAULT_EN_SHIFT 7
/* DA9055_REG_CONFIG_C (addr=0x67) */
#define DA9055_BCORE_CLK_INV_SHIFT 0
#define DA9055_BMEM_CLK_INV_SHIFT 1
#define DA9055_NFAULT_CONF_SHIFT 2
#define DA9055_LDO_SD_SHIFT 4
#define DA9055_LDO5_BYP_SHIFT 6
#define DA9055_LDO6_BYP_SHIFT 7
/* DA9055_REG_CONFIG_D (addr=0x68) */
#define DA9055_NONKEY_PIN_SHIFT 0
#define DA9055_NONKEY_PIN_MASK 0x3
#define DA9055_NONKEY_PIN_PORT_MODE 0x0
#define DA9055_NONKEY_PIN_KEY_MODE 0x1
#define DA9055_NONKEY_PIN_MULTI_FUNC 0x2
#define DA9055_NONKEY_PIN_DEDICT 0x3
#define DA9055_NONKEY_SD_SHIFT 2
#define DA9055_KEY_DELAY_SHIFT 3
#define DA9055_KEY_DELAY_MASK 0x3
#define DA9055_KEY_DELAY_4S 0x0
#define DA9055_KEY_DELAY_6S 0x1
#define DA9055_KEY_DELAY_8S 0x2
#define DA9055_KEY_DELAY_10S 0x3
/* DA9055_REG_CONFIG_E (addr=0x69) */
#define DA9055_GPIO_PUPD_PULL_UP 0x0
#define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1
#define DA9055_GPIO0_PUPD_SHIFT 0
#define DA9055_GPIO1_PUPD_SHIFT 1
#define DA9055_GPIO2_PUPD_SHIFT 2
#define DA9055_UVOV_DELAY_SHIFT 4
#define DA9055_UVOV_DELAY_MASK 0x3
#define DA9055_RESET_DURATION_SHIFT 6
#define DA9055_RESET_DURATION_MASK 0x3
#define DA9055_RESET_DURATION_0MS 0x0
#define DA9055_RESET_DURATION_100MS 0x1
#define DA9055_RESET_DURATION_500MS 0x2
#define DA9055_RESET_DURATION_1000MS 0x3
/* DA9055_REG_MON_REG_1 (addr=0x6A) */
#define DA9055_MON_THRES_SHIFT 0
#define DA9055_MON_THRES_MASK 0x3
#define DA9055_MON_RES_SHIFT 2
#define DA9055_MON_DEB_SHIFT 3
#define DA9055_MON_MODE_SHIFT 4
#define DA9055_MON_MODE_MASK 0x3
#define DA9055_START_MAX_SHIFT 6
#define DA9055_START_MAX_MASK 0x3
/* DA9055_REG_MON_REG_2 (addr=0x6B) */
#define DA9055_LDO1_MON_EN_SHIFT 0
#define DA9055_LDO2_MON_EN_SHIFT 1
#define DA9055_LDO3_MON_EN_SHIFT 2
#define DA9055_LDO4_MON_EN_SHIFT 3
#define DA9055_LDO5_MON_EN_SHIFT 4
#define DA9055_LDO6_MON_EN_SHIFT 5
#define DA9055_BCORE_MON_EN_SHIFT 6
#define DA9055_BMEM_MON_EN_SHIFT 7
/* DA9055_REG_CONFIG_F (addr=0x6C) */
#define DA9055_LDO1_DEF_SHIFT 0
#define DA9055_LDO2_DEF_SHIFT 1
#define DA9055_LDO3_DEF_SHIFT 2
#define DA9055_LDO4_DEF_SHIFT 3
#define DA9055_LDO5_DEF_SHIFT 4
#define DA9055_LDO6_DEF_SHIFT 5
#define DA9055_BCORE_DEF_SHIFT 6
#define DA9055_BMEM_DEF_SHIFT 7
/* DA9055_REG_MON_REG_4 (addr=0x6D) */
#define DA9055_MON_A8_IDX_SHIFT 0
#define DA9055_MON_A89_IDX_MASK 0x3
#define DA9055_MON_A89_IDX_NONE 0x0
#define DA9055_MON_A89_IDX_BUCKCORE 0x1
#define DA9055_MON_A89_IDX_LDO3 0x2
#define DA9055_MON_A9_IDX_SHIFT 5
/* DA9055_REG_MON_REG_5 (addr=0x6E) */
#define DA9055_MON_A10_IDX_SHIFT 0
#define DA9055_MON_A10_IDX_MASK 0x3
#define DA9055_MON_A10_IDX_NONE 0x0
#define DA9055_MON_A10_IDX_LDO1 0x1
#define DA9055_MON_A10_IDX_LDO2 0x2
#define DA9055_MON_A10_IDX_LDO5 0x3
#define DA9055_MON_A10_IDX_LDO6 0x4
#endif /* __DA9055_REG_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9062/core.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015-2017 Dialog Semiconductor
*/
#ifndef __MFD_DA9062_CORE_H__
#define __MFD_DA9062_CORE_H__
#include <linux/interrupt.h>
#include <linux/mfd/da9062/registers.h>
enum da9062_compatible_types {
COMPAT_TYPE_DA9061 = 1,
COMPAT_TYPE_DA9062,
};
enum da9061_irqs {
/* IRQ A */
DA9061_IRQ_ONKEY,
DA9061_IRQ_WDG_WARN,
DA9061_IRQ_SEQ_RDY,
/* IRQ B*/
DA9061_IRQ_TEMP,
DA9061_IRQ_LDO_LIM,
DA9061_IRQ_DVC_RDY,
DA9061_IRQ_VDD_WARN,
/* IRQ C */
DA9061_IRQ_GPI0,
DA9061_IRQ_GPI1,
DA9061_IRQ_GPI2,
DA9061_IRQ_GPI3,
DA9061_IRQ_GPI4,
DA9061_NUM_IRQ,
};
enum da9062_irqs {
/* IRQ A */
DA9062_IRQ_ONKEY,
DA9062_IRQ_ALARM,
DA9062_IRQ_TICK,
DA9062_IRQ_WDG_WARN,
DA9062_IRQ_SEQ_RDY,
/* IRQ B*/
DA9062_IRQ_TEMP,
DA9062_IRQ_LDO_LIM,
DA9062_IRQ_DVC_RDY,
DA9062_IRQ_VDD_WARN,
/* IRQ C */
DA9062_IRQ_GPI0,
DA9062_IRQ_GPI1,
DA9062_IRQ_GPI2,
DA9062_IRQ_GPI3,
DA9062_IRQ_GPI4,
DA9062_NUM_IRQ,
};
struct da9062 {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq;
enum da9062_compatible_types chip_type;
};
#endif /* __MFD_DA9062_CORE_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9062/registers.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/da9063/core.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Definitions for DA9063 MFD driver
*
* Copyright 2012 Dialog Semiconductor Ltd.
*
* Author: Michal Hajduk, Dialog Semiconductor
* Author: Krystian Garbaciak, Dialog Semiconductor
*/
#ifndef __MFD_DA9063_CORE_H__
#define __MFD_DA9063_CORE_H__
#include <linux/interrupt.h>
#include <linux/mfd/da9063/registers.h>
/* DA9063 modules */
#define DA9063_DRVNAME_CORE "da9063-core"
#define DA9063_DRVNAME_REGULATORS "da9063-regulators"
#define DA9063_DRVNAME_LEDS "da9063-leds"
#define DA9063_DRVNAME_WATCHDOG "da9063-watchdog"
#define DA9063_DRVNAME_HWMON "da9063-hwmon"
#define DA9063_DRVNAME_ONKEY "da9063-onkey"
#define DA9063_DRVNAME_RTC "da9063-rtc"
#define DA9063_DRVNAME_VIBRATION "da9063-vibration"
#define PMIC_CHIP_ID_DA9063 0x61
enum da9063_type {
PMIC_TYPE_DA9063 = 0,
PMIC_TYPE_DA9063L,
};
enum da9063_variant_codes {
PMIC_DA9063_AD = 0x3,
PMIC_DA9063_BB = 0x5,
PMIC_DA9063_CA = 0x6,
PMIC_DA9063_DA = 0x7,
PMIC_DA9063_EA = 0x8,
};
/* Interrupts */
enum da9063_irqs {
DA9063_IRQ_ONKEY = 0,
DA9063_IRQ_ALARM,
DA9063_IRQ_TICK,
DA9063_IRQ_ADC_RDY,
DA9063_IRQ_SEQ_RDY,
DA9063_IRQ_WAKE,
DA9063_IRQ_TEMP,
DA9063_IRQ_COMP_1V2,
DA9063_IRQ_LDO_LIM,
DA9063_IRQ_REG_UVOV,
DA9063_IRQ_DVC_RDY,
DA9063_IRQ_VDD_MON,
DA9063_IRQ_WARN,
DA9063_IRQ_GPI0,
DA9063_IRQ_GPI1,
DA9063_IRQ_GPI2,
DA9063_IRQ_GPI3,
DA9063_IRQ_GPI4,
DA9063_IRQ_GPI5,
DA9063_IRQ_GPI6,
DA9063_IRQ_GPI7,
DA9063_IRQ_GPI8,
DA9063_IRQ_GPI9,
DA9063_IRQ_GPI10,
DA9063_IRQ_GPI11,
DA9063_IRQ_GPI12,
DA9063_IRQ_GPI13,
DA9063_IRQ_GPI14,
DA9063_IRQ_GPI15,
};
struct da9063 {
/* Device */
struct device *dev;
enum da9063_type type;
unsigned char variant_code;
unsigned int flags;
bool use_sw_pm;
/* Control interface */
struct regmap *regmap;
/* Interrupts */
int chip_irq;
unsigned int irq_base;
struct regmap_irq_chip_data *regmap_irq;
};
int da9063_device_init(struct da9063 *da9063, unsigned int irq);
int da9063_irq_init(struct da9063 *da9063);
#endif /* __MFD_DA9063_CORE_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9063/registers.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/da9150/core.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* DA9150 MFD Driver - Core Data
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
*/
#ifndef __DA9150_CORE_H
#define __DA9150_CORE_H
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
/* I2C address paging */
#define DA9150_REG_PAGE_SHIFT 8
#define DA9150_REG_PAGE_MASK 0xFF
/* IRQs */
#define DA9150_NUM_IRQ_REGS 4
#define DA9150_IRQ_VBUS 0
#define DA9150_IRQ_CHG 1
#define DA9150_IRQ_TCLASS 2
#define DA9150_IRQ_TJUNC 3
#define DA9150_IRQ_VFAULT 4
#define DA9150_IRQ_CONF 5
#define DA9150_IRQ_DAT 6
#define DA9150_IRQ_DTYPE 7
#define DA9150_IRQ_ID 8
#define DA9150_IRQ_ADP 9
#define DA9150_IRQ_SESS_END 10
#define DA9150_IRQ_SESS_VLD 11
#define DA9150_IRQ_FG 12
#define DA9150_IRQ_GP 13
#define DA9150_IRQ_TBAT 14
#define DA9150_IRQ_GPIOA 15
#define DA9150_IRQ_GPIOB 16
#define DA9150_IRQ_GPIOC 17
#define DA9150_IRQ_GPIOD 18
#define DA9150_IRQ_GPADC 19
#define DA9150_IRQ_WKUP 20
/* I2C sub-device address */
#define DA9150_QIF_I2C_ADDR_LSB 0x5
struct da9150_fg_pdata {
u32 update_interval; /* msecs */
u8 warn_soc_lvl; /* % value */
u8 crit_soc_lvl; /* % value */
};
struct da9150_pdata {
int irq_base;
struct da9150_fg_pdata *fg_pdata;
};
struct da9150 {
struct device *dev;
struct regmap *regmap;
struct i2c_client *core_qif;
struct regmap_irq_chip_data *regmap_irq_data;
int irq;
int irq_base;
};
/* Device I/O - Query Interface for FG and standard register access */
void da9150_read_qif(struct da9150 *da9150, u8 addr, int count, u8 *buf);
void da9150_write_qif(struct da9150 *da9150, u8 addr, int count, const u8 *buf);
u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
#endif /* __DA9150_CORE_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/da9150/registers.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/davinci_voicecodec.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* DaVinci Voice Codec Core Interface for TI platforms
*
* Copyright (C) 2010 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*/
#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
#define __LINUX_MFD_DAVINCI_VOICECODEC_H_
#include <linux/bits.h>
#include <linux/mfd/core.h>
#include <linux/types.h>
struct clk;
struct device;
struct platform_device;
struct regmap;
/*
* Register values.
*/
#define DAVINCI_VC_PID 0x00
#define DAVINCI_VC_CTRL 0x04
#define DAVINCI_VC_INTEN 0x08
#define DAVINCI_VC_INTSTATUS 0x0c
#define DAVINCI_VC_INTCLR 0x10
#define DAVINCI_VC_EMUL_CTRL 0x14
#define DAVINCI_VC_RFIFO 0x20
#define DAVINCI_VC_WFIFO 0x24
#define DAVINCI_VC_FIFOSTAT 0x28
#define DAVINCI_VC_TST_CTRL 0x2C
#define DAVINCI_VC_REG05 0x94
#define DAVINCI_VC_REG09 0xA4
#define DAVINCI_VC_REG12 0xB0
/* DAVINCI_VC_CTRL bit fields */
#define DAVINCI_VC_CTRL_MASK 0x5500
#define DAVINCI_VC_CTRL_RSTADC BIT(0)
#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
/* DAVINCI_VC_INT bit fields */
#define DAVINCI_VC_INT_MASK 0x3F
#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
/* DAVINCI_VC_REG05 bit fields */
#define DAVINCI_VC_REG05_PGA_GAIN 0x07
/* DAVINCI_VC_REG09 bit fields */
#define DAVINCI_VC_REG09_MUTE 0x40
#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
/* DAVINCI_VC_REG12 bit fields */
#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
#define DAVINCI_VC_CELLS 2
enum davinci_vc_cells {
DAVINCI_VC_VCIF_CELL,
DAVINCI_VC_CQ93VC_CELL,
};
struct davinci_vcif {
struct platform_device *pdev;
u32 dma_tx_channel;
u32 dma_rx_channel;
dma_addr_t dma_tx_addr;
dma_addr_t dma_rx_addr;
};
struct davinci_vc {
/* Device data */
struct device *dev;
struct platform_device *pdev;
struct clk *clk;
/* Memory resources */
void __iomem *base;
struct regmap *regmap;
/* MFD cells */
struct mfd_cell cells[DAVINCI_VC_CELLS];
/* Client devices */
struct davinci_vcif davinci_vcif;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/db8500-prcmu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) STMicroelectronics 2009
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* PRCMU f/w APIs
*/
#ifndef __MFD_DB8500_PRCMU_H
#define __MFD_DB8500_PRCMU_H
#include <linux/interrupt.h>
#include <linux/bitops.h>
/*
* Registers
*/
#define DB8500_PRCM_LINE_VALUE 0x170
#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
#define DB8500_PRCM_DSI_SW_RESET 0x324
#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
/**
* enum state - ON/OFF state definition
* @OFF: State is ON
* @ON: State is OFF
*
*/
enum state {
OFF = 0x0,
ON = 0x1,
};
/**
* enum ret_state - general purpose On/Off/Retention states
*
*/
enum ret_state {
OFFST = 0,
ONST = 1,
RETST = 2
};
/**
* enum clk_arm - ARM Cortex A9 clock schemes
* @A9_OFF:
* @A9_BOOT:
* @A9_OPPT1:
* @A9_OPPT2:
* @A9_EXTCLK:
*/
enum clk_arm {
A9_OFF,
A9_BOOT,
A9_OPPT1,
A9_OPPT2,
A9_EXTCLK
};
/**
* enum clk_gen - GEN#0/GEN#1 clock schemes
* @GEN_OFF:
* @GEN_BOOT:
* @GEN_OPPT1:
*/
enum clk_gen {
GEN_OFF,
GEN_BOOT,
GEN_OPPT1,
};
/* some information between arm and xp70 */
/**
* enum romcode_write - Romcode message written by A9 AND read by XP70
* @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
* @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
* romcode. The xp70 will go into self-reset
*/
enum romcode_write {
RDY_2_DS = 0x09,
RDY_2_XP70_RST = 0x10
};
/**
* enum romcode_read - Romcode message written by XP70 and read by A9
* @INIT: Init value when romcode field is not used
* @FS_2_DS: Value set when power state is going from ApExecute to
* ApDeepSleep
* @END_DS: Value set when ApDeepSleep power state is reached coming from
* ApExecute state
* @DS_TO_FS: Value set when power state is going from ApDeepSleep to
* ApExecute
* @END_FS: Value set when ApExecute power state is reached coming from
* ApDeepSleep state
* @SWR: Value set when power state is going to ApReset
* @END_SWR: Value set when the xp70 finished executing ApReset actions and
* waits for romcode acknowledgment to go to self-reset
*/
enum romcode_read {
INIT = 0x00,
FS_2_DS = 0x0A,
END_DS = 0x0B,
DS_TO_FS = 0x0C,
END_FS = 0x0D,
SWR = 0x0E,
END_SWR = 0x0F
};
/**
* enum ap_pwrst - current power states defined in PRCMU firmware
* @NO_PWRST: Current power state init
* @AP_BOOT: Current power state is apBoot
* @AP_EXECUTE: Current power state is apExecute
* @AP_DEEP_SLEEP: Current power state is apDeepSleep
* @AP_SLEEP: Current power state is apSleep
* @AP_IDLE: Current power state is apIdle
* @AP_RESET: Current power state is apReset
*/
enum ap_pwrst {
NO_PWRST = 0x00,
AP_BOOT = 0x01,
AP_EXECUTE = 0x02,
AP_DEEP_SLEEP = 0x03,
AP_SLEEP = 0x04,
AP_IDLE = 0x05,
AP_RESET = 0x06
};
/**
* enum ap_pwrst_trans - Transition states defined in PRCMU firmware
* @NO_TRANSITION: No power state transition
* @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
* @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
* @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
* @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
* ApDeepSleep
* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
*/
enum ap_pwrst_trans {
PRCMU_AP_NO_CHANGE = 0x00,
APEXECUTE_TO_APSLEEP = 0x01,
APIDLE_TO_APSLEEP = 0x02, /* To be removed */
PRCMU_AP_SLEEP = 0x01,
APBOOT_TO_APEXECUTE = 0x03,
APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
PRCMU_AP_DEEP_SLEEP = 0x04,
APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
PRCMU_AP_IDLE = 0x05,
PRCMU_AP_DEEP_IDLE = 0x07,
};
/**
* enum hw_acc_state - State definition for hardware accelerator
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
* @HW_OFF: The hardware accelerator must be switched off
* @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
* internal RAM in retention
* @HW_ON: The hwa hardware accelerator hwa must be switched on
*
* NOTE! Deprecated, to be removed when all users switched over to use the
* regulator API.
*/
enum hw_acc_state {
HW_NO_CHANGE = 0x00,
HW_OFF = 0x01,
HW_OFF_RAMRET = 0x02,
HW_ON = 0x04
};
/**
* enum mbox_2_arm_stat - Status messages definition for mbox_arm
* @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
* completed
* @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
* completed
* @SLEEPOK: The apExecute to apSleep state transition has been completed
* @IDLEOK: The apExecute to apIdle state transition has been completed
* @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
* @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
* @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
* @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
* going
* @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
* going
* @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
* been completed
* @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
* @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
* @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
* completed
* @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
* @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
* @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
* completed
* @INIT_STATUS: Status init
*/
enum ap_pwrsttr_status {
BOOT_TO_EXECUTEOK = 0xFF,
DEEPSLEEPOK = 0xFE,
SLEEPOK = 0xFD,
IDLEOK = 0xFC,
SOFTRESETOK = 0xFB,
SOFTRESETGO = 0xFA,
BOOT_TO_EXECUTE = 0xF9,
EXECUTE_TO_DEEPSLEEP = 0xF8,
DEEPSLEEP_TO_EXECUTE = 0xF7,
DEEPSLEEP_TO_EXECUTEOK = 0xF6,
EXECUTE_TO_SLEEP = 0xF5,
SLEEP_TO_EXECUTE = 0xF4,
SLEEP_TO_EXECUTEOK = 0xF3,
EXECUTE_TO_IDLE = 0xF2,
IDLE_TO_EXECUTE = 0xF1,
IDLE_TO_EXECUTEOK = 0xF0,
RDYTODS_RETURNTOEXE = 0xEF,
NORDYTODS_RETURNTOEXE = 0xEE,
EXETOSLEEP_RETURNTOEXE = 0xED,
EXETOIDLE_RETURNTOEXE = 0xEC,
INIT_STATUS = 0xEB,
/*error messages */
INITERROR = 0x00,
PLLARMLOCKP_ER = 0x01,
PLLDDRLOCKP_ER = 0x02,
PLLSOCLOCKP_ER = 0x03,
PLLSOCK1LOCKP_ER = 0x04,
ARMWFI_ER = 0x05,
SYSCLKOK_ER = 0x06,
I2C_NACK_DATA_ER = 0x07,
BOOT_ER = 0x08,
I2C_STATUS_ALWAYS_1 = 0x0A,
I2C_NACK_REG_ADDR_ER = 0x0B,
I2C_NACK_DATA0123_ER = 0x1B,
I2C_NACK_ADDR_ER = 0x1F,
CURAPPWRSTISNOT_BOOT = 0x20,
CURAPPWRSTISNOT_EXECUTE = 0x21,
CURAPPWRSTISNOT_SLEEPMODE = 0x22,
CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
FIFO4500WUISNOT_WUPEVENT = 0x24,
PLL32KLOCKP_ER = 0x29,
DDRDEEPSLEEPOK_ER = 0x2A,
ROMCODEREADY_ER = 0x50,
WUPBEFOREDS = 0x51,
DDRCONFIG_ER = 0x52,
WUPBEFORESLEEP = 0x53,
WUPBEFOREIDLE = 0x54
}; /* earlier called as mbox_2_arm_stat */
/**
* enum dvfs_stat - DVFS status messages definition
* @DVFS_GO: A state transition DVFS is on going
* @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
* @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
* @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
* @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
* NOCHGCLK
* @DVFS_INITSTATUS: Value init
*/
enum dvfs_stat {
DVFS_GO = 0xFF,
DVFS_ARM100OPPOK = 0xFE,
DVFS_ARM50OPPOK = 0xFD,
DVFS_ARMEXTCLKOK = 0xFC,
DVFS_NOCHGTCLKOK = 0xFB,
DVFS_INITSTATUS = 0x00
};
/**
* enum sva_mmdsp_stat - SVA MMDSP status messages
* @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
* @SVA_MMDSP_INIT: Status init
*/
enum sva_mmdsp_stat {
SVA_MMDSP_GO = 0xFF,
SVA_MMDSP_INIT = 0x00
};
/**
* enum sia_mmdsp_stat - SIA MMDSP status messages
* @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
* @SIA_MMDSP_INIT: Status init
*/
enum sia_mmdsp_stat {
SIA_MMDSP_GO = 0xFF,
SIA_MMDSP_INIT = 0x00
};
/**
* enum mbox_to_arm_err - Error messages definition
* @INIT_ERR: Init value
* @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
* @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
* @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
* @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
* @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
* @SYSCLKOK_ERR: The SYSCLK is not available in the given time
* @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
* @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
* @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
* through I2C has not been correctly executed in the given time
* @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
* through I2C has not been correctly executed in the given time
* @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
* I2C has not been correctly executed in the given time
* @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
* has not been correctly executed in the given time
* @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
* not been correctly executed in the given time
* @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
* not been correctly executed in the given time
* @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
* through I2C has not been correctly executed in the given time
* @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
* ApBoot to ApExecute but the power current state is not Apboot
* @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
* transition from ApExecute to others power state but the
* power current state is not ApExecute
* @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
* but the power current state is not ApDeepSleep/ApSleep/ApIdle
* @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
* but the power current state is not correct
* @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
* been correctly executed in the given time
* @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
* been correctly executed in the given time
* @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
* been correctly executed in the given time
* @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
* been correctly executed in the given time
* @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
* been correctly executed in the given time
*/
enum mbox_to_arm_err {
INIT_ERR = 0x00,
PLLARMLOCKP_ERR = 0x01,
PLLDDRLOCKP_ERR = 0x02,
PLLSOC0LOCKP_ERR = 0x03,
PLLSOC1LOCKP_ERR = 0x04,
ARMWFI_ERR = 0x05,
SYSCLKOK_ERR = 0x06,
BOOT_ERR = 0x07,
ROMCODESAVECONTEXT = 0x08,
VARMHIGHSPEEDVALTO_ERR = 0x10,
VARMHIGHSPEEDACCESS_ERR = 0x11,
VARMLOWSPEEDVALTO_ERR = 0x12,
VARMLOWSPEEDACCESS_ERR = 0x13,
VARMRETENTIONVALTO_ERR = 0x14,
VARMRETENTIONACCESS_ERR = 0x15,
VAPEHIGHSPEEDVALTO_ERR = 0x16,
VSAFEHPVALTO_ERR = 0x17,
VMODSEL1VALTO_ERR = 0x18,
VMODSEL2VALTO_ERR = 0x19,
VARMOFFACCESS_ERR = 0x1A,
VAPEOFFACCESS_ERR = 0x1B,
VARMRETACCES_ERR = 0x1C,
CURAPPWRSTISNOTBOOT = 0x20,
CURAPPWRSTISNOTEXECUTE = 0x21,
CURAPPWRSTISNOTSLEEPMODE = 0x22,
CURAPPWRSTISNOTCORRECTDBG = 0x23,
ARMREGU1VALTO_ERR = 0x24,
ARMREGU2VALTO_ERR = 0x25,
VAPEREGUVALTO_ERR = 0x26,
VSMPS3REGUVALTO_ERR = 0x27,
VMODREGUVALTO_ERR = 0x28
};
enum hw_acc {
SVAMMDSP = 0,
SVAPIPE = 1,
SIAMMDSP = 2,
SIAPIPE = 3,
SGA = 4,
B2R2MCDE = 5,
ESRAM12 = 6,
ESRAM34 = 7,
};
enum cs_pwrmgt {
PWRDNCS0 = 0,
WKUPCS0 = 1,
PWRDNCS1 = 2,
WKUPCS1 = 3
};
/* Defs related to autonomous power management */
/**
* enum sia_sva_pwr_policy - Power policy
* @NO_CHGT: No change
* @DSPOFF_HWPOFF:
* @DSPOFFRAMRET_HWPOFF:
* @DSPCLKOFF_HWPOFF:
* @DSPCLKOFF_HWPCLKOFF:
*
*/
enum sia_sva_pwr_policy {
NO_CHGT = 0x0,
DSPOFF_HWPOFF = 0x1,
DSPOFFRAMRET_HWPOFF = 0x2,
DSPCLKOFF_HWPOFF = 0x3,
DSPCLKOFF_HWPCLKOFF = 0x4,
};
/**
* enum auto_enable - Auto Power enable
* @AUTO_OFF:
* @AUTO_ON:
*
*/
enum auto_enable {
AUTO_OFF = 0x0,
AUTO_ON = 0x1,
};
/* End of file previously known as prcmu-fw-defs_v1.h */
/**
* enum prcmu_power_status - results from set_power_state
* @PRCMU_SLEEP_OK: Sleep went ok
* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
* @PRCMU_IDLE_OK: Idle went ok
* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
*
*/
enum prcmu_power_status {
PRCMU_SLEEP_OK = 0xf3,
PRCMU_DEEP_SLEEP_OK = 0xf6,
PRCMU_IDLE_OK = 0xf0,
PRCMU_DEEPIDLE_OK = 0xe3,
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
PRCMU_ARMPENDINGIT_ER = 0x93,
};
/*
* Definitions for autonomous power management configuration.
*/
#define PRCMU_AUTO_PM_OFF 0
#define PRCMU_AUTO_PM_ON 1
#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
enum prcmu_auto_pm_policy {
PRCMU_AUTO_PM_POLICY_NO_CHANGE,
PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
};
/**
* struct prcmu_auto_pm_config - Autonomous power management configuration.
* @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
* @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
*/
struct prcmu_auto_pm_config {
u8 sia_auto_pm_enable;
u8 sia_power_on;
u8 sia_policy;
u8 sva_auto_pm_enable;
u8 sva_power_on;
u8 sva_policy;
};
#ifdef CONFIG_MFD_DB8500_PRCMU
void db8500_prcmu_early_init(void);
int prcmu_set_rc_a2p(enum romcode_write);
enum romcode_read prcmu_get_rc_p2a(void);
enum ap_pwrst prcmu_get_xp70_current_state(void);
bool prcmu_has_arm_maxopp(void);
struct prcmu_fw_version *prcmu_get_fw_version(void);
int prcmu_release_usb_wakeup_state(void);
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle);
bool prcmu_is_auto_pm_enabled(void);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
int prcmu_set_clock_divider(u8 clock, u8 divider);
int db8500_prcmu_config_hotdog(u8 threshold);
int db8500_prcmu_config_hotmon(u8 low, u8 high);
int db8500_prcmu_start_temp_sense(u16 cycles32k);
int db8500_prcmu_stop_temp_sense(void);
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void db8500_prcmu_modem_reset(void);
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int db8500_prcmu_enable_a9wdog(u8 id);
int db8500_prcmu_disable_a9wdog(u8 id);
int db8500_prcmu_kick_a9wdog(u8 id);
int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
u16 db8500_prcmu_get_reset_code(void);
bool db8500_prcmu_is_ac_wake_requested(void);
int db8500_prcmu_set_arm_opp(u8 opp);
int db8500_prcmu_get_arm_opp(void);
int db8500_prcmu_set_ape_opp(u8 opp);
int db8500_prcmu_get_ape_opp(void);
int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
int db8500_prcmu_get_ddr_opp(void);
u32 db8500_prcmu_read(unsigned int reg);
void db8500_prcmu_write(unsigned int reg, u32 value);
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
#else /* !CONFIG_MFD_DB8500_PRCMU */
static inline void db8500_prcmu_early_init(void) {}
static inline int prcmu_set_rc_a2p(enum romcode_write code)
{
return 0;
}
static inline enum romcode_read prcmu_get_rc_p2a(void)
{
return INIT;
}
static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
{
return AP_EXECUTE;
}
static inline bool prcmu_has_arm_maxopp(void)
{
return false;
}
static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
{
return NULL;
}
static inline int db8500_prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
{
return 0;
}
static inline int prcmu_release_usb_wakeup_state(void)
{
return 0;
}
static inline int db8500_prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle)
{
}
static inline bool prcmu_is_auto_pm_enabled(void)
{
return false;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
{
return 0;
}
static inline int db8500_prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int db8500_prcmu_stop_temp_sense(void)
{
return 0;
}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_ac_wake_req(void)
{
return 0;
}
static inline void prcmu_ac_sleep_req(void) {}
static inline void db8500_prcmu_modem_reset(void) {}
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline u8 db8500_prcmu_get_power_state_result(void)
{
return 0;
}
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
static inline u16 db8500_prcmu_get_reset_code(void)
{
return 0;
}
static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return 0;
}
static inline int db8500_prcmu_enable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_disable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_kick_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
{
return 0;
}
static inline bool db8500_prcmu_is_ac_wake_requested(void)
{
return false;
}
static inline int db8500_prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_arm_opp(void)
{
return 0;
}
static inline u32 db8500_prcmu_read(unsigned int reg)
{
return 0;
}
static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
u32 value) {}
#endif /* !CONFIG_MFD_DB8500_PRCMU */
#endif /* __MFD_DB8500_PRCMU_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/dbx500-prcmu.h
+575
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@@ -0,0 +1,575 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST Ericsson SA 2011
*
* STE Ux500 PRCMU API
*/
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>
#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
/* Offset for the firmware version within the TCPM */
#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
PRCMU_WAKEUP_INDEX_RTC,
PRCMU_WAKEUP_INDEX_RTT0,
PRCMU_WAKEUP_INDEX_RTT1,
PRCMU_WAKEUP_INDEX_HSI0,
PRCMU_WAKEUP_INDEX_HSI1,
PRCMU_WAKEUP_INDEX_USB,
PRCMU_WAKEUP_INDEX_ABB,
PRCMU_WAKEUP_INDEX_ABB_FIFO,
PRCMU_WAKEUP_INDEX_ARM,
PRCMU_WAKEUP_INDEX_CD_IRQ,
NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
/* EPOD (power domain) IDs */
/*
* DB8500 EPODs
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
* - EPOD_ID_SGA: power domain for SGA
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
* - NUM_EPOD_ID: number of power domains
*
* TODO: These should be prefixed.
*/
#define EPOD_ID_SVAMMDSP 0
#define EPOD_ID_SVAPIPE 1
#define EPOD_ID_SIAMMDSP 2
#define EPOD_ID_SIAPIPE 3
#define EPOD_ID_SGA 4
#define EPOD_ID_B2R2_MCDE 5
#define EPOD_ID_ESRAM12 6
#define EPOD_ID_ESRAM34 7
#define NUM_EPOD_ID 8
/*
* state definition for EPOD (power domain)
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
* - EPOD_STATE_OFF: The EPOD is switched off
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
* retention
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
* - EPOD_STATE_ON: Same as above, but with clock enabled
*/
#define EPOD_STATE_NO_CHANGE 0x00
#define EPOD_STATE_OFF 0x01
#define EPOD_STATE_RAMRET 0x02
#define EPOD_STATE_ON_CLK_OFF 0x03
#define EPOD_STATE_ON 0x04
/*
* CLKOUT sources
*/
#define PRCMU_CLKSRC_CLK38M 0x00
#define PRCMU_CLKSRC_ACLK 0x01
#define PRCMU_CLKSRC_SYSCLK 0x02
#define PRCMU_CLKSRC_LCDCLK 0x03
#define PRCMU_CLKSRC_SDMMCCLK 0x04
#define PRCMU_CLKSRC_TVCLK 0x05
#define PRCMU_CLKSRC_TIMCLK 0x06
#define PRCMU_CLKSRC_CLK009 0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
#define PRCMU_CLKSRC_I2CCLK 0x41
#define PRCMU_CLKSRC_MSP02CLK 0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
#define PRCMU_CLKSRC_HSIRXCLK 0x44
#define PRCMU_CLKSRC_HSITXCLK 0x45
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
#define PRCMU_CLKSRC_HDMICLK 0x47
/**
* enum prcmu_wdog_id - PRCMU watchdog IDs
* @PRCMU_WDOG_ALL: use all timers
* @PRCMU_WDOG_CPU1: use first CPU timer only
* @PRCMU_WDOG_CPU2: use second CPU timer conly
*/
enum prcmu_wdog_id {
PRCMU_WDOG_ALL = 0x00,
PRCMU_WDOG_CPU1 = 0x01,
PRCMU_WDOG_CPU2 = 0x02,
};
/**
* enum ape_opp - APE OPP states definition
* @APE_OPP_INIT:
* @APE_NO_CHANGE: The APE operating point is unchanged
* @APE_100_OPP: The new APE operating point is ape100opp
* @APE_50_OPP: 50%
* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
*/
enum ape_opp {
APE_OPP_INIT = 0x00,
APE_NO_CHANGE = 0x01,
APE_100_OPP = 0x02,
APE_50_OPP = 0x03,
APE_50_PARTLY_25_OPP = 0xFF,
};
/**
* enum arm_opp - ARM OPP states definition
* @ARM_OPP_INIT:
* @ARM_NO_CHANGE: The ARM operating point is unchanged
* @ARM_100_OPP: The new ARM operating point is arm100opp
* @ARM_50_OPP: The new ARM operating point is arm50opp
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
* @ARM_EXTCLK: The new ARM operating point is armExtClk
*/
enum arm_opp {
ARM_OPP_INIT = 0x00,
ARM_NO_CHANGE = 0x01,
ARM_100_OPP = 0x02,
ARM_50_OPP = 0x03,
ARM_MAX_OPP = 0x04,
ARM_MAX_FREQ100OPP = 0x05,
ARM_EXTCLK = 0x07
};
/**
* enum ddr_opp - DDR OPP states definition
* @DDR_100_OPP: The new DDR operating point is ddr100opp
* @DDR_50_OPP: The new DDR operating point is ddr50opp
* @DDR_25_OPP: The new DDR operating point is ddr25opp
*/
enum ddr_opp {
DDR_100_OPP = 0x00,
DDR_50_OPP = 0x01,
DDR_25_OPP = 0x02,
};
/*
* Definitions for controlling ESRAM0 in deep sleep.
*/
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
/**
* enum ddr_pwrst - DDR power states definition
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
* @DDR_PWR_STATE_ON:
* @DDR_PWR_STATE_OFFLOWLAT:
* @DDR_PWR_STATE_OFFHIGHLAT:
*/
enum ddr_pwrst {
DDR_PWR_STATE_UNCHANGED = 0x00,
DDR_PWR_STATE_ON = 0x01,
DDR_PWR_STATE_OFFLOWLAT = 0x02,
DDR_PWR_STATE_OFFHIGHLAT = 0x03
};
#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
#define PRCMU_FW_PROJECT_U8500 2
#define PRCMU_FW_PROJECT_U8400 3
#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBB 5
#define PRCMU_FW_PROJECT_U8500_C1 6
#define PRCMU_FW_PROJECT_U8500_C2 7
#define PRCMU_FW_PROJECT_U8500_C3 8
#define PRCMU_FW_PROJECT_U8500_C4 9
#define PRCMU_FW_PROJECT_U9500_MBL 10
#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
#define PRCMU_FW_PROJECT_U8520 13
#define PRCMU_FW_PROJECT_U8420 14
#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
#define PRCMU_FW_PROJECT_A9420 20
/* [32..63] 9540 and derivatives */
#define PRCMU_FW_PROJECT_U9540 32
/* [64..95] 8540 and derivatives */
#define PRCMU_FW_PROJECT_L8540 64
/* [96..126] 8580 and derivatives */
#define PRCMU_FW_PROJECT_L8580 96
#define PRCMU_FW_PROJECT_NAME_LEN 20
struct prcmu_fw_version {
u32 project; /* Notice, project shifted with 8 on ux540 */
u8 api_version;
u8 func_version;
u8 errata;
char project_name[PRCMU_FW_PROJECT_NAME_LEN];
};
#include <linux/mfd/db8500-prcmu.h>
#if defined(CONFIG_UX500_SOC_DB8500)
static inline void __init prcmu_early_init(void)
{
db8500_prcmu_early_init();
}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return db8500_prcmu_set_power_state(state, keep_ulp_clk,
keep_ap_pll);
}
static inline u8 prcmu_get_power_state_result(void)
{
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return db8500_prcmu_set_epod(epod_id, epod_state);
}
static inline void prcmu_enable_wakeups(u32 wakeups)
{
db8500_prcmu_enable_wakeups(wakeups);
}
static inline void prcmu_disable_wakeups(void)
{
prcmu_enable_wakeups(0);
}
static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
db8500_prcmu_config_abb_event_readout(abb_events);
}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
db8500_prcmu_get_abb_event_buffer(buf);
}
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
static inline int prcmu_request_clock(u8 clock, bool enable)
{
return db8500_prcmu_request_clock(clock, enable);
}
unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);
static inline int prcmu_get_ddr_opp(void)
{
return db8500_prcmu_get_ddr_opp();
}
static inline int prcmu_set_arm_opp(u8 opp)
{
return db8500_prcmu_set_arm_opp(opp);
}
static inline int prcmu_get_arm_opp(void)
{
return db8500_prcmu_get_arm_opp();
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return db8500_prcmu_set_ape_opp(opp);
}
static inline int prcmu_get_ape_opp(void)
{
return db8500_prcmu_get_ape_opp();
}
static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
return db8500_prcmu_request_ape_opp_100_voltage(enable);
}
static inline void prcmu_system_reset(u16 reset_code)
{
db8500_prcmu_system_reset(reset_code);
}
static inline u16 prcmu_get_reset_code(void)
{
return db8500_prcmu_get_reset_code();
}
int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
db8500_prcmu_modem_reset();
}
static inline bool prcmu_is_ac_wake_requested(void)
{
return db8500_prcmu_is_ac_wake_requested();
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return db8500_prcmu_config_esram0_deep_sleep(state);
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return db8500_prcmu_config_hotdog(threshold);
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return db8500_prcmu_config_hotmon(low, high);
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return db8500_prcmu_start_temp_sense(cycles32k);
}
static inline int prcmu_stop_temp_sense(void)
{
return db8500_prcmu_stop_temp_sense();
}
static inline u32 prcmu_read(unsigned int reg)
{
return db8500_prcmu_read(reg);
}
static inline void prcmu_write(unsigned int reg, u32 value)
{
db8500_prcmu_write(reg, value);
}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
db8500_prcmu_write_masked(reg, mask, value);
}
static inline int prcmu_enable_a9wdog(u8 id)
{
return db8500_prcmu_enable_a9wdog(id);
}
static inline int prcmu_disable_a9wdog(u8 id)
{
return db8500_prcmu_disable_a9wdog(id);
}
static inline int prcmu_kick_a9wdog(u8 id)
{
return db8500_prcmu_kick_a9wdog(id);
}
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
return db8500_prcmu_load_a9wdog(id, timeout);
}
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else
static inline void prcmu_early_init(void) {}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline void prcmu_enable_wakeups(u32 wakeups) {}
static inline void prcmu_disable_wakeups(void) {}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
u8 size)
{
return -ENOSYS;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline unsigned long prcmu_clock_rate(u8 clock)
{
return 0;
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
return 0;
}
static inline int prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_arm_opp(void)
{
return ARM_100_OPP;
}
static inline int prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_system_reset(u16 reset_code) {}
static inline u16 prcmu_get_reset_code(void)
{
return 0;
}
static inline int prcmu_ac_wake_req(void)
{
return 0;
}
static inline void prcmu_ac_sleep_req(void) {}
static inline void prcmu_modem_reset(void) {}
static inline bool prcmu_is_ac_wake_requested(void)
{
return false;
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
*buf = NULL;
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int prcmu_stop_temp_sense(void)
{
return 0;
}
static inline u32 prcmu_read(unsigned int reg)
{
return 0;
}
static inline void prcmu_write(unsigned int reg, u32 value) {}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
#endif
static inline void prcmu_set(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, bits);
}
static inline void prcmu_clear(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, 0);
}
/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
char *name, s32 value)
{
return 0;
}
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
char *name, s32 new_value)
{
return 0;
}
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}
#endif /* __MACH_PRCMU_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/dln2.h
+104
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@@ -0,0 +1,104 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_USB_DLN2_H
#define __LINUX_USB_DLN2_H
#define DLN2_CMD(cmd, id) ((cmd) | ((id) << 8))
struct dln2_platform_data {
u16 handle; /* sub-driver handle (internally used only) */
u8 port; /* I2C/SPI port */
};
/**
* dln2_event_cb_t - event callback function signature
*
* @pdev - the sub-device that registered this callback
* @echo - the echo header field received in the message
* @data - the data payload
* @len - the data payload length
*
* The callback function is called in interrupt context and the data payload is
* only valid during the call. If the user needs later access of the data, it
* must copy it.
*/
typedef void (*dln2_event_cb_t)(struct platform_device *pdev, u16 echo,
const void *data, int len);
/**
* dl2n_register_event_cb - register a callback function for an event
*
* @pdev - the sub-device that registers the callback
* @event - the event for which to register a callback
* @event_cb - the callback function
*
* @return 0 in case of success, negative value in case of error
*/
int dln2_register_event_cb(struct platform_device *pdev, u16 event,
dln2_event_cb_t event_cb);
/**
* dln2_unregister_event_cb - unregister the callback function for an event
*
* @pdev - the sub-device that registered the callback
* @event - the event for which to register a callback
*/
void dln2_unregister_event_cb(struct platform_device *pdev, u16 event);
/**
* dln2_transfer - issue a DLN2 command and wait for a response and the
* associated data
*
* @pdev - the sub-device which is issuing this transfer
* @cmd - the command to be sent to the device
* @obuf - the buffer to be sent to the device; it can be NULL if the user
* doesn't need to transmit data with this command
* @obuf_len - the size of the buffer to be sent to the device
* @ibuf - any data associated with the response will be copied here; it can be
* NULL if the user doesn't need the response data
* @ibuf_len - must be initialized to the input buffer size; it will be modified
* to indicate the actual data transferred;
*
* @return 0 for success, negative value for errors
*/
int dln2_transfer(struct platform_device *pdev, u16 cmd,
const void *obuf, unsigned obuf_len,
void *ibuf, unsigned *ibuf_len);
/**
* dln2_transfer_rx - variant of @dln2_transfer() where TX buffer is not needed
*
* @pdev - the sub-device which is issuing this transfer
* @cmd - the command to be sent to the device
* @ibuf - any data associated with the response will be copied here; it can be
* NULL if the user doesn't need the response data
* @ibuf_len - must be initialized to the input buffer size; it will be modified
* to indicate the actual data transferred;
*
* @return 0 for success, negative value for errors
*/
static inline int dln2_transfer_rx(struct platform_device *pdev, u16 cmd,
void *ibuf, unsigned *ibuf_len)
{
return dln2_transfer(pdev, cmd, NULL, 0, ibuf, ibuf_len);
}
/**
* dln2_transfer_tx - variant of @dln2_transfer() where RX buffer is not needed
*
* @pdev - the sub-device which is issuing this transfer
* @cmd - the command to be sent to the device
* @obuf - the buffer to be sent to the device; it can be NULL if the
* user doesn't need to transmit data with this command
* @obuf_len - the size of the buffer to be sent to the device
*
* @return 0 for success, negative value for errors
*/
static inline int dln2_transfer_tx(struct platform_device *pdev, u16 cmd,
const void *obuf, unsigned obuf_len)
{
return dln2_transfer(pdev, cmd, obuf, obuf_len, NULL, NULL);
}
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/ezx-pcap.h
+253
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@@ -0,0 +1,253 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
*
* For further information, please see http://wiki.openezx.org/PCAP2
*/
#ifndef EZX_PCAP_H
#define EZX_PCAP_H
struct pcap_subdev {
int id;
const char *name;
void *platform_data;
};
struct pcap_platform_data {
unsigned int irq_base;
unsigned int config;
int gpio;
void (*init) (void *); /* board specific init */
int num_subdevs;
struct pcap_subdev *subdevs;
};
struct pcap_chip;
int ezx_pcap_write(struct pcap_chip *, u8, u32);
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
int pcap_to_irq(struct pcap_chip *, int);
int irq_to_pcap(struct pcap_chip *, int);
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
void pcap_set_ts_bits(struct pcap_chip *, u32);
#define PCAP_SECOND_PORT 1
#define PCAP_CS_AH 2
#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
#define PCAP_REGISTER_READ_OP_BIT 0x00000000
#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
#define PCAP_REGISTER_ADDRESS_SHIFT 26
#define PCAP_REGISTER_NUMBER 32
#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
/* registers accessible by both pcap ports */
#define PCAP_REG_ISR 0x0 /* Interrupt Status */
#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
#define PCAP_REG_PSTAT 0x2 /* Processor Status */
#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
#define PCAP_REG_BATT 0x8 /* Battery Control */
#define PCAP_REG_ADC 0x9 /* AD Control */
#define PCAP_REG_ADR 0xa /* AD Result */
#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
#define PCAP_REG_GP 0x1b /* General Purpose */
#define PCAP_REG_TEST1 0x1c
#define PCAP_REG_TEST2 0x1d
#define PCAP_REG_VENDOR_TEST1 0x1e
#define PCAP_REG_VENDOR_TEST2 0x1f
/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
#define PCAP_REG_PWR 0x13 /* Power Control */
#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
#define PCAP_REG_VENDOR_REV 0x17
#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
/* PCAP2 Interrupts */
#define PCAP_NIRQS 23
#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
#define PCAP_IRQ_TS 1 /* Touch Screen */
#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
#define PCAP_IRQ_WH 3 /* ADC above high limit */
#define PCAP_IRQ_WL 4 /* ADC below low limit */
#define PCAP_IRQ_TODA 5 /* Time of day alarm */
#define PCAP_IRQ_USB4V 6 /* USB above 4V */
#define PCAP_IRQ_ONOFF 7 /* On/Off button */
#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
#define PCAP_IRQ_USB1V 9 /* USB above 1V */
#define PCAP_IRQ_MOBPORT 10
#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
#define PCAP_IRQ_HS 12 /* Headset attach */
#define PCAP_IRQ_ST 13
#define PCAP_IRQ_PC 14 /* Power Cut */
#define PCAP_IRQ_WARM 15
#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
#define PCAP_IRQ_CLK 17
#define PCAP_IRQ_SYSRST 18 /* System Reset */
#define PCAP_IRQ_DUMMY 19
#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
#define PCAP_IRQ_SOFTRESET 21
#define PCAP_IRQ_MNEXB 22
/* voltage regulators */
#define V1 0
#define V2 1
#define V3 2
#define V4 3
#define V5 4
#define V6 5
#define V7 6
#define V8 7
#define V9 8
#define V10 9
#define VAUX1 10
#define VAUX2 11
#define VAUX3 12
#define VAUX4 13
#define VSIM 14
#define VSIM2 15
#define VVIB 16
#define SW1 17
#define SW2 18
#define SW3 19
#define SW1S 20
#define SW2S 21
#define PCAP_BATT_DAC_MASK 0x000000ff
#define PCAP_BATT_DAC_SHIFT 0
#define PCAP_BATT_B_FDBK (1 << 8)
#define PCAP_BATT_EXT_ISENSE (1 << 9)
#define PCAP_BATT_V_COIN_MASK 0x00003c00
#define PCAP_BATT_V_COIN_SHIFT 10
#define PCAP_BATT_I_COIN (1 << 14)
#define PCAP_BATT_COIN_CH_EN (1 << 15)
#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
#define PCAP_BATT_EOL_SEL_SHIFT 17
#define PCAP_BATT_EOL_CMP_EN (1 << 20)
#define PCAP_BATT_BATT_DET_EN (1 << 21)
#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
#define PCAP_ADC_ADEN (1 << 0)
#define PCAP_ADC_RAND (1 << 1)
#define PCAP_ADC_AD_SEL1 (1 << 2)
#define PCAP_ADC_AD_SEL2 (1 << 3)
#define PCAP_ADC_ADA1_MASK 0x00000070
#define PCAP_ADC_ADA1_SHIFT 4
#define PCAP_ADC_ADA2_MASK 0x00000380
#define PCAP_ADC_ADA2_SHIFT 7
#define PCAP_ADC_ATO_MASK 0x00003c00
#define PCAP_ADC_ATO_SHIFT 10
#define PCAP_ADC_ATOX (1 << 14)
#define PCAP_ADC_MTR1 (1 << 15)
#define PCAP_ADC_MTR2 (1 << 16)
#define PCAP_ADC_TS_M_MASK 0x000e0000
#define PCAP_ADC_TS_M_SHIFT 17
#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
#define PCAP_ADC_TS_REFENB (1 << 21)
#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
#define PCAP_ADC_BATT_I_ADC (1 << 23)
#define PCAP_ADC_BANK_0 0
#define PCAP_ADC_BANK_1 1
/* ADC bank 0 */
#define PCAP_ADC_CH_COIN 0
#define PCAP_ADC_CH_BATT 1
#define PCAP_ADC_CH_BPLUS 2
#define PCAP_ADC_CH_MOBPORTB 3
#define PCAP_ADC_CH_TEMPERATURE 4
#define PCAP_ADC_CH_CHARGER_ID 5
#define PCAP_ADC_CH_AD6 6
/* ADC bank 1 */
#define PCAP_ADC_CH_AD7 0
#define PCAP_ADC_CH_AD8 1
#define PCAP_ADC_CH_AD9 2
#define PCAP_ADC_CH_TS_X1 3
#define PCAP_ADC_CH_TS_X2 4
#define PCAP_ADC_CH_TS_Y1 5
#define PCAP_ADC_CH_TS_Y2 6
#define PCAP_ADC_T_NOW 0
#define PCAP_ADC_T_IN_BURST 1
#define PCAP_ADC_T_OUT_BURST 2
#define PCAP_ADC_ATO_IN_BURST 6
#define PCAP_ADC_ATO_OUT_BURST 0
#define PCAP_ADC_TS_M_XY 1
#define PCAP_ADC_TS_M_PRESSURE 2
#define PCAP_ADC_TS_M_PLATE_X 3
#define PCAP_ADC_TS_M_PLATE_Y 4
#define PCAP_ADC_TS_M_STANDBY 5
#define PCAP_ADC_TS_M_NONTS 6
#define PCAP_ADR_ADD1_MASK 0x000003ff
#define PCAP_ADR_ADD1_SHIFT 0
#define PCAP_ADR_ADD2_MASK 0x000ffc00
#define PCAP_ADR_ADD2_SHIFT 10
#define PCAP_ADR_ADINC1 (1 << 20)
#define PCAP_ADR_ADINC2 (1 << 21)
#define PCAP_ADR_ASC (1 << 22)
#define PCAP_ADR_ONESHOT (1 << 23)
#define PCAP_BUSCTRL_FSENB (1 << 0)
#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
#define PCAP_BUSCTRL_USB_PU (1 << 2)
#define PCAP_BUSCTRL_USB_PD (1 << 3)
#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
#define PCAP_BUSCTRL_USB_PS (1 << 5)
#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
#define PCAP_BUSCTRL_CURRLIM (1 << 8)
#define PCAP_BUSCTRL_RS232ENB (1 << 9)
#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
#define PCAP_BUSCTRL_USB_PDM (1 << 12)
#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
/* leds */
#define PCAP_LED0 0
#define PCAP_LED1 1
#define PCAP_BL0 2
#define PCAP_BL1 3
#define PCAP_LED_3MA 0
#define PCAP_LED_4MA 1
#define PCAP_LED_5MA 2
#define PCAP_LED_9MA 3
#define PCAP_LED_T_MASK 0xf
#define PCAP_LED_C_MASK 0x3
#define PCAP_BL_MASK 0x1f
#define PCAP_BL0_SHIFT 0
#define PCAP_LED0_EN (1 << 5)
#define PCAP_LED1_EN (1 << 6)
#define PCAP_LED0_T_SHIFT 7
#define PCAP_LED1_T_SHIFT 11
#define PCAP_LED0_C_SHIFT 15
#define PCAP_LED1_C_SHIFT 17
#define PCAP_BL1_SHIFT 20
/* RTC */
#define PCAP_RTC_DAY_MASK 0x3fff
#define PCAP_RTC_TOD_MASK 0xffff
#define PCAP_RTC_PC_MASK 0x7
#define SEC_PER_DAY 86400
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/gsc.h
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Gateworks Corporation
*/
#ifndef __LINUX_MFD_GSC_H_
#define __LINUX_MFD_GSC_H_
#include <linux/regmap.h>
/* Device Addresses */
#define GSC_MISC 0x20
#define GSC_UPDATE 0x21
#define GSC_GPIO 0x23
#define GSC_HWMON 0x29
#define GSC_EEPROM0 0x50
#define GSC_EEPROM1 0x51
#define GSC_EEPROM2 0x52
#define GSC_EEPROM3 0x53
#define GSC_RTC 0x68
/* Register offsets */
enum {
GSC_CTRL_0 = 0x00,
GSC_CTRL_1 = 0x01,
GSC_TIME = 0x02,
GSC_TIME_ADD = 0x06,
GSC_IRQ_STATUS = 0x0A,
GSC_IRQ_ENABLE = 0x0B,
GSC_FW_CRC = 0x0C,
GSC_FW_VER = 0x0E,
GSC_WP = 0x0F,
};
/* Bit definitions */
#define GSC_CTRL_0_PB_HARD_RESET 0
#define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1
#define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2
#define GSC_CTRL_0_PB_BOOT_ALTERNATE 3
#define GSC_CTRL_0_PERFORM_CRC 4
#define GSC_CTRL_0_TAMPER_DETECT 5
#define GSC_CTRL_0_SWITCH_HOLD 6
#define GSC_CTRL_1_SLEEP_ENABLE 0
#define GSC_CTRL_1_SLEEP_ACTIVATE 1
#define GSC_CTRL_1_SLEEP_ADD 2
#define GSC_CTRL_1_SLEEP_NOWAKEPB 3
#define GSC_CTRL_1_WDT_TIME 4
#define GSC_CTRL_1_WDT_ENABLE 5
#define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6
#define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7
#define GSC_IRQ_PB 0
#define GSC_IRQ_KEY_ERASED 1
#define GSC_IRQ_EEPROM_WP 2
#define GSC_IRQ_RESV 3
#define GSC_IRQ_GPIO 4
#define GSC_IRQ_TAMPER 5
#define GSC_IRQ_WDT_TIMEOUT 6
#define GSC_IRQ_SWITCH_HOLD 7
int gsc_read(void *context, unsigned int reg, unsigned int *val);
int gsc_write(void *context, unsigned int reg, unsigned int val);
struct gsc_dev {
struct device *dev;
struct i2c_client *i2c; /* 0x20: interrupt controller, WDT */
struct i2c_client *i2c_hwmon; /* 0x29: hwmon, fan controller */
struct regmap *regmap;
unsigned int fwver;
unsigned short fwcrc;
};
#endif /* __LINUX_MFD_GSC_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/hi6421-pmic.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header file for device driver Hi6421 PMIC
*
* Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd.
* http://www.hisilicon.com
* Copyright (c) <2013-2014> Linaro Ltd.
* https://www.linaro.org
*
* Author: Guodong Xu <guodong.xu@linaro.org>
*/
#ifndef __HI6421_PMIC_H
#define __HI6421_PMIC_H
/* Hi6421 registers are mapped to memory bus in 4 bytes stride */
#define HI6421_REG_TO_BUS_ADDR(x) (x << 2)
/* Hi6421 maximum register number */
#define HI6421_REG_MAX 0xFF
/* Hi6421 OCP (over current protection) and DEB (debounce) control register */
#define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51)
#define HI6421_OCP_DEB_SEL_MASK 0x0C
#define HI6421_OCP_DEB_SEL_8MS 0x00
#define HI6421_OCP_DEB_SEL_16MS 0x04
#define HI6421_OCP_DEB_SEL_32MS 0x08
#define HI6421_OCP_DEB_SEL_64MS 0x0C
#define HI6421_OCP_EN_DEBOUNCE_MASK 0x02
#define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02
#define HI6421_OCP_AUTO_STOP_MASK 0x01
#define HI6421_OCP_AUTO_STOP_ENABLE 0x01
struct hi6421_pmic {
struct regmap *regmap;
};
enum hi6421_type {
HI6421 = 0,
HI6421_V530,
};
#endif /* __HI6421_PMIC_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/hi655x-pmic.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Device driver for regulators in hi655x IC
*
* Copyright (c) 2016 HiSilicon Ltd.
*
* Authors:
* Chen Feng <puck.chen@hisilicon.com>
* Fei Wang <w.f@huawei.com>
*/
#ifndef __HI655X_PMIC_H
#define __HI655X_PMIC_H
#include <linux/gpio/consumer.h>
/* Hi655x registers are mapped to memory bus in 4 bytes stride */
#define HI655X_STRIDE 4
#define HI655X_BUS_ADDR(x) ((x) << 2)
#define HI655X_BITS 8
#define HI655X_NR_IRQ 32
#define HI655X_IRQ_STAT_BASE (0x003 << 2)
#define HI655X_IRQ_MASK_BASE (0x007 << 2)
#define HI655X_ANA_IRQM_BASE (0x1b5 << 2)
#define HI655X_IRQ_ARRAY 4
#define HI655X_IRQ_MASK 0xFF
#define HI655X_IRQ_CLR 0xFF
#define HI655X_VER_REG 0x00
#define PMU_VER_START 0x10
#define PMU_VER_END 0x38
#define RESERVE_INT 7
#define PWRON_D20R_INT 6
#define PWRON_D20F_INT 5
#define PWRON_D4SR_INT 4
#define VSYS_6P0_D200UR_INT 3
#define VSYS_UV_D3R_INT 2
#define VSYS_2P5_R_INT 1
#define OTMP_D1R_INT 0
#define RESERVE_INT_MASK BIT(RESERVE_INT)
#define PWRON_D20R_INT_MASK BIT(PWRON_D20R_INT)
#define PWRON_D20F_INT_MASK BIT(PWRON_D20F_INT)
#define PWRON_D4SR_INT_MASK BIT(PWRON_D4SR_INT)
#define VSYS_6P0_D200UR_INT_MASK BIT(VSYS_6P0_D200UR_INT)
#define VSYS_UV_D3R_INT_MASK BIT(VSYS_UV_D3R_INT)
#define VSYS_2P5_R_INT_MASK BIT(VSYS_2P5_R_INT)
#define OTMP_D1R_INT_MASK BIT(OTMP_D1R_INT)
struct hi655x_pmic {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *gpio;
unsigned int ver;
struct regmap_irq_chip_data *irq_data;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/idt82p33_reg.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
*
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
*/
#ifndef HAVE_IDT82P33_REG
#define HAVE_IDT82P33_REG
#define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
/* Register address */
#define DPLL1_TOD_CNFG 0x134
#define DPLL2_TOD_CNFG 0x1B4
#define DPLL1_TOD_STS 0x10B
#define DPLL2_TOD_STS 0x18B
#define DPLL1_TOD_TRIGGER 0x115
#define DPLL2_TOD_TRIGGER 0x195
#define DPLL1_OPERATING_MODE_CNFG 0x120
#define DPLL2_OPERATING_MODE_CNFG 0x1A0
#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
#define DPLL1_PHASE_OFFSET_CNFG 0x143
#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
#define DPLL1_SYNC_EDGE_CNFG 0x140
#define DPLL2_SYNC_EDGE_CNFG 0x1C0
#define DPLL1_INPUT_MODE_CNFG 0x116
#define DPLL2_INPUT_MODE_CNFG 0x196
#define DPLL1_OPERATING_STS 0x102
#define DPLL2_OPERATING_STS 0x182
#define DPLL1_CURRENT_FREQ_STS 0x103
#define DPLL2_CURRENT_FREQ_STS 0x183
#define REG_SOFT_RESET 0X381
#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
/* Register bit definitions */
#define SYNC_TOD BIT(1)
#define PH_OFFSET_EN BIT(7)
#define SQUELCH_ENABLE BIT(5)
/* Bit definitions for the DPLL_MODE register */
#define PLL_MODE_SHIFT (0)
#define PLL_MODE_MASK (0x1F)
#define COMBO_MODE_EN BIT(5)
#define COMBO_MODE_SHIFT (6)
#define COMBO_MODE_MASK (0x3)
/* Bit definitions for DPLL_OPERATING_STS register */
#define OPERATING_STS_MASK (0x7)
#define OPERATING_STS_SHIFT (0x0)
/* Bit definitions for DPLL_TOD_TRIGGER register */
#define READ_TRIGGER_MASK (0xF)
#define READ_TRIGGER_SHIFT (0x0)
#define WRITE_TRIGGER_MASK (0xF0)
#define WRITE_TRIGGER_SHIFT (0x4)
/* Bit definitions for REG_SOFT_RESET register */
#define SOFT_RESET_EN BIT(7)
enum pll_mode {
PLL_MODE_MIN = 0,
PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
PLL_MODE_FORCE_FREERUN = 1,
PLL_MODE_FORCE_HOLDOVER = 2,
PLL_MODE_FORCE_LOCKED = 4,
PLL_MODE_FORCE_PRE_LOCKED2 = 5,
PLL_MODE_FORCE_PRE_LOCKED = 6,
PLL_MODE_FORCE_LOST_PHASE = 7,
PLL_MODE_DCO = 10,
PLL_MODE_WPH = 18,
PLL_MODE_MAX = PLL_MODE_WPH,
};
enum hw_tod_trig_sel {
HW_TOD_TRIG_SEL_MIN = 0,
HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
HW_TOD_TRIG_SEL_SYNC_SEL = 1,
HW_TOD_TRIG_SEL_IN12 = 2,
HW_TOD_TRIG_SEL_IN13 = 3,
HW_TOD_TRIG_SEL_IN14 = 4,
HW_TOD_TRIG_SEL_TOD_PPS = 5,
HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
};
/** @brief Enumerated type listing DPLL operational modes */
enum dpll_state {
DPLL_STATE_FREERUN = 1,
DPLL_STATE_HOLDOVER = 2,
DPLL_STATE_LOCKED = 4,
DPLL_STATE_PRELOCKED2 = 5,
DPLL_STATE_PRELOCKED = 6,
DPLL_STATE_LOSTPHASE = 7,
DPLL_STATE_MAX
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/idt8a340_reg.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
*
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
*/
#ifndef HAVE_IDT8A340_REG
#define HAVE_IDT8A340_REG
#define PAGE_ADDR_BASE 0x0000
#define PAGE_ADDR 0x00fc
#define HW_REVISION 0x8180
#define REV_ID 0x007a
#define HW_DPLL_0 (0x8a00)
#define HW_DPLL_1 (0x8b00)
#define HW_DPLL_2 (0x8c00)
#define HW_DPLL_3 (0x8d00)
#define HW_DPLL_4 (0x8e00)
#define HW_DPLL_5 (0x8f00)
#define HW_DPLL_6 (0x9000)
#define HW_DPLL_7 (0x9100)
#define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
#define HW_DPLL_TOD_CTRL_1 (0x089)
#define HW_DPLL_TOD_CTRL_2 (0x08A)
#define HW_DPLL_TOD_OVR__0 (0x098)
#define HW_DPLL_TOD_OUT_0__0 (0x0B0)
#define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
#define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
#define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
#define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
#define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
#define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
#define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
#define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
#define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
#define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
#define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
#define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
#define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
#define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
#define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
#define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
#define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
#define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
#define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
#define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
#define SYNCTRL1_MASTER_SYNC_RST BIT(7)
#define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
#define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
#define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
#define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
#define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
#define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
#define HW_Q8_CTRL_SPARE (0xa7d4)
#define HW_Q11_CTRL_SPARE (0xa7ec)
/*
* Select FOD5 as sync_trigger for Q8 divider.
* Transition from logic zero to one
* sets trigger to sync Q8 divider.
*
* Unused when FOD4 is driving Q8 divider (normal operation).
*/
#define Q9_TO_Q8_SYNC_TRIG BIT(1)
/*
* Enable FOD5 as driver for clock and sync for Q8 divider.
* Enable fanout buffer for FOD5.
*
* Unused when FOD4 is driving Q8 divider (normal operation).
*/
#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
/*
* Select FOD6 as sync_trigger for Q11 divider.
* Transition from logic zero to one
* sets trigger to sync Q11 divider.
*
* Unused when FOD7 is driving Q11 divider (normal operation).
*/
#define Q10_TO_Q11_SYNC_TRIG BIT(1)
/*
* Enable FOD6 as driver for clock and sync for Q11 divider.
* Enable fanout buffer for FOD6.
*
* Unused when FOD7 is driving Q11 divider (normal operation).
*/
#define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
#define RESET_CTRL 0xc000
#define SM_RESET 0x0012
#define SM_RESET_V520 0x0013
#define SM_RESET_CMD 0x5A
#define GENERAL_STATUS 0xc014
#define BOOT_STATUS 0x0000
#define HW_REV_ID 0x000A
#define BOND_ID 0x000B
#define HW_CSR_ID 0x000C
#define HW_IRQ_ID 0x000E
#define MAJ_REL 0x0010
#define MIN_REL 0x0011
#define HOTFIX_REL 0x0012
#define PIPELINE_ID 0x0014
#define BUILD_ID 0x0018
#define JTAG_DEVICE_ID 0x001c
#define PRODUCT_ID 0x001e
#define OTP_SCSR_CONFIG_SELECT 0x0022
#define STATUS 0xc03c
#define DPLL0_STATUS 0x0018
#define DPLL1_STATUS 0x0019
#define DPLL2_STATUS 0x001a
#define DPLL3_STATUS 0x001b
#define DPLL4_STATUS 0x001c
#define DPLL5_STATUS 0x001d
#define DPLL6_STATUS 0x001e
#define DPLL7_STATUS 0x001f
#define DPLL_SYS_STATUS 0x0020
#define DPLL_SYS_APLL_STATUS 0x0021
#define DPLL0_FILTER_STATUS 0x0044
#define DPLL1_FILTER_STATUS 0x004c
#define DPLL2_FILTER_STATUS 0x0054
#define DPLL3_FILTER_STATUS 0x005c
#define DPLL4_FILTER_STATUS 0x0064
#define DPLL5_FILTER_STATUS 0x006c
#define DPLL6_FILTER_STATUS 0x0074
#define DPLL7_FILTER_STATUS 0x007c
#define DPLLSYS_FILTER_STATUS 0x0084
#define USER_GPIO0_TO_7_STATUS 0x008a
#define USER_GPIO8_TO_15_STATUS 0x008b
#define GPIO_USER_CONTROL 0xc160
#define GPIO0_TO_7_OUT 0x0000
#define GPIO8_TO_15_OUT 0x0001
#define GPIO0_TO_7_OUT_V520 0x0002
#define GPIO8_TO_15_OUT_V520 0x0003
#define STICKY_STATUS_CLEAR 0xc164
#define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
#define ALERT_CFG 0xc188
#define SYS_DPLL_XO 0xc194
#define SYS_APLL 0xc19c
#define INPUT_0 0xc1b0
#define INPUT_1 0xc1c0
#define INPUT_2 0xc1d0
#define INPUT_3 0xc200
#define INPUT_4 0xc210
#define INPUT_5 0xc220
#define INPUT_6 0xc230
#define INPUT_7 0xc240
#define INPUT_8 0xc250
#define INPUT_9 0xc260
#define INPUT_10 0xc280
#define INPUT_11 0xc290
#define INPUT_12 0xc2a0
#define INPUT_13 0xc2b0
#define INPUT_14 0xc2c0
#define INPUT_15 0xc2d0
#define REF_MON_0 0xc2e0
#define REF_MON_1 0xc2ec
#define REF_MON_2 0xc300
#define REF_MON_3 0xc30c
#define REF_MON_4 0xc318
#define REF_MON_5 0xc324
#define REF_MON_6 0xc330
#define REF_MON_7 0xc33c
#define REF_MON_8 0xc348
#define REF_MON_9 0xc354
#define REF_MON_10 0xc360
#define REF_MON_11 0xc36c
#define REF_MON_12 0xc380
#define REF_MON_13 0xc38c
#define REF_MON_14 0xc398
#define REF_MON_15 0xc3a4
#define DPLL_0 0xc3b0
#define DPLL_CTRL_REG_0 0x0002
#define DPLL_CTRL_REG_1 0x0003
#define DPLL_CTRL_REG_2 0x0004
#define DPLL_TOD_SYNC_CFG 0x0031
#define DPLL_COMBO_SLAVE_CFG_0 0x0032
#define DPLL_COMBO_SLAVE_CFG_1 0x0033
#define DPLL_SLAVE_REF_CFG 0x0034
#define DPLL_REF_MODE 0x0035
#define DPLL_PHASE_MEASUREMENT_CFG 0x0036
#define DPLL_MODE 0x0037
#define DPLL_MODE_V520 0x003B
#define DPLL_1 0xc400
#define DPLL_2 0xc438
#define DPLL_2_V520 0xc43c
#define DPLL_3 0xc480
#define DPLL_4 0xc4b8
#define DPLL_4_V520 0xc4bc
#define DPLL_5 0xc500
#define DPLL_6 0xc538
#define DPLL_6_V520 0xc53c
#define DPLL_7 0xc580
#define SYS_DPLL 0xc5b8
#define SYS_DPLL_V520 0xc5bc
#define DPLL_CTRL_0 0xc600
#define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
#define DPLL_CTRL_DPLL_FOD_FREQ 0x001c
#define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
#define DPLL_CTRL_1 0xc63c
#define DPLL_CTRL_2 0xc680
#define DPLL_CTRL_3 0xc6bc
#define DPLL_CTRL_4 0xc700
#define DPLL_CTRL_5 0xc73c
#define DPLL_CTRL_6 0xc780
#define DPLL_CTRL_7 0xc7bc
#define SYS_DPLL_CTRL 0xc800
#define DPLL_PHASE_0 0xc818
/* Signed 42-bit FFO in units of 2^(-53) */
#define DPLL_WR_PHASE 0x0000
#define DPLL_PHASE_1 0xc81c
#define DPLL_PHASE_2 0xc820
#define DPLL_PHASE_3 0xc824
#define DPLL_PHASE_4 0xc828
#define DPLL_PHASE_5 0xc82c
#define DPLL_PHASE_6 0xc830
#define DPLL_PHASE_7 0xc834
#define DPLL_FREQ_0 0xc838
/* Signed 42-bit FFO in units of 2^(-53) */
#define DPLL_WR_FREQ 0x0000
#define DPLL_FREQ_1 0xc840
#define DPLL_FREQ_2 0xc848
#define DPLL_FREQ_3 0xc850
#define DPLL_FREQ_4 0xc858
#define DPLL_FREQ_5 0xc860
#define DPLL_FREQ_6 0xc868
#define DPLL_FREQ_7 0xc870
#define DPLL_PHASE_PULL_IN_0 0xc880
#define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
#define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
#define PULL_IN_CTRL 0x0007
#define DPLL_PHASE_PULL_IN_1 0xc888
#define DPLL_PHASE_PULL_IN_2 0xc890
#define DPLL_PHASE_PULL_IN_3 0xc898
#define DPLL_PHASE_PULL_IN_4 0xc8a0
#define DPLL_PHASE_PULL_IN_5 0xc8a8
#define DPLL_PHASE_PULL_IN_6 0xc8b0
#define DPLL_PHASE_PULL_IN_7 0xc8b8
#define GPIO_CFG 0xc8c0
#define GPIO_CFG_GBL 0x0000
#define GPIO_0 0xc8c2
#define GPIO_DCO_INC_DEC 0x0000
#define GPIO_OUT_CTRL_0 0x0001
#define GPIO_OUT_CTRL_1 0x0002
#define GPIO_TOD_TRIG 0x0003
#define GPIO_DPLL_INDICATOR 0x0004
#define GPIO_LOS_INDICATOR 0x0005
#define GPIO_REF_INPUT_DSQ_0 0x0006
#define GPIO_REF_INPUT_DSQ_1 0x0007
#define GPIO_REF_INPUT_DSQ_2 0x0008
#define GPIO_REF_INPUT_DSQ_3 0x0009
#define GPIO_MAN_CLK_SEL_0 0x000a
#define GPIO_MAN_CLK_SEL_1 0x000b
#define GPIO_MAN_CLK_SEL_2 0x000c
#define GPIO_SLAVE 0x000d
#define GPIO_ALERT_OUT_CFG 0x000e
#define GPIO_TOD_NOTIFICATION_CFG 0x000f
#define GPIO_CTRL 0x0010
#define GPIO_CTRL_V520 0x0011
#define GPIO_1 0xc8d4
#define GPIO_2 0xc8e6
#define GPIO_3 0xc900
#define GPIO_4 0xc912
#define GPIO_5 0xc924
#define GPIO_6 0xc936
#define GPIO_7 0xc948
#define GPIO_8 0xc95a
#define GPIO_9 0xc980
#define GPIO_10 0xc992
#define GPIO_11 0xc9a4
#define GPIO_12 0xc9b6
#define GPIO_13 0xc9c8
#define GPIO_14 0xc9da
#define GPIO_15 0xca00
#define OUT_DIV_MUX 0xca12
#define OUTPUT_0 0xca14
#define OUTPUT_0_V520 0xca20
/* FOD frequency output divider value */
#define OUT_DIV 0x0000
#define OUT_DUTY_CYCLE_HIGH 0x0004
#define OUT_CTRL_0 0x0008
#define OUT_CTRL_1 0x0009
/* Phase adjustment in FOD cycles */
#define OUT_PHASE_ADJ 0x000c
#define OUTPUT_1 0xca24
#define OUTPUT_1_V520 0xca30
#define OUTPUT_2 0xca34
#define OUTPUT_2_V520 0xca40
#define OUTPUT_3 0xca44
#define OUTPUT_3_V520 0xca50
#define OUTPUT_4 0xca54
#define OUTPUT_4_V520 0xca60
#define OUTPUT_5 0xca64
#define OUTPUT_5_V520 0xca80
#define OUTPUT_6 0xca80
#define OUTPUT_6_V520 0xca90
#define OUTPUT_7 0xca90
#define OUTPUT_7_V520 0xcaa0
#define OUTPUT_8 0xcaa0
#define OUTPUT_8_V520 0xcab0
#define OUTPUT_9 0xcab0
#define OUTPUT_9_V520 0xcac0
#define OUTPUT_10 0xcac0
#define OUTPUT_10_V520 0xcad0
#define OUTPUT_11 0xcad0
#define OUTPUT_11_V520 0xcae0
#define SERIAL 0xcae0
#define SERIAL_V520 0xcaf0
#define PWM_ENCODER_0 0xcb00
#define PWM_ENCODER_1 0xcb08
#define PWM_ENCODER_2 0xcb10
#define PWM_ENCODER_3 0xcb18
#define PWM_ENCODER_4 0xcb20
#define PWM_ENCODER_5 0xcb28
#define PWM_ENCODER_6 0xcb30
#define PWM_ENCODER_7 0xcb38
#define PWM_DECODER_0 0xcb40
#define PWM_DECODER_1 0xcb48
#define PWM_DECODER_1_V520 0xcb4a
#define PWM_DECODER_2 0xcb50
#define PWM_DECODER_2_V520 0xcb54
#define PWM_DECODER_3 0xcb58
#define PWM_DECODER_3_V520 0xcb5e
#define PWM_DECODER_4 0xcb60
#define PWM_DECODER_4_V520 0xcb68
#define PWM_DECODER_5 0xcb68
#define PWM_DECODER_5_V520 0xcb80
#define PWM_DECODER_6 0xcb70
#define PWM_DECODER_6_V520 0xcb8a
#define PWM_DECODER_7 0xcb80
#define PWM_DECODER_7_V520 0xcb94
#define PWM_DECODER_8 0xcb88
#define PWM_DECODER_8_V520 0xcb9e
#define PWM_DECODER_9 0xcb90
#define PWM_DECODER_9_V520 0xcba8
#define PWM_DECODER_10 0xcb98
#define PWM_DECODER_10_V520 0xcbb2
#define PWM_DECODER_11 0xcba0
#define PWM_DECODER_11_V520 0xcbbc
#define PWM_DECODER_12 0xcba8
#define PWM_DECODER_12_V520 0xcbc6
#define PWM_DECODER_13 0xcbb0
#define PWM_DECODER_13_V520 0xcbd0
#define PWM_DECODER_14 0xcbb8
#define PWM_DECODER_14_V520 0xcbda
#define PWM_DECODER_15 0xcbc0
#define PWM_DECODER_15_V520 0xcbe4
#define PWM_USER_DATA 0xcbc8
#define PWM_USER_DATA_V520 0xcbf0
#define TOD_0 0xcbcc
#define TOD_0_V520 0xcc00
/* Enable TOD counter, output channel sync and even-PPS mode */
#define TOD_CFG 0x0000
#define TOD_CFG_V520 0x0001
#define TOD_1 0xcbce
#define TOD_1_V520 0xcc02
#define TOD_2 0xcbd0
#define TOD_2_V520 0xcc04
#define TOD_3 0xcbd2
#define TOD_3_V520 0xcc06
#define TOD_WRITE_0 0xcc00
#define TOD_WRITE_0_V520 0xcc10
/* 8-bit subns, 32-bit ns, 48-bit seconds */
#define TOD_WRITE 0x0000
/* Counter increments after TOD write is completed */
#define TOD_WRITE_COUNTER 0x000c
/* TOD write trigger configuration */
#define TOD_WRITE_SELECT_CFG_0 0x000d
/* TOD write trigger selection */
#define TOD_WRITE_CMD 0x000f
#define TOD_WRITE_1 0xcc10
#define TOD_WRITE_1_V520 0xcc20
#define TOD_WRITE_2 0xcc20
#define TOD_WRITE_2_V520 0xcc30
#define TOD_WRITE_3 0xcc30
#define TOD_WRITE_3_V520 0xcc40
#define TOD_READ_PRIMARY_0 0xcc40
#define TOD_READ_PRIMARY_0_V520 0xcc50
/* 8-bit subns, 32-bit ns, 48-bit seconds */
#define TOD_READ_PRIMARY_BASE 0x0000
/* Counter increments after TOD write is completed */
#define TOD_READ_PRIMARY_COUNTER 0x000b
/* Read trigger configuration */
#define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
/* Read trigger selection */
#define TOD_READ_PRIMARY_CMD 0x000e
#define TOD_READ_PRIMARY_CMD_V520 0x000f
#define TOD_READ_PRIMARY_1 0xcc50
#define TOD_READ_PRIMARY_1_V520 0xcc60
#define TOD_READ_PRIMARY_2 0xcc60
#define TOD_READ_PRIMARY_2_V520 0xcc80
#define TOD_READ_PRIMARY_3 0xcc80
#define TOD_READ_PRIMARY_3_V520 0xcc90
#define TOD_READ_SECONDARY_0 0xcc90
#define TOD_READ_SECONDARY_0_V520 0xcca0
/* 8-bit subns, 32-bit ns, 48-bit seconds */
#define TOD_READ_SECONDARY_BASE 0x0000
/* Counter increments after TOD write is completed */
#define TOD_READ_SECONDARY_COUNTER 0x000b
/* Read trigger configuration */
#define TOD_READ_SECONDARY_SEL_CFG_0 0x000c
/* Read trigger selection */
#define TOD_READ_SECONDARY_CMD 0x000e
#define TOD_READ_SECONDARY_CMD_V520 0x000f
#define TOD_READ_SECONDARY_1 0xcca0
#define TOD_READ_SECONDARY_1_V520 0xccb0
#define TOD_READ_SECONDARY_2 0xccb0
#define TOD_READ_SECONDARY_2_V520 0xccc0
#define TOD_READ_SECONDARY_3 0xccc0
#define TOD_READ_SECONDARY_3_V520 0xccd0
#define OUTPUT_TDC_CFG 0xccd0
#define OUTPUT_TDC_CFG_V520 0xcce0
#define OUTPUT_TDC_0 0xcd00
#define OUTPUT_TDC_1 0xcd08
#define OUTPUT_TDC_2 0xcd10
#define OUTPUT_TDC_3 0xcd18
#define INPUT_TDC 0xcd20
#define SCRATCH 0xcf50
#define SCRATCH_V520 0xcf4c
#define EEPROM 0xcf68
#define EEPROM_V520 0xcf64
#define OTP 0xcf70
#define BYTE 0xcf80
/* Bit definitions for the MAJ_REL register */
#define MAJOR_SHIFT (1)
#define MAJOR_MASK (0x7f)
#define PR_BUILD BIT(0)
/* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
#define GPIO0_LEVEL BIT(0)
#define GPIO1_LEVEL BIT(1)
#define GPIO2_LEVEL BIT(2)
#define GPIO3_LEVEL BIT(3)
#define GPIO4_LEVEL BIT(4)
#define GPIO5_LEVEL BIT(5)
#define GPIO6_LEVEL BIT(6)
#define GPIO7_LEVEL BIT(7)
/* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
#define GPIO8_LEVEL BIT(0)
#define GPIO9_LEVEL BIT(1)
#define GPIO10_LEVEL BIT(2)
#define GPIO11_LEVEL BIT(3)
#define GPIO12_LEVEL BIT(4)
#define GPIO13_LEVEL BIT(5)
#define GPIO14_LEVEL BIT(6)
#define GPIO15_LEVEL BIT(7)
/* Bit definitions for the GPIO0_TO_7_OUT register */
#define GPIO0_DRIVE_LEVEL BIT(0)
#define GPIO1_DRIVE_LEVEL BIT(1)
#define GPIO2_DRIVE_LEVEL BIT(2)
#define GPIO3_DRIVE_LEVEL BIT(3)
#define GPIO4_DRIVE_LEVEL BIT(4)
#define GPIO5_DRIVE_LEVEL BIT(5)
#define GPIO6_DRIVE_LEVEL BIT(6)
#define GPIO7_DRIVE_LEVEL BIT(7)
/* Bit definitions for the GPIO8_TO_15_OUT register */
#define GPIO8_DRIVE_LEVEL BIT(0)
#define GPIO9_DRIVE_LEVEL BIT(1)
#define GPIO10_DRIVE_LEVEL BIT(2)
#define GPIO11_DRIVE_LEVEL BIT(3)
#define GPIO12_DRIVE_LEVEL BIT(4)
#define GPIO13_DRIVE_LEVEL BIT(5)
#define GPIO14_DRIVE_LEVEL BIT(6)
#define GPIO15_DRIVE_LEVEL BIT(7)
/* Bit definitions for the DPLL_TOD_SYNC_CFG register */
#define TOD_SYNC_SOURCE_SHIFT (1)
#define TOD_SYNC_SOURCE_MASK (0x3)
#define TOD_SYNC_EN BIT(0)
/* Bit definitions for the DPLL_MODE register */
#define WRITE_TIMER_MODE BIT(6)
#define PLL_MODE_SHIFT (3)
#define PLL_MODE_MASK (0x7)
#define STATE_MODE_SHIFT (0)
#define STATE_MODE_MASK (0x7)
/* Bit definitions for the DPLL_MANU_REF_CFG register */
#define MANUAL_REFERENCE_SHIFT (0)
#define MANUAL_REFERENCE_MASK (0x1f)
/* Bit definitions for the GPIO_CFG_GBL register */
#define SUPPLY_MODE_SHIFT (0)
#define SUPPLY_MODE_MASK (0x3)
/* Bit definitions for the GPIO_DCO_INC_DEC register */
#define INCDEC_DPLL_INDEX_SHIFT (0)
#define INCDEC_DPLL_INDEX_MASK (0x7)
/* Bit definitions for the GPIO_OUT_CTRL_0 register */
#define CTRL_OUT_0 BIT(0)
#define CTRL_OUT_1 BIT(1)
#define CTRL_OUT_2 BIT(2)
#define CTRL_OUT_3 BIT(3)
#define CTRL_OUT_4 BIT(4)
#define CTRL_OUT_5 BIT(5)
#define CTRL_OUT_6 BIT(6)
#define CTRL_OUT_7 BIT(7)
/* Bit definitions for the GPIO_OUT_CTRL_1 register */
#define CTRL_OUT_8 BIT(0)
#define CTRL_OUT_9 BIT(1)
#define CTRL_OUT_10 BIT(2)
#define CTRL_OUT_11 BIT(3)
#define CTRL_OUT_12 BIT(4)
#define CTRL_OUT_13 BIT(5)
#define CTRL_OUT_14 BIT(6)
#define CTRL_OUT_15 BIT(7)
/* Bit definitions for the GPIO_TOD_TRIG register */
#define TOD_TRIG_0 BIT(0)
#define TOD_TRIG_1 BIT(1)
#define TOD_TRIG_2 BIT(2)
#define TOD_TRIG_3 BIT(3)
/* Bit definitions for the GPIO_DPLL_INDICATOR register */
#define IND_DPLL_INDEX_SHIFT (0)
#define IND_DPLL_INDEX_MASK (0x7)
/* Bit definitions for the GPIO_LOS_INDICATOR register */
#define REFMON_INDEX_SHIFT (0)
#define REFMON_INDEX_MASK (0xf)
/* Active level of LOS indicator, 0=low 1=high */
#define ACTIVE_LEVEL BIT(4)
/* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
#define DSQ_INP_0 BIT(0)
#define DSQ_INP_1 BIT(1)
#define DSQ_INP_2 BIT(2)
#define DSQ_INP_3 BIT(3)
#define DSQ_INP_4 BIT(4)
#define DSQ_INP_5 BIT(5)
#define DSQ_INP_6 BIT(6)
#define DSQ_INP_7 BIT(7)
/* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
#define DSQ_INP_8 BIT(0)
#define DSQ_INP_9 BIT(1)
#define DSQ_INP_10 BIT(2)
#define DSQ_INP_11 BIT(3)
#define DSQ_INP_12 BIT(4)
#define DSQ_INP_13 BIT(5)
#define DSQ_INP_14 BIT(6)
#define DSQ_INP_15 BIT(7)
/* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
#define DSQ_DPLL_0 BIT(0)
#define DSQ_DPLL_1 BIT(1)
#define DSQ_DPLL_2 BIT(2)
#define DSQ_DPLL_3 BIT(3)
#define DSQ_DPLL_4 BIT(4)
#define DSQ_DPLL_5 BIT(5)
#define DSQ_DPLL_6 BIT(6)
#define DSQ_DPLL_7 BIT(7)
/* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
#define DSQ_DPLL_SYS BIT(0)
#define GPIO_DSQ_LEVEL BIT(1)
/* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
#define DPLL_TOD_SHIFT (0)
#define DPLL_TOD_MASK (0x3)
#define TOD_READ_SECONDARY BIT(2)
#define GPIO_ASSERT_LEVEL BIT(3)
/* Bit definitions for the GPIO_CTRL register */
#define GPIO_FUNCTION_EN BIT(0)
#define GPIO_CMOS_OD_MODE BIT(1)
#define GPIO_CONTROL_DIR BIT(2)
#define GPIO_PU_PD_MODE BIT(3)
#define GPIO_FUNCTION_SHIFT (4)
#define GPIO_FUNCTION_MASK (0xf)
/* Bit definitions for the OUT_CTRL_1 register */
#define OUT_SYNC_DISABLE BIT(7)
#define SQUELCH_VALUE BIT(6)
#define SQUELCH_DISABLE BIT(5)
#define PAD_VDDO_SHIFT (2)
#define PAD_VDDO_MASK (0x7)
#define PAD_CMOSDRV_SHIFT (0)
#define PAD_CMOSDRV_MASK (0x3)
/* Bit definitions for the TOD_CFG register */
#define TOD_EVEN_PPS_MODE BIT(2)
#define TOD_OUT_SYNC_ENABLE BIT(1)
#define TOD_ENABLE BIT(0)
/* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
#define WR_PWM_DECODER_INDEX_SHIFT (4)
#define WR_PWM_DECODER_INDEX_MASK (0xf)
#define WR_REF_INDEX_SHIFT (0)
#define WR_REF_INDEX_MASK (0xf)
/* Bit definitions for the TOD_WRITE_CMD register */
#define TOD_WRITE_SELECTION_SHIFT (0)
#define TOD_WRITE_SELECTION_MASK (0xf)
/* 4.8.7 */
#define TOD_WRITE_TYPE_SHIFT (4)
#define TOD_WRITE_TYPE_MASK (0x3)
/* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
#define RD_PWM_DECODER_INDEX_SHIFT (4)
#define RD_PWM_DECODER_INDEX_MASK (0xf)
#define RD_REF_INDEX_SHIFT (0)
#define RD_REF_INDEX_MASK (0xf)
/* Bit definitions for the TOD_READ_PRIMARY_CMD register */
#define TOD_READ_TRIGGER_MODE BIT(4)
#define TOD_READ_TRIGGER_SHIFT (0)
#define TOD_READ_TRIGGER_MASK (0xf)
/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
#define COMBO_MASTER_HOLD BIT(0)
/* Bit definitions for DPLL_SYS_STATUS register */
#define DPLL_SYS_STATE_MASK (0xf)
/* Bit definitions for SYS_APLL_STATUS register */
#define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0)
#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0
#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1
/* Bit definitions for the DPLL0_STATUS register */
#define DPLL_STATE_MASK (0xf)
#define DPLL_STATE_SHIFT (0x0)
/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
enum pll_mode {
PLL_MODE_MIN = 0,
PLL_MODE_PLL = PLL_MODE_MIN,
PLL_MODE_WRITE_PHASE = 1,
PLL_MODE_WRITE_FREQUENCY = 2,
PLL_MODE_GPIO_INC_DEC = 3,
PLL_MODE_SYNTHESIS = 4,
PLL_MODE_PHASE_MEASUREMENT = 5,
PLL_MODE_DISABLED = 6,
PLL_MODE_MAX = PLL_MODE_DISABLED,
};
/* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */
enum manual_reference {
MANU_REF_MIN = 0,
MANU_REF_CLK0 = MANU_REF_MIN,
MANU_REF_CLK1,
MANU_REF_CLK2,
MANU_REF_CLK3,
MANU_REF_CLK4,
MANU_REF_CLK5,
MANU_REF_CLK6,
MANU_REF_CLK7,
MANU_REF_CLK8,
MANU_REF_CLK9,
MANU_REF_CLK10,
MANU_REF_CLK11,
MANU_REF_CLK12,
MANU_REF_CLK13,
MANU_REF_CLK14,
MANU_REF_CLK15,
MANU_REF_WRITE_PHASE,
MANU_REF_WRITE_FREQUENCY,
MANU_REF_XO_DPLL,
MANU_REF_MAX = MANU_REF_XO_DPLL,
};
enum hw_tod_write_trig_sel {
HW_TOD_WR_TRIG_SEL_MIN = 0,
HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
HW_TOD_WR_TRIG_SEL_RESERVED = 1,
HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
HW_TOD_WR_TRIG_SEL_GPIO = 5,
HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
};
enum scsr_read_trig_sel {
/* CANCEL CURRENT TOD READ; MODULE BECOMES IDLE - NO TRIGGER OCCURS */
SCSR_TOD_READ_TRIG_SEL_DISABLE = 0,
/* TRIGGER IMMEDIATELY */
SCSR_TOD_READ_TRIG_SEL_IMMEDIATE = 1,
/* TRIGGER ON RISING EDGE OF INTERNAL TOD PPS SIGNAL */
SCSR_TOD_READ_TRIG_SEL_TODPPS = 2,
/* TRGGER ON RISING EDGE OF SELECTED REFERENCE INPUT */
SCSR_TOD_READ_TRIG_SEL_REFCLK = 3,
/* TRIGGER ON RISING EDGE OF SELECTED PWM DECODER 1PPS OUTPUT */
SCSR_TOD_READ_TRIG_SEL_PWMPPS = 4,
SCSR_TOD_READ_TRIG_SEL_RESERVED = 5,
/* TRIGGER WHEN WRITE FREQUENCY EVENT OCCURS */
SCSR_TOD_READ_TRIG_SEL_WRITEFREQUENCYEVENT = 6,
/* TRIGGER ON SELECTED GPIO */
SCSR_TOD_READ_TRIG_SEL_GPIO = 7,
SCSR_TOD_READ_TRIG_SEL_MAX = SCSR_TOD_READ_TRIG_SEL_GPIO,
};
/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
enum dpll_state {
DPLL_STATE_MIN = 0,
DPLL_STATE_FREERUN = DPLL_STATE_MIN,
DPLL_STATE_LOCKACQ = 1,
DPLL_STATE_LOCKREC = 2,
DPLL_STATE_LOCKED = 3,
DPLL_STATE_HOLDOVER = 4,
DPLL_STATE_OPEN_LOOP = 5,
DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
};
/* 4.8.7 only */
enum scsr_tod_write_trig_sel {
SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
};
/* 4.8.7 only */
enum scsr_tod_write_type_sel {
SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/idtRC38xxx_reg.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Register Map - Based on PolarBear_CSRs.RevA.xlsx (2023-04-21)
*
* Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company.
*/
#ifndef MFD_IDTRC38XXX_REG
#define MFD_IDTRC38XXX_REG
/* GLOBAL */
#define SOFT_RESET_CTRL (0x15) /* Specific to FC3W */
#define MISC_CTRL (0x14) /* Specific to FC3A */
#define APLL_REINIT BIT(1)
#define APLL_REINIT_VFC3A BIT(2)
#define DEVICE_ID (0x2)
#define DEVICE_ID_MASK (0x1000) /* Bit 12 is 1 if FC3W and 0 if FC3A */
#define DEVICE_ID_SHIFT (12)
/* FOD */
#define FOD_0 (0x300)
#define FOD_0_VFC3A (0x400)
#define FOD_1 (0x340)
#define FOD_1_VFC3A (0x440)
#define FOD_2 (0x380)
#define FOD_2_VFC3A (0x480)
/* TDCAPLL */
#define TDC_CTRL (0x44a) /* Specific to FC3W */
#define TDC_ENABLE_CTRL (0x169) /* Specific to FC3A */
#define TDC_DAC_CAL_CTRL (0x16a) /* Specific to FC3A */
#define TDC_EN BIT(0)
#define TDC_DAC_RECAL_REQ BIT(1)
#define TDC_DAC_RECAL_REQ_VFC3A BIT(0)
#define TDC_FB_DIV_INT_CNFG (0x442)
#define TDC_FB_DIV_INT_CNFG_VFC3A (0x162)
#define TDC_FB_DIV_INT_MASK GENMASK(7, 0)
#define TDC_REF_DIV_CNFG (0x443)
#define TDC_REF_DIV_CNFG_VFC3A (0x163)
#define TDC_REF_DIV_CONFIG_MASK GENMASK(2, 0)
/* TIME SYNC CHANNEL */
#define TIME_CLOCK_SRC (0xa01) /* Specific to FC3W */
#define TIME_CLOCK_COUNT (0xa00) /* Specific to FC3W */
#define TIME_CLOCK_COUNT_MASK GENMASK(5, 0)
#define SUB_SYNC_GEN_CNFG (0xa04)
#define TOD_COUNTER_READ_REQ (0xa5f)
#define TOD_COUNTER_READ_REQ_VFC3A (0x6df)
#define TOD_SYNC_LOAD_VAL_CTRL (0xa10)
#define TOD_SYNC_LOAD_VAL_CTRL_VFC3A (0x690)
#define SYNC_COUNTER_MASK GENMASK_ULL(51, 0)
#define SUB_SYNC_COUNTER_MASK GENMASK(30, 0)
#define TOD_SYNC_LOAD_REQ_CTRL (0xa21)
#define TOD_SYNC_LOAD_REQ_CTRL_VFC3A (0x6a1)
#define SYNC_LOAD_ENABLE BIT(1)
#define SUB_SYNC_LOAD_ENABLE BIT(0)
#define SYNC_LOAD_REQ BIT(0)
#define LPF_MODE_CNFG (0xa80)
#define LPF_MODE_CNFG_VFC3A (0x700)
enum lpf_mode {
LPF_DISABLED = 0,
LPF_WP = 1,
LPF_HOLDOVER = 2,
LPF_WF = 3,
LPF_INVALID = 4
};
#define LPF_CTRL (0xa98)
#define LPF_CTRL_VFC3A (0x718)
#define LPF_EN BIT(0)
#define LPF_BW_CNFG (0xa81)
#define LPF_BW_SHIFT GENMASK(7, 3)
#define LPF_BW_MULT GENMASK(2, 0)
#define LPF_BW_SHIFT_DEFAULT (0xb)
#define LPF_BW_MULT_DEFAULT (0x0)
#define LPF_BW_SHIFT_1PPS (0x5)
#define LPF_WR_PHASE_CTRL (0xaa8)
#define LPF_WR_PHASE_CTRL_VFC3A (0x728)
#define LPF_WR_FREQ_CTRL (0xab0)
#define LPF_WR_FREQ_CTRL_VFC3A (0x730)
#define TIME_CLOCK_TDC_FANOUT_CNFG (0xB00)
#define TIME_SYNC_TO_TDC_EN BIT(0)
#define SIG1_MUX_SEL_MASK GENMASK(7, 4)
#define SIG2_MUX_SEL_MASK GENMASK(11, 8)
enum tdc_mux_sel {
REF0 = 0,
REF1 = 1,
REF2 = 2,
REF3 = 3,
REF_CLK5 = 4,
REF_CLK6 = 5,
DPLL_FB_TO_TDC = 6,
DPLL_FB_DIVIDED_TO_TDC = 7,
TIME_CLK_DIVIDED = 8,
TIME_SYNC = 9,
};
#define TIME_CLOCK_MEAS_CNFG (0xB04)
#define TDC_MEAS_MODE BIT(0)
enum tdc_meas_mode {
CONTINUOUS = 0,
ONE_SHOT = 1,
MEAS_MODE_INVALID = 2,
};
#define TIME_CLOCK_MEAS_DIV_CNFG (0xB08)
#define TIME_REF_DIV_MASK GENMASK(29, 24)
#define TIME_CLOCK_MEAS_CTRL (0xB10)
#define TDC_MEAS_EN BIT(0)
#define TDC_MEAS_START BIT(1)
#define TDC_FIFO_READ_REQ (0xB2F)
#define TDC_FIFO_READ (0xB30)
#define COARSE_MEAS_MASK GENMASK_ULL(39, 13)
#define FINE_MEAS_MASK GENMASK(12, 0)
#define TDC_FIFO_CTRL (0xB12)
#define FIFO_CLEAR BIT(0)
#define TDC_FIFO_STS (0xB38)
#define FIFO_FULL BIT(1)
#define FIFO_EMPTY BIT(0)
#define TDC_FIFO_EVENT (0xB39)
#define FIFO_OVERRUN BIT(1)
/* DPLL */
#define MAX_REFERENCE_INDEX (3)
#define MAX_NUM_REF_PRIORITY (4)
#define MAX_DPLL_INDEX (2)
#define DPLL_STS (0x580)
#define DPLL_STS_VFC3A (0x571)
#define DPLL_STATE_STS_MASK (0x70)
#define DPLL_STATE_STS_SHIFT (4)
#define DPLL_REF_SEL_STS_MASK (0x6)
#define DPLL_REF_SEL_STS_SHIFT (1)
#define DPLL_REF_PRIORITY_CNFG (0x502)
#define DPLL_REFX_PRIORITY_DISABLE_MASK (0xf)
#define DPLL_REF0_PRIORITY_ENABLE_AND_SET_MASK (0x31)
#define DPLL_REF1_PRIORITY_ENABLE_AND_SET_MASK (0xc2)
#define DPLL_REF2_PRIORITY_ENABLE_AND_SET_MASK (0x304)
#define DPLL_REF3_PRIORITY_ENABLE_AND_SET_MASK (0xc08)
#define DPLL_REF0_PRIORITY_SHIFT (4)
#define DPLL_REF1_PRIORITY_SHIFT (6)
#define DPLL_REF2_PRIORITY_SHIFT (8)
#define DPLL_REF3_PRIORITY_SHIFT (10)
enum dpll_state {
DPLL_STATE_MIN = 0,
DPLL_STATE_FREERUN = DPLL_STATE_MIN,
DPLL_STATE_LOCKED = 1,
DPLL_STATE_HOLDOVER = 2,
DPLL_STATE_WRITE_FREQUENCY = 3,
DPLL_STATE_ACQUIRE = 4,
DPLL_STATE_HITLESS_SWITCH = 5,
DPLL_STATE_MAX = DPLL_STATE_HITLESS_SWITCH
};
/* REFMON */
#define LOSMON_STS_0 (0x81e)
#define LOSMON_STS_0_VFC3A (0x18e)
#define LOSMON_STS_1 (0x82e)
#define LOSMON_STS_1_VFC3A (0x19e)
#define LOSMON_STS_2 (0x83e)
#define LOSMON_STS_2_VFC3A (0x1ae)
#define LOSMON_STS_3 (0x84e)
#define LOSMON_STS_3_VFC3A (0x1be)
#define LOS_STS_MASK (0x1)
#define FREQMON_STS_0 (0x874)
#define FREQMON_STS_0_VFC3A (0x1d4)
#define FREQMON_STS_1 (0x894)
#define FREQMON_STS_1_VFC3A (0x1f4)
#define FREQMON_STS_2 (0x8b4)
#define FREQMON_STS_2_VFC3A (0x214)
#define FREQMON_STS_3 (0x8d4)
#define FREQMON_STS_3_VFC3A (0x234)
#define FREQ_FAIL_STS_SHIFT (31)
/* Firmware interface */
#define TIME_CLK_FREQ_ADDR (0xffa0)
#define XTAL_FREQ_ADDR (0xffa1)
/*
* Return register address and field mask based on passed in firmware version
*/
#define IDTFC3_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
#define IDTFC3_FW_FIELD(FW, VER, FIELD) (((FW) < (VER)) ? (FIELD) : (FIELD##_##VER))
enum fw_version {
V_DEFAULT = 0,
VFC3W = 1,
VFC3A = 2
};
/* XTAL_FREQ_ADDR/TIME_CLK_FREQ_ADDR */
enum {
FREQ_MIN = 0,
FREQ_25M = 1,
FREQ_49_152M = 2,
FREQ_50M = 3,
FREQ_100M = 4,
FREQ_125M = 5,
FREQ_250M = 6,
FREQ_MAX
};
struct idtfc3_hw_param {
u32 xtal_freq;
u32 time_clk_freq;
};
struct idtfc3_fwrc {
u8 hiaddr;
u8 loaddr;
u8 value;
u8 reserved;
} __packed;
static inline void idtfc3_default_hw_param(struct idtfc3_hw_param *hw_param)
{
hw_param->xtal_freq = 49152000;
hw_param->time_clk_freq = 25000000;
}
static inline int idtfc3_set_hw_param(struct idtfc3_hw_param *hw_param,
u16 addr, u8 val)
{
if (addr == XTAL_FREQ_ADDR)
switch (val) {
case FREQ_49_152M:
hw_param->xtal_freq = 49152000;
break;
case FREQ_50M:
hw_param->xtal_freq = 50000000;
break;
default:
return -EINVAL;
}
else if (addr == TIME_CLK_FREQ_ADDR)
switch (val) {
case FREQ_25M:
hw_param->time_clk_freq = 25000000;
break;
case FREQ_50M:
hw_param->time_clk_freq = 50000000;
break;
case FREQ_100M:
hw_param->time_clk_freq = 100000000;
break;
case FREQ_125M:
hw_param->time_clk_freq = 125000000;
break;
case FREQ_250M:
hw_param->time_clk_freq = 250000000;
break;
default:
return -EINVAL;
}
else
return -EFAULT;
return 0;
}
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/imx25-tsadc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
#define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
struct regmap;
struct clk;
struct mx25_tsadc {
struct regmap *regs;
struct irq_domain *domain;
struct clk *clk;
};
#define MX25_TSC_TGCR 0x00
#define MX25_TSC_TGSR 0x04
#define MX25_TSC_TICR 0x08
/* The same register layout for TC and GC queue */
#define MX25_ADCQ_FIFO 0x00
#define MX25_ADCQ_CR 0x04
#define MX25_ADCQ_SR 0x08
#define MX25_ADCQ_MR 0x0c
#define MX25_ADCQ_ITEM_7_0 0x20
#define MX25_ADCQ_ITEM_15_8 0x24
#define MX25_ADCQ_CFG(n) (0x40 + ((n) * 0x4))
#define MX25_ADCQ_MR_MASK 0xffffffff
/* TGCR */
#define MX25_TGCR_PDBTIME(x) ((x) << 25)
#define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)
#define MX25_TGCR_PDBEN BIT(24)
#define MX25_TGCR_PDEN BIT(23)
#define MX25_TGCR_ADCCLKCFG(x) ((x) << 16)
#define MX25_TGCR_GET_ADCCLK(x) (((x) >> 16) & 0x1f)
#define MX25_TGCR_INTREFEN BIT(10)
#define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)
#define MX25_TGCR_POWERMODE_SAVE (1 << 8)
#define MX25_TGCR_POWERMODE_ON (2 << 8)
#define MX25_TGCR_STLC BIT(5)
#define MX25_TGCR_SLPC BIT(4)
#define MX25_TGCR_FUNC_RST BIT(2)
#define MX25_TGCR_TSC_RST BIT(1)
#define MX25_TGCR_CLK_EN BIT(0)
/* TGSR */
#define MX25_TGSR_SLP_INT BIT(2)
#define MX25_TGSR_GCQ_INT BIT(1)
#define MX25_TGSR_TCQ_INT BIT(0)
/* ADCQ_ITEM_* */
#define _MX25_ADCQ_ITEM(item, x) ((x) << ((item) * 4))
#define MX25_ADCQ_ITEM(item, x) ((item) >= 8 ? \
_MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
/* ADCQ_FIFO (TCQFIFO and GCQFIFO) */
#define MX25_ADCQ_FIFO_DATA(x) (((x) >> 4) & 0xfff)
#define MX25_ADCQ_FIFO_ID(x) ((x) & 0xf)
/* ADCQ_CR (TCQR and GCQR) */
#define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19)
#define MX25_ADCQ_CR_PDMSK BIT(18)
#define MX25_ADCQ_CR_FRST BIT(17)
#define MX25_ADCQ_CR_QRST BIT(16)
#define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)
#define MX25_ADCQ_CR_RWAIT(x) ((x) << 12)
#define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)
#define MX25_ADCQ_CR_WMRK(x) ((x) << 8)
#define MX25_ADCQ_CR_LITEMID_MASK (0xf << 4)
#define MX25_ADCQ_CR_LITEMID(x) ((x) << 4)
#define MX25_ADCQ_CR_RPT BIT(3)
#define MX25_ADCQ_CR_FQS BIT(2)
#define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)
#define MX25_ADCQ_CR_QSM_PD 0x1
#define MX25_ADCQ_CR_QSM_FQS 0x2
#define MX25_ADCQ_CR_QSM_FQS_PD 0x3
/* ADCQ_SR (TCQSR and GCQSR) */
#define MX25_ADCQ_SR_FDRY BIT(15)
#define MX25_ADCQ_SR_FULL BIT(14)
#define MX25_ADCQ_SR_EMPT BIT(13)
#define MX25_ADCQ_SR_FDN(x) (((x) >> 8) & 0x1f)
#define MX25_ADCQ_SR_FRR BIT(6)
#define MX25_ADCQ_SR_FUR BIT(5)
#define MX25_ADCQ_SR_FOR BIT(4)
#define MX25_ADCQ_SR_EOQ BIT(1)
#define MX25_ADCQ_SR_PD BIT(0)
/* ADCQ_MR (TCQMR and GCQMR) */
#define MX25_ADCQ_MR_FDRY_DMA BIT(31)
#define MX25_ADCQ_MR_FER_DMA BIT(22)
#define MX25_ADCQ_MR_FUR_DMA BIT(21)
#define MX25_ADCQ_MR_FOR_DMA BIT(20)
#define MX25_ADCQ_MR_EOQ_DMA BIT(17)
#define MX25_ADCQ_MR_PD_DMA BIT(16)
#define MX25_ADCQ_MR_FDRY_IRQ BIT(15)
#define MX25_ADCQ_MR_FER_IRQ BIT(6)
#define MX25_ADCQ_MR_FUR_IRQ BIT(5)
#define MX25_ADCQ_MR_FOR_IRQ BIT(4)
#define MX25_ADCQ_MR_EOQ_IRQ BIT(1)
#define MX25_ADCQ_MR_PD_IRQ BIT(0)
/* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */
#define MX25_ADCQ_CFG_SETTLING_TIME(x) ((x) << 24)
#define MX25_ADCQ_CFG_IGS (1 << 20)
#define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)
#define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16)
#define MX25_ADCQ_CFG_WIPER (1 << 15)
#define MX25_ADCQ_CFG_YNLR (1 << 14)
#define MX25_ADCQ_CFG_YPLL_HIGH (0 << 12)
#define MX25_ADCQ_CFG_YPLL_OFF (1 << 12)
#define MX25_ADCQ_CFG_YPLL_LOW (3 << 12)
#define MX25_ADCQ_CFG_XNUR_HIGH (0 << 10)
#define MX25_ADCQ_CFG_XNUR_OFF (1 << 10)
#define MX25_ADCQ_CFG_XNUR_LOW (3 << 10)
#define MX25_ADCQ_CFG_XPUL_HIGH (0 << 9)
#define MX25_ADCQ_CFG_XPUL_OFF (1 << 9)
#define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7)
#define MX25_ADCQ_CFG_REFP_YP MX25_ADCQ_CFG_REFP(0)
#define MX25_ADCQ_CFG_REFP_XP MX25_ADCQ_CFG_REFP(1)
#define MX25_ADCQ_CFG_REFP_EXT MX25_ADCQ_CFG_REFP(2)
#define MX25_ADCQ_CFG_REFP_INT MX25_ADCQ_CFG_REFP(3)
#define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)
#define MX25_ADCQ_CFG_IN(sel) ((sel) << 4)
#define MX25_ADCQ_CFG_IN_XP MX25_ADCQ_CFG_IN(0)
#define MX25_ADCQ_CFG_IN_YP MX25_ADCQ_CFG_IN(1)
#define MX25_ADCQ_CFG_IN_XN MX25_ADCQ_CFG_IN(2)
#define MX25_ADCQ_CFG_IN_YN MX25_ADCQ_CFG_IN(3)
#define MX25_ADCQ_CFG_IN_WIPER MX25_ADCQ_CFG_IN(4)
#define MX25_ADCQ_CFG_IN_AUX0 MX25_ADCQ_CFG_IN(5)
#define MX25_ADCQ_CFG_IN_AUX1 MX25_ADCQ_CFG_IN(6)
#define MX25_ADCQ_CFG_IN_AUX2 MX25_ADCQ_CFG_IN(7)
#define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2)
#define MX25_ADCQ_CFG_REFN_XN MX25_ADCQ_CFG_REFN(0)
#define MX25_ADCQ_CFG_REFN_YN MX25_ADCQ_CFG_REFN(1)
#define MX25_ADCQ_CFG_REFN_NGND MX25_ADCQ_CFG_REFN(2)
#define MX25_ADCQ_CFG_REFN_NGND2 MX25_ADCQ_CFG_REFN(3)
#define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)
#define MX25_ADCQ_CFG_PENIACK (1 << 1)
#endif /* _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/ingenic-tcu.h
+56
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header file for the Ingenic JZ47xx TCU driver
*/
#ifndef __LINUX_MFD_INGENIC_TCU_H_
#define __LINUX_MFD_INGENIC_TCU_H_
#include <linux/bitops.h>
#define TCU_REG_WDT_TDR 0x00
#define TCU_REG_WDT_TCER 0x04
#define TCU_REG_WDT_TCNT 0x08
#define TCU_REG_WDT_TCSR 0x0c
#define TCU_REG_TER 0x10
#define TCU_REG_TESR 0x14
#define TCU_REG_TECR 0x18
#define TCU_REG_TSR 0x1c
#define TCU_REG_TFR 0x20
#define TCU_REG_TFSR 0x24
#define TCU_REG_TFCR 0x28
#define TCU_REG_TSSR 0x2c
#define TCU_REG_TMR 0x30
#define TCU_REG_TMSR 0x34
#define TCU_REG_TMCR 0x38
#define TCU_REG_TSCR 0x3c
#define TCU_REG_TDFR0 0x40
#define TCU_REG_TDHR0 0x44
#define TCU_REG_TCNT0 0x48
#define TCU_REG_TCSR0 0x4c
#define TCU_REG_OST_DR 0xe0
#define TCU_REG_OST_CNTL 0xe4
#define TCU_REG_OST_CNTH 0xe8
#define TCU_REG_OST_TCSR 0xec
#define TCU_REG_TSTR 0xf0
#define TCU_REG_TSTSR 0xf4
#define TCU_REG_TSTCR 0xf8
#define TCU_REG_OST_CNTHBUF 0xfc
#define TCU_TCSR_RESERVED_BITS 0x3f
#define TCU_TCSR_PARENT_CLOCK_MASK 0x07
#define TCU_TCSR_PRESCALE_LSB 3
#define TCU_TCSR_PRESCALE_MASK 0x38
#define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown gracefully 1: abruptly */
#define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */
#define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */
#define TCU_WDT_TCER_TCEN BIT(0) /* Watchdog timer enable */
#define TCU_CHANNEL_STRIDE 0x10
#define TCU_REG_TDFRc(c) (TCU_REG_TDFR0 + ((c) * TCU_CHANNEL_STRIDE))
#define TCU_REG_TDHRc(c) (TCU_REG_TDHR0 + ((c) * TCU_CHANNEL_STRIDE))
#define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE))
#define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE))
#endif /* __LINUX_MFD_INGENIC_TCU_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/intel-m10-bmc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel MAX 10 Board Management Controller chip.
*
* Copyright (C) 2018-2020 Intel Corporation, Inc.
*/
#ifndef __MFD_INTEL_M10_BMC_H
#define __MFD_INTEL_M10_BMC_H
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/dev_printk.h>
#include <linux/regmap.h>
#include <linux/rwsem.h>
#define M10BMC_N3000_LEGACY_BUILD_VER 0x300468
#define M10BMC_N3000_SYS_BASE 0x300800
#define M10BMC_N3000_SYS_END 0x300fff
#define M10BMC_N3000_FLASH_BASE 0x10000000
#define M10BMC_N3000_FLASH_END 0x1fffffff
#define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END
#define M10BMC_STAGING_BASE 0x18000000
#define M10BMC_STAGING_SIZE 0x3800000
/* Register offset of system registers */
#define NIOS2_N3000_FW_VERSION 0x0
#define M10BMC_N3000_MAC_LOW 0x10
#define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
#define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
#define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
#define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
#define M10BMC_N3000_MAC_HIGH 0x14
#define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
#define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
#define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
#define M10BMC_N3000_TEST_REG 0x3c
#define M10BMC_N3000_BUILD_VER 0x68
#define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
#define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)
#define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff
/* Telemetry registers */
#define M10BMC_N3000_TELEM_START 0x100
#define M10BMC_N3000_TELEM_END 0x250
#define M10BMC_D5005_TELEM_END 0x300
/* Secure update doorbell register, in system register region */
#define M10BMC_N3000_DOORBELL 0x400
/* Authorization Result register, in system register region */
#define M10BMC_N3000_AUTH_RESULT 0x404
/* Doorbell register fields */
#define DRBL_RSU_REQUEST BIT(0)
#define DRBL_RSU_PROGRESS GENMASK(7, 4)
#define DRBL_HOST_STATUS GENMASK(11, 8)
#define DRBL_RSU_STATUS GENMASK(23, 16)
#define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
#define DRBL_PKVL1_POLL_EN BIT(25)
#define DRBL_PKVL2_POLL_EN BIT(26)
#define DRBL_CONFIG_SEL BIT(28)
#define DRBL_REBOOT_REQ BIT(29)
#define DRBL_REBOOT_DISABLED BIT(30)
/* Progress states */
#define RSU_PROG_IDLE 0x0
#define RSU_PROG_PREPARE 0x1
#define RSU_PROG_READY 0x3
#define RSU_PROG_AUTHENTICATING 0x4
#define RSU_PROG_COPYING 0x5
#define RSU_PROG_UPDATE_CANCEL 0x6
#define RSU_PROG_PROGRAM_KEY_HASH 0x7
#define RSU_PROG_RSU_DONE 0x8
#define RSU_PROG_PKVL_PROM_DONE 0x9
/* Device and error states */
#define RSU_STAT_NORMAL 0x0
#define RSU_STAT_TIMEOUT 0x1
#define RSU_STAT_AUTH_FAIL 0x2
#define RSU_STAT_COPY_FAIL 0x3
#define RSU_STAT_FATAL 0x4
#define RSU_STAT_PKVL_REJECT 0x5
#define RSU_STAT_NON_INC 0x6
#define RSU_STAT_ERASE_FAIL 0x7
#define RSU_STAT_WEAROUT 0x8
#define RSU_STAT_NIOS_OK 0x80
#define RSU_STAT_USER_OK 0x81
#define RSU_STAT_FACTORY_OK 0x82
#define RSU_STAT_USER_FAIL 0x83
#define RSU_STAT_FACTORY_FAIL 0x84
#define RSU_STAT_NIOS_FLASH_ERR 0x85
#define RSU_STAT_FPGA_FLASH_ERR 0x86
#define HOST_STATUS_IDLE 0x0
#define HOST_STATUS_WRITE_DONE 0x1
#define HOST_STATUS_ABORT_RSU 0x2
#define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell)
/* interval 100ms and timeout 5s */
#define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000)
#define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000)
/* RSU PREP Timeout (2 minutes) to erase flash staging area */
#define RSU_PREP_INTERVAL_MS 100
#define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000)
/* RSU Complete Timeout (40 minutes) for full flash update */
#define RSU_COMPLETE_INTERVAL_MS 1000
#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000)
/* Addresses for security related data in FLASH */
#define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004
#define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000
#define M10BMC_N3000_BMC_PROG_MAGIC 0x5746
#define M10BMC_N3000_SR_REH_ADDR 0x17ffd004
#define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000
#define M10BMC_N3000_SR_PROG_MAGIC 0x5253
#define M10BMC_N3000_PR_REH_ADDR 0x17ffe004
#define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000
#define M10BMC_N3000_PR_PROG_MAGIC 0x5250
/* Address of 4KB inverted bit vector containing staging area FLASH count */
#define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
#define M10BMC_N6000_INDIRECT_BASE 0x400
#define M10BMC_N6000_SYS_BASE 0x0
#define M10BMC_N6000_SYS_END 0xfff
#define M10BMC_N6000_DOORBELL 0x1c0
#define M10BMC_N6000_AUTH_RESULT 0x1c4
#define AUTH_RESULT_RSU_STATUS GENMASK(23, 16)
#define M10BMC_N6000_BUILD_VER 0x0
#define NIOS2_N6000_FW_VERSION 0x4
#define M10BMC_N6000_MAC_LOW 0x20
#define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4)
/* Addresses for security related data in FLASH */
#define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004
#define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000
#define M10BMC_N6000_BMC_PROG_MAGIC 0x5746
#define M10BMC_N6000_SR_REH_ADDR 0x7ffd004
#define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000
#define M10BMC_N6000_SR_PROG_MAGIC 0x5253
#define M10BMC_N6000_PR_REH_ADDR 0x7ffe004
#define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000
#define M10BMC_N6000_PR_PROG_MAGIC 0x5250
#define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000
#define M10BMC_N6000_FLASH_MUX_CTRL 0x1d0
#define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0)
#define M10BMC_N6000_FLASH_MUX_IDLE 0
#define M10BMC_N6000_FLASH_MUX_NIOS 1
#define M10BMC_N6000_FLASH_MUX_HOST 2
#define M10BMC_N6000_FLASH_MUX_PFL 4
#define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux)
#define M10BMC_N6000_FLASH_NIOS_REQUEST BIT(4)
#define M10BMC_N6000_FLASH_HOST_REQUEST BIT(5)
#define M10BMC_N6000_FLASH_CTRL 0x40
#define M10BMC_N6000_FLASH_WR_MODE BIT(0)
#define M10BMC_N6000_FLASH_RD_MODE BIT(1)
#define M10BMC_N6000_FLASH_BUSY BIT(2)
#define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4)
#define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16)
#define M10BMC_N6000_FLASH_ADDR 0x44
#define M10BMC_N6000_FLASH_FIFO 0x800
#define M10BMC_N6000_READ_BLOCK_SIZE 0x800
#define M10BMC_N6000_FIFO_MAX_BYTES 0x800
#define M10BMC_N6000_FIFO_WORD_SIZE 4
#define M10BMC_N6000_FIFO_MAX_WORDS (M10BMC_N6000_FIFO_MAX_BYTES / \
M10BMC_N6000_FIFO_WORD_SIZE)
#define M10BMC_FLASH_INT_US 1
#define M10BMC_FLASH_TIMEOUT_US 10000
/**
* struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
*/
struct m10bmc_csr_map {
unsigned int base;
unsigned int build_version;
unsigned int fw_version;
unsigned int mac_low;
unsigned int mac_high;
unsigned int doorbell;
unsigned int auth_result;
unsigned int bmc_prog_addr;
unsigned int bmc_reh_addr;
unsigned int bmc_magic;
unsigned int sr_prog_addr;
unsigned int sr_reh_addr;
unsigned int sr_magic;
unsigned int pr_prog_addr;
unsigned int pr_reh_addr;
unsigned int pr_magic;
unsigned int rsu_update_counter;
unsigned int staging_size;
};
/**
* struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
* @cells: MFD cells
* @n_cells: MFD cells ARRAY_SIZE()
* @handshake_sys_reg_ranges: array of register ranges for fw handshake regs
* @handshake_sys_reg_nranges: number of register ranges for fw handshake regs
* @csr_map: the mappings for register definition of MAX10 BMC
*/
struct intel_m10bmc_platform_info {
struct mfd_cell *cells;
int n_cells;
const struct regmap_range *handshake_sys_reg_ranges;
unsigned int handshake_sys_reg_nranges;
const struct m10bmc_csr_map *csr_map;
};
struct intel_m10bmc;
/**
* struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
* @read: read a block of data from flash
* @write: write a block of data to flash
* @lock_write: locks flash access for erase+write
* @unlock_write: unlock flash access
*
* Write must be protected with @lock_write and @unlock_write. While the flash
* is locked, @read returns -EBUSY.
*/
struct intel_m10bmc_flash_bulk_ops {
int (*read)(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size);
int (*write)(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size);
int (*lock_write)(struct intel_m10bmc *m10bmc);
void (*unlock_write)(struct intel_m10bmc *m10bmc);
};
enum m10bmc_fw_state {
M10BMC_FW_STATE_NORMAL,
M10BMC_FW_STATE_SEC_UPDATE_PREPARE,
M10BMC_FW_STATE_SEC_UPDATE_WRITE,
M10BMC_FW_STATE_SEC_UPDATE_PROGRAM,
};
/**
* struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
* @dev: this device
* @regmap: the regmap used to access registers by m10bmc itself
* @info: the platform information for MAX10 BMC
* @flash_bulk_ops: optional device specific operations for flash R/W
* @bmcfw_lock: read/write semaphore to BMC firmware running state
* @bmcfw_state: BMC firmware running state. Available only when
* handshake_sys_reg_nranges > 0.
*/
struct intel_m10bmc {
struct device *dev;
struct regmap *regmap;
const struct intel_m10bmc_platform_info *info;
const struct intel_m10bmc_flash_bulk_ops *flash_bulk_ops;
struct rw_semaphore bmcfw_lock; /* Protects bmcfw_state */
enum m10bmc_fw_state bmcfw_state;
};
/*
* register access helper functions.
*
* m10bmc_raw_read - read m10bmc register per addr
* m10bmc_sys_read - read m10bmc system register per offset
* m10bmc_sys_update_bits - update m10bmc system register per offset
*/
static inline int
m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
unsigned int *val)
{
int ret;
ret = regmap_read(m10bmc->regmap, addr, val);
if (ret)
dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
addr, ret);
return ret;
}
int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val);
int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
unsigned int msk, unsigned int val);
/*
* Track the state of the firmware, as it is not available for register
* handshakes during secure updates on some MAX 10 cards.
*/
void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state);
/*
* MAX10 BMC Core support
*/
int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info);
extern const struct attribute_group *m10bmc_dev_groups[];
#endif /* __MFD_INTEL_M10_BMC_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/intel_pmc_bxt.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef MFD_INTEL_PMC_BXT_H
#define MFD_INTEL_PMC_BXT_H
/* GCR reg offsets from GCR base */
#define PMC_GCR_PMC_CFG_REG 0x08
#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
/* PMC_CFG_REG bit masks */
#define PMC_CFG_NO_REBOOT_EN BIT(4)
/**
* struct intel_pmc_dev - Intel PMC device structure
* @dev: Pointer to the parent PMC device
* @scu: Pointer to the SCU IPC device data structure
* @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
* @gcr_lock: Lock used to serialize access to GCR registers
* @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not
* available
*/
struct intel_pmc_dev {
struct device *dev;
struct intel_scu_ipc_dev *scu;
void __iomem *gcr_mem_base;
spinlock_t gcr_lock;
struct resource *telem_base;
};
#if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT)
int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data);
int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val);
int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data);
#else
static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset,
u64 *data)
{
return -ENOTSUPP;
}
static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset,
u32 mask, u32 val)
{
return -ENOTSUPP;
}
static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
{
return -ENOTSUPP;
}
#endif
#endif /* MFD_INTEL_PMC_BXT_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/intel_soc_pmic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel SoC PMIC Driver
*
* Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
*
* Author: Yang, Bin <bin.yang@intel.com>
* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
*/
#ifndef __INTEL_SOC_PMIC_H__
#define __INTEL_SOC_PMIC_H__
#include <linux/regmap.h>
enum intel_cht_wc_models {
INTEL_CHT_WC_UNKNOWN,
INTEL_CHT_WC_GPD_WIN_POCKET,
INTEL_CHT_WC_XIAOMI_MIPAD2,
INTEL_CHT_WC_LENOVO_YOGABOOK1,
INTEL_CHT_WC_LENOVO_YT3_X90,
};
/**
* struct intel_soc_pmic - Intel SoC PMIC data
* @irq: Master interrupt number of the parent PMIC device
* @regmap: Pointer to the parent PMIC device regmap structure
* @irq_chip_data: IRQ chip data for the PMIC itself
* @irq_chip_data_pwrbtn: Chained IRQ chip data for the Power Button
* @irq_chip_data_tmu: Chained IRQ chip data for the Time Management Unit
* @irq_chip_data_bcu: Chained IRQ chip data for the Burst Control Unit
* @irq_chip_data_adc: Chained IRQ chip data for the General Purpose ADC
* @irq_chip_data_chgr: Chained IRQ chip data for the External Charger
* @irq_chip_data_crit: Chained IRQ chip data for the Critical Event Handler
* @dev: Pointer to the parent PMIC device
* @scu: Pointer to the SCU IPC device data structure
*/
struct intel_soc_pmic {
int irq;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_chip_data;
struct regmap_irq_chip_data *irq_chip_data_pwrbtn;
struct regmap_irq_chip_data *irq_chip_data_tmu;
struct regmap_irq_chip_data *irq_chip_data_bcu;
struct regmap_irq_chip_data *irq_chip_data_adc;
struct regmap_irq_chip_data *irq_chip_data_chgr;
struct regmap_irq_chip_data *irq_chip_data_crit;
struct device *dev;
struct intel_scu_ipc_dev *scu;
enum intel_cht_wc_models cht_wc_model;
};
int intel_soc_pmic_exec_mipi_pmic_seq_element(u16 i2c_address, u32 reg_address,
u32 value, u32 mask);
#endif /* __INTEL_SOC_PMIC_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/intel_soc_pmic_bxtwc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header file for Intel Broxton Whiskey Cove PMIC
*
* Copyright (C) 2015 Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_BXTWC_H__
#define __INTEL_BXTWC_H__
/* BXT WC devices */
#define BXTWC_DEVICE1_ADDR 0x4E
#define BXTWC_DEVICE2_ADDR 0x4F
#define BXTWC_DEVICE3_ADDR 0x5E
/* device1 Registers */
#define BXTWC_CHIPID 0x4E00
#define BXTWC_CHIPVER 0x4E01
#define BXTWC_SCHGRIRQ0_ADDR 0x5E1A
#define BXTWC_CHGRCTRL0_ADDR 0x5E16
#define BXTWC_CHGRCTRL1_ADDR 0x5E17
#define BXTWC_CHGRCTRL2_ADDR 0x5E18
#define BXTWC_CHGRSTATUS_ADDR 0x5E19
#define BXTWC_THRMBATZONE_ADDR 0x4F22
#define BXTWC_USBPATH_ADDR 0x5E19
#define BXTWC_USBPHYCTRL_ADDR 0x5E07
#define BXTWC_USBIDCTRL_ADDR 0x5E05
#define BXTWC_USBIDEN_MASK 0x01
#define BXTWC_USBIDSTAT_ADDR 0x00FF
#define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29
#define BXTWC_DBGUSBBC1_ADDR 0x5FE0
#define BXTWC_DBGUSBBC2_ADDR 0x5FE1
#define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2
#define BXTWC_WAKESRC_ADDR 0x4E22
#define BXTWC_WAKESRC2_ADDR 0x4EE5
#define BXTWC_CHRTTADDR_ADDR 0x5E22
#define BXTWC_CHRTTDATA_ADDR 0x5E23
#define BXTWC_STHRMIRQ0_ADDR 0x4F19
#define WC_MTHRMIRQ1_ADDR 0x4E12
#define WC_STHRMIRQ1_ADDR 0x4F1A
#define WC_STHRMIRQ2_ADDR 0x4F1B
#define BXTWC_THRMZN0H_ADDR 0x4F44
#define BXTWC_THRMZN0L_ADDR 0x4F45
#define BXTWC_THRMZN1H_ADDR 0x4F46
#define BXTWC_THRMZN1L_ADDR 0x4F47
#define BXTWC_THRMZN2H_ADDR 0x4F48
#define BXTWC_THRMZN2L_ADDR 0x4F49
#define BXTWC_THRMZN3H_ADDR 0x4F4A
#define BXTWC_THRMZN3L_ADDR 0x4F4B
#define BXTWC_THRMZN4H_ADDR 0x4F4C
#define BXTWC_THRMZN4L_ADDR 0x4F4D
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/intel_soc_pmic_mrfld.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header file for Intel Merrifield Basin Cove PMIC
*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_SOC_PMIC_MRFLD_H__
#define __INTEL_SOC_PMIC_MRFLD_H__
#include <linux/bits.h>
#define BCOVE_ID 0x00
#define BCOVE_ID_MINREV0 GENMASK(2, 0)
#define BCOVE_ID_MAJREV0 GENMASK(5, 3)
#define BCOVE_ID_VENDID0 GENMASK(7, 6)
#define BCOVE_MINOR(x) (unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0)
#define BCOVE_MAJOR(x) (unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3)
#define BCOVE_VENDOR(x) (unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6)
#define BCOVE_IRQLVL1 0x01
#define BCOVE_PBIRQ 0x02
#define BCOVE_TMUIRQ 0x03
#define BCOVE_THRMIRQ 0x04
#define BCOVE_BCUIRQ 0x05
#define BCOVE_ADCIRQ 0x06
#define BCOVE_CHGRIRQ0 0x07
#define BCOVE_CHGRIRQ1 0x08
#define BCOVE_GPIOIRQ 0x09
#define BCOVE_CRITIRQ 0x0B
#define BCOVE_MIRQLVL1 0x0C
#define BCOVE_MPBIRQ 0x0D
#define BCOVE_MTMUIRQ 0x0E
#define BCOVE_MTHRMIRQ 0x0F
#define BCOVE_MBCUIRQ 0x10
#define BCOVE_MADCIRQ 0x11
#define BCOVE_MCHGRIRQ0 0x12
#define BCOVE_MCHGRIRQ1 0x13
#define BCOVE_MGPIOIRQ 0x14
#define BCOVE_MCRITIRQ 0x16
#define BCOVE_SCHGRIRQ0 0x4E
#define BCOVE_SCHGRIRQ1 0x4F
/* Level 1 IRQs */
#define BCOVE_LVL1_PWRBTN BIT(0) /* power button */
#define BCOVE_LVL1_TMU BIT(1) /* time management unit */
#define BCOVE_LVL1_THRM BIT(2) /* thermal */
#define BCOVE_LVL1_BCU BIT(3) /* burst control unit */
#define BCOVE_LVL1_ADC BIT(4) /* ADC */
#define BCOVE_LVL1_CHGR BIT(5) /* charger */
#define BCOVE_LVL1_GPIO BIT(6) /* GPIO */
#define BCOVE_LVL1_CRIT BIT(7) /* critical event */
/* Level 2 IRQs: power button */
#define BCOVE_PBIRQ_PBTN BIT(0)
#define BCOVE_PBIRQ_UBTN BIT(1)
/* Level 2 IRQs: ADC */
#define BCOVE_ADCIRQ_BATTEMP BIT(2)
#define BCOVE_ADCIRQ_SYSTEMP BIT(3)
#define BCOVE_ADCIRQ_BATTID BIT(4)
#define BCOVE_ADCIRQ_VIBATT BIT(5)
#define BCOVE_ADCIRQ_CCTICK BIT(7)
/* Level 2 IRQs: charger */
#define BCOVE_CHGRIRQ_BAT0ALRT BIT(4)
#define BCOVE_CHGRIRQ_BAT1ALRT BIT(5)
#define BCOVE_CHGRIRQ_BATCRIT BIT(6)
#define BCOVE_CHGRIRQ_VBUSDET BIT(0)
#define BCOVE_CHGRIRQ_DCDET BIT(1)
#define BCOVE_CHGRIRQ_BATTDET BIT(2)
#define BCOVE_CHGRIRQ_USBIDDET BIT(3)
#endif /* __INTEL_SOC_PMIC_MRFLD_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/ipaq-micro.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header file for the compaq Micro MFD
*/
#ifndef _MFD_IPAQ_MICRO_H_
#define _MFD_IPAQ_MICRO_H_
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/list.h>
#define TX_BUF_SIZE 32
#define RX_BUF_SIZE 16
#define CHAR_SOF 0x02
/*
* These are the different messages that can be sent to the microcontroller
* to control various aspects.
*/
#define MSG_VERSION 0x0
#define MSG_KEYBOARD 0x2
#define MSG_TOUCHSCREEN 0x3
#define MSG_EEPROM_READ 0x4
#define MSG_EEPROM_WRITE 0x5
#define MSG_THERMAL_SENSOR 0x6
#define MSG_NOTIFY_LED 0x8
#define MSG_BATTERY 0x9
#define MSG_SPI_READ 0xb
#define MSG_SPI_WRITE 0xc
#define MSG_BACKLIGHT 0xd /* H3600 only */
#define MSG_CODEC_CTRL 0xe /* H3100 only */
#define MSG_DISPLAY_CTRL 0xf /* H3100 only */
/* state of receiver parser */
enum rx_state {
STATE_SOF = 0, /* Next byte should be start of frame */
STATE_ID, /* Next byte is ID & message length */
STATE_DATA, /* Next byte is a data byte */
STATE_CHKSUM /* Next byte should be checksum */
};
/**
* struct ipaq_micro_txdev - TX state
* @len: length of message in TX buffer
* @index: current index into TX buffer
* @buf: TX buffer
*/
struct ipaq_micro_txdev {
u8 len;
u8 index;
u8 buf[TX_BUF_SIZE];
};
/**
* struct ipaq_micro_rxdev - RX state
* @state: context of RX state machine
* @chksum: calculated checksum
* @id: message ID from packet
* @len: RX buffer length
* @index: RX buffer index
* @buf: RX buffer
*/
struct ipaq_micro_rxdev {
enum rx_state state;
unsigned char chksum;
u8 id;
unsigned int len;
unsigned int index;
u8 buf[RX_BUF_SIZE];
};
/**
* struct ipaq_micro_msg - message to the iPAQ microcontroller
* @id: 4-bit ID of the message
* @tx_len: length of TX data
* @tx_data: TX data to send
* @rx_len: length of received RX data
* @rx_data: RX data to receive
* @ack: a completion that will be completed when RX is complete
* @node: list node if message gets queued
*/
struct ipaq_micro_msg {
u8 id;
u8 tx_len;
u8 tx_data[TX_BUF_SIZE];
u8 rx_len;
u8 rx_data[RX_BUF_SIZE];
struct completion ack;
struct list_head node;
};
/**
* struct ipaq_micro - iPAQ microcontroller state
* @dev: corresponding platform device
* @base: virtual memory base for underlying serial device
* @sdlc: virtual memory base for Synchronous Data Link Controller
* @version: version string
* @tx: TX state
* @rx: RX state
* @lock: lock for this state container
* @msg: current message
* @queue: message queue
* @key: callback for asynchronous key events
* @key_data: data to pass along with key events
* @ts: callback for asynchronous touchscreen events
* @ts_data: data to pass along with key events
*/
struct ipaq_micro {
struct device *dev;
void __iomem *base;
void __iomem *sdlc;
char version[5];
struct ipaq_micro_txdev tx; /* transmit ISR state */
struct ipaq_micro_rxdev rx; /* receive ISR state */
spinlock_t lock;
struct ipaq_micro_msg *msg;
struct list_head queue;
void (*key) (void *data, int len, unsigned char *rxdata);
void *key_data;
void (*ts) (void *data, int len, unsigned char *rxdata);
void *ts_data;
};
extern int
ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg);
static inline int
ipaq_micro_tx_msg_sync(struct ipaq_micro *micro,
struct ipaq_micro_msg *msg)
{
int ret;
init_completion(&msg->ack);
ret = ipaq_micro_tx_msg(micro, msg);
wait_for_completion(&msg->ack);
return ret;
}
static inline int
ipaq_micro_tx_msg_async(struct ipaq_micro *micro,
struct ipaq_micro_msg *msg)
{
init_completion(&msg->ack);
return ipaq_micro_tx_msg(micro, msg);
}
#endif /* _MFD_IPAQ_MICRO_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/iqs62x.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Azoteq IQS620A/621/622/624/625 Multi-Function Sensors
*
* Copyright (C) 2019 Jeff LaBundy <jeff@labundy.com>
*/
#ifndef __LINUX_MFD_IQS62X_H
#define __LINUX_MFD_IQS62X_H
#define IQS620_PROD_NUM 0x41
#define IQS621_PROD_NUM 0x46
#define IQS622_PROD_NUM 0x42
#define IQS624_PROD_NUM 0x43
#define IQS625_PROD_NUM 0x4E
#define IQS620_HW_NUM_V0 0x82
#define IQS620_HW_NUM_V1 IQS620_HW_NUM_V0
#define IQS620_HW_NUM_V2 IQS620_HW_NUM_V0
#define IQS620_HW_NUM_V3 0x92
#define IQS621_ALS_FLAGS 0x16
#define IQS622_ALS_FLAGS 0x14
#define IQS624_HALL_UI 0x70
#define IQS624_HALL_UI_WHL_EVENT BIT(4)
#define IQS624_HALL_UI_INT_EVENT BIT(3)
#define IQS624_HALL_UI_AUTO_CAL BIT(2)
#define IQS624_INTERVAL_DIV 0x7D
#define IQS620_GLBL_EVENT_MASK 0xD7
#define IQS620_GLBL_EVENT_MASK_PMU BIT(6)
#define IQS62X_NUM_KEYS 16
#define IQS62X_NUM_EVENTS (IQS62X_NUM_KEYS + 6)
#define IQS62X_EVENT_SIZE 10
enum iqs62x_ui_sel {
IQS62X_UI_PROX,
IQS62X_UI_SAR1,
};
enum iqs62x_event_reg {
IQS62X_EVENT_NONE,
IQS62X_EVENT_SYS,
IQS62X_EVENT_PROX,
IQS62X_EVENT_HYST,
IQS62X_EVENT_HALL,
IQS62X_EVENT_ALS,
IQS62X_EVENT_IR,
IQS62X_EVENT_WHEEL,
IQS62X_EVENT_INTER,
IQS62X_EVENT_UI_LO,
IQS62X_EVENT_UI_HI,
};
enum iqs62x_event_flag {
/* keys */
IQS62X_EVENT_PROX_CH0_T,
IQS62X_EVENT_PROX_CH0_P,
IQS62X_EVENT_PROX_CH1_T,
IQS62X_EVENT_PROX_CH1_P,
IQS62X_EVENT_PROX_CH2_T,
IQS62X_EVENT_PROX_CH2_P,
IQS62X_EVENT_HYST_POS_T,
IQS62X_EVENT_HYST_POS_P,
IQS62X_EVENT_HYST_NEG_T,
IQS62X_EVENT_HYST_NEG_P,
IQS62X_EVENT_SAR1_ACT,
IQS62X_EVENT_SAR1_QRD,
IQS62X_EVENT_SAR1_MOVE,
IQS62X_EVENT_SAR1_HALT,
IQS62X_EVENT_WHEEL_UP,
IQS62X_EVENT_WHEEL_DN,
/* switches */
IQS62X_EVENT_HALL_N_T,
IQS62X_EVENT_HALL_N_P,
IQS62X_EVENT_HALL_S_T,
IQS62X_EVENT_HALL_S_P,
/* everything else */
IQS62X_EVENT_SYS_RESET,
IQS62X_EVENT_SYS_ATI,
};
struct iqs62x_event_data {
u16 ui_data;
u8 als_flags;
u8 ir_flags;
u8 interval;
};
struct iqs62x_event_desc {
enum iqs62x_event_reg reg;
u8 mask;
u8 val;
};
struct iqs62x_dev_desc {
const char *dev_name;
const struct mfd_cell *sub_devs;
int num_sub_devs;
u8 prod_num;
u8 sw_num;
const u8 *cal_regs;
int num_cal_regs;
u8 prox_mask;
u8 sar_mask;
u8 hall_mask;
u8 hyst_mask;
u8 temp_mask;
u8 als_mask;
u8 ir_mask;
u8 prox_settings;
u8 als_flags;
u8 hall_flags;
u8 hyst_shift;
u8 interval;
u8 interval_div;
const char *fw_name;
const enum iqs62x_event_reg (*event_regs)[IQS62X_EVENT_SIZE];
};
struct iqs62x_core {
const struct iqs62x_dev_desc *dev_desc;
struct i2c_client *client;
struct regmap *regmap;
struct blocking_notifier_head nh;
struct list_head fw_blk_head;
struct completion ati_done;
struct completion fw_done;
enum iqs62x_ui_sel ui_sel;
unsigned long event_cache;
u8 sw_num;
u8 hw_num;
};
extern const struct iqs62x_event_desc iqs62x_events[IQS62X_NUM_EVENTS];
#endif /* __LINUX_MFD_IQS62X_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/janz.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Common Definitions for Janz MODULbus devices
*
* Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
*/
#ifndef JANZ_H
#define JANZ_H
struct janz_platform_data {
/* MODULbus Module Number */
unsigned int modno;
};
/* PLX bridge chip onboard registers */
struct janz_cmodio_onboard_regs {
u8 unused1;
/*
* Read access: interrupt status
* Write access: interrupt disable
*/
u8 int_disable;
u8 unused2;
/*
* Read access: MODULbus number (hex switch)
* Write access: interrupt enable
*/
u8 int_enable;
u8 unused3;
/* write-only */
u8 reset_assert;
u8 unused4;
/* write-only */
u8 reset_deassert;
u8 unused5;
/* read-write access to serial EEPROM */
u8 eep;
u8 unused6;
/* write-only access to EEPROM chip select */
u8 enid;
};
#endif /* JANZ_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/kempld.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Kontron PLD driver definitions
*
* Copyright (c) 2010-2012 Kontron Europe GmbH
* Author: Michael Brunner <michael.brunner@kontron.com>
*/
#ifndef _LINUX_MFD_KEMPLD_H_
#define _LINUX_MFD_KEMPLD_H_
/* kempld register definitions */
#define KEMPLD_IOINDEX 0xa80
#define KEMPLD_IODATA 0xa81
#define KEMPLD_MUTEX_KEY 0x80
#define KEMPLD_VERSION 0x00
#define KEMPLD_VERSION_LSB 0x00
#define KEMPLD_VERSION_MSB 0x01
#define KEMPLD_VERSION_GET_MINOR(x) (x & 0x1f)
#define KEMPLD_VERSION_GET_MAJOR(x) ((x >> 5) & 0x1f)
#define KEMPLD_VERSION_GET_NUMBER(x) ((x >> 10) & 0xf)
#define KEMPLD_VERSION_GET_TYPE(x) ((x >> 14) & 0x3)
#define KEMPLD_BUILDNR 0x02
#define KEMPLD_BUILDNR_LSB 0x02
#define KEMPLD_BUILDNR_MSB 0x03
#define KEMPLD_FEATURE 0x04
#define KEMPLD_FEATURE_LSB 0x04
#define KEMPLD_FEATURE_MSB 0x05
#define KEMPLD_FEATURE_BIT_I2C (1 << 0)
#define KEMPLD_FEATURE_BIT_WATCHDOG (1 << 1)
#define KEMPLD_FEATURE_BIT_GPIO (1 << 2)
#define KEMPLD_FEATURE_MASK_UART (7 << 3)
#define KEMPLD_FEATURE_BIT_NMI (1 << 8)
#define KEMPLD_FEATURE_BIT_SMI (1 << 9)
#define KEMPLD_FEATURE_BIT_SCI (1 << 10)
#define KEMPLD_SPEC 0x06
#define KEMPLD_SPEC_GET_MINOR(x) (x & 0x0f)
#define KEMPLD_SPEC_GET_MAJOR(x) ((x >> 4) & 0x0f)
#define KEMPLD_IRQ_GPIO 0x35
#define KEMPLD_IRQ_GPIO_MASK 0x0f
#define KEMPLD_IRQ_I2C 0x36
#define KEMPLD_CFG 0x37
#define KEMPLD_CFG_GPIO_I2C_MUX (1 << 0)
#define KEMPLD_CFG_BIOS_WP (1 << 7)
#define KEMPLD_CLK 33333333
#define KEMPLD_TYPE_RELEASE 0x0
#define KEMPLD_TYPE_DEBUG 0x1
#define KEMPLD_TYPE_CUSTOM 0x2
#define KEMPLD_VERSION_LEN 10
/**
* struct kempld_info - PLD device information structure
* @major: PLD major revision
* @minor: PLD minor revision
* @buildnr: PLD build number
* @number: PLD board specific index
* @type: PLD type
* @spec_major: PLD FW specification major revision
* @spec_minor: PLD FW specification minor revision
* @version: PLD version string
*/
struct kempld_info {
unsigned int major;
unsigned int minor;
unsigned int buildnr;
unsigned int number;
unsigned int type;
unsigned int spec_major;
unsigned int spec_minor;
char version[KEMPLD_VERSION_LEN];
};
/**
* struct kempld_device_data - Internal representation of the PLD device
* @io_base: Pointer to the IO memory
* @io_index: Pointer to the IO index register
* @io_data: Pointer to the IO data register
* @pld_clock: PLD clock frequency
* @feature_mask: PLD feature mask
* @dev: Pointer to kernel device structure
* @info: KEMPLD info structure
* @lock: PLD mutex
*/
struct kempld_device_data {
void __iomem *io_base;
void __iomem *io_index;
void __iomem *io_data;
u32 pld_clock;
u32 feature_mask;
struct device *dev;
struct kempld_info info;
struct mutex lock;
};
/**
* struct kempld_platform_data - PLD hardware configuration structure
* @pld_clock: PLD clock frequency
* @gpio_base: GPIO base pin number
* @ioresource: IO addresses of the PLD
* @get_hardware_mutex: PLD specific get_mutex callback
* @release_hardware_mutex: PLD specific release_mutex callback
* @get_info: PLD specific get_info callback
* @register_cells: PLD specific register_cells callback
*/
struct kempld_platform_data {
u32 pld_clock;
int gpio_base;
struct resource *ioresource;
void (*get_hardware_mutex) (struct kempld_device_data *);
void (*release_hardware_mutex) (struct kempld_device_data *);
int (*get_info) (struct kempld_device_data *);
int (*register_cells) (struct kempld_device_data *);
};
extern void kempld_get_mutex(struct kempld_device_data *pld);
extern void kempld_release_mutex(struct kempld_device_data *pld);
extern u8 kempld_read8(struct kempld_device_data *pld, u8 index);
extern void kempld_write8(struct kempld_device_data *pld, u8 index, u8 data);
extern u16 kempld_read16(struct kempld_device_data *pld, u8 index);
extern void kempld_write16(struct kempld_device_data *pld, u8 index, u16 data);
extern u32 kempld_read32(struct kempld_device_data *pld, u8 index);
extern void kempld_write32(struct kempld_device_data *pld, u8 index, u32 data);
#endif /* _LINUX_MFD_KEMPLD_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/khadas-mcu.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Khadas System control Microcontroller Register map
*
* Copyright (C) 2020 BayLibre SAS
*
* Author(s): Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef MFD_KHADAS_MCU_H
#define MFD_KHADAS_MCU_H
#define KHADAS_MCU_PASSWD_VEN_0_REG 0x00 /* RO */
#define KHADAS_MCU_PASSWD_VEN_1_REG 0x01 /* RO */
#define KHADAS_MCU_PASSWD_VEN_2_REG 0x02 /* RO */
#define KHADAS_MCU_PASSWD_VEN_3_REG 0x03 /* RO */
#define KHADAS_MCU_PASSWD_VEN_4_REG 0x04 /* RO */
#define KHADAS_MCU_PASSWD_VEN_5_REG 0x05 /* RO */
#define KHADAS_MCU_MAC_0_REG 0x06 /* RO */
#define KHADAS_MCU_MAC_1_REG 0x07 /* RO */
#define KHADAS_MCU_MAC_2_REG 0x08 /* RO */
#define KHADAS_MCU_MAC_3_REG 0x09 /* RO */
#define KHADAS_MCU_MAC_4_REG 0x0a /* RO */
#define KHADAS_MCU_MAC_5_REG 0x0b /* RO */
#define KHADAS_MCU_USID_0_REG 0x0c /* RO */
#define KHADAS_MCU_USID_1_REG 0x0d /* RO */
#define KHADAS_MCU_USID_2_REG 0x0e /* RO */
#define KHADAS_MCU_USID_3_REG 0x0f /* RO */
#define KHADAS_MCU_USID_4_REG 0x10 /* RO */
#define KHADAS_MCU_USID_5_REG 0x11 /* RO */
#define KHADAS_MCU_VERSION_0_REG 0x12 /* RO */
#define KHADAS_MCU_VERSION_1_REG 0x13 /* RO */
#define KHADAS_MCU_DEVICE_NO_0_REG 0x14 /* RO */
#define KHADAS_MCU_DEVICE_NO_1_REG 0x15 /* RO */
#define KHADAS_MCU_FACTORY_TEST_REG 0x16 /* R */
#define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
#define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
#define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
#define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
#define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
#define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
#define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
#define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
#define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
#define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
#define KHADAS_MCU_SHUTDOWN_NORMAL_REG 0x2c /* RW */
#define KHADAS_MCU_MAC_SWITCH_REG 0x2d /* RW */
#define KHADAS_MCU_MCU_SLEEP_MODE_REG 0x2e /* RW */
#define KHADAS_MCU_IR_CODE1_0_REG 0x2f /* RW */
#define KHADAS_MCU_IR_CODE1_1_REG 0x30 /* RW */
#define KHADAS_MCU_IR_CODE1_2_REG 0x31 /* RW */
#define KHADAS_MCU_IR_CODE1_3_REG 0x32 /* RW */
#define KHADAS_MCU_USB_PCIE_SWITCH_REG 0x33 /* RW */
#define KHADAS_MCU_IR_CODE2_0_REG 0x34 /* RW */
#define KHADAS_MCU_IR_CODE2_1_REG 0x35 /* RW */
#define KHADAS_MCU_IR_CODE2_2_REG 0x36 /* RW */
#define KHADAS_MCU_IR_CODE2_3_REG 0x37 /* RW */
#define KHADAS_MCU_PASSWD_USER_0_REG 0x40 /* RW */
#define KHADAS_MCU_PASSWD_USER_1_REG 0x41 /* RW */
#define KHADAS_MCU_PASSWD_USER_2_REG 0x42 /* RW */
#define KHADAS_MCU_PASSWD_USER_3_REG 0x43 /* RW */
#define KHADAS_MCU_PASSWD_USER_4_REG 0x44 /* RW */
#define KHADAS_MCU_PASSWD_USER_5_REG 0x45 /* RW */
#define KHADAS_MCU_USER_DATA_0_REG 0x46 /* RW 56 bytes */
#define KHADAS_MCU_PWR_OFF_CMD_REG 0x80 /* WO */
#define KHADAS_MCU_PASSWD_START_REG 0x81 /* WO */
#define KHADAS_MCU_CHECK_VEN_PASSWD_REG 0x82 /* WO */
#define KHADAS_MCU_CHECK_USER_PASSWD_REG 0x83 /* WO */
#define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG 0x86 /* RO */
#define KHADAS_MCU_WOL_INIT_START_REG 0x87 /* WO */
#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG 0x88 /* WO */
enum {
KHADAS_BOARD_VIM1 = 0x1,
KHADAS_BOARD_VIM2,
KHADAS_BOARD_VIM3,
KHADAS_BOARD_EDGE = 0x11,
KHADAS_BOARD_EDGE_V,
};
/**
* struct khadas_mcu - Khadas MCU structure
* @device: device reference used for logs
* @regmap: register map
*/
struct khadas_mcu {
struct device *dev;
struct regmap *regmap;
};
#endif /* MFD_KHADAS_MCU_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/lm3533.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* lm3533.h -- LM3533 interface
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <jhovold@gmail.com>
*/
#ifndef __LINUX_MFD_LM3533_H
#define __LINUX_MFD_LM3533_H
#define LM3533_ATTR_RO(_name) \
DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL)
#define LM3533_ATTR_RW(_name) \
DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
struct device;
struct gpio_desc;
struct regmap;
struct lm3533 {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *hwen;
int irq;
unsigned have_als:1;
unsigned have_backlights:1;
unsigned have_leds:1;
};
struct lm3533_ctrlbank {
struct lm3533 *lm3533;
struct device *dev;
int id;
};
struct lm3533_als_platform_data {
unsigned pwm_mode:1; /* PWM input mode (default analog) */
u8 r_select; /* 1 - 127 (ignored in PWM-mode) */
};
struct lm3533_bl_platform_data {
char *name;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 default_brightness; /* 0 - 255 */
u8 pwm; /* 0 - 0x3f */
};
struct lm3533_led_platform_data {
char *name;
const char *default_trigger;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 pwm; /* 0 - 0x3f */
};
enum lm3533_boost_freq {
LM3533_BOOST_FREQ_500KHZ,
LM3533_BOOST_FREQ_1000KHZ,
};
enum lm3533_boost_ovp {
LM3533_BOOST_OVP_16V,
LM3533_BOOST_OVP_24V,
LM3533_BOOST_OVP_32V,
LM3533_BOOST_OVP_40V,
};
struct lm3533_platform_data {
enum lm3533_boost_ovp boost_ovp;
enum lm3533_boost_freq boost_freq;
struct lm3533_als_platform_data *als;
struct lm3533_bl_platform_data *backlights;
int num_backlights;
struct lm3533_led_platform_data *leds;
int num_leds;
};
extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb,
u16 imax);
extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val);
extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val);
extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_LM3533_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/lochnagar.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Lochnagar internals
*
* Copyright (c) 2013-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
*/
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#ifndef CIRRUS_LOCHNAGAR_H
#define CIRRUS_LOCHNAGAR_H
enum lochnagar_type {
LOCHNAGAR1,
LOCHNAGAR2,
};
/**
* struct lochnagar - Core data for the Lochnagar audio board driver.
*
* @type: The type of Lochnagar device connected.
* @dev: A pointer to the struct device for the main MFD.
* @regmap: The devices main register map.
* @analogue_config_lock: Lock used to protect updates in the analogue
* configuration as these must not be changed whilst the hardware is processing
* the last update.
*/
struct lochnagar {
enum lochnagar_type type;
struct device *dev;
struct regmap *regmap;
/* Lock to protect updates to the analogue configuration */
struct mutex analogue_config_lock;
};
/* Register Addresses */
#define LOCHNAGAR_SOFTWARE_RESET 0x00
#define LOCHNAGAR_FIRMWARE_ID1 0x01
#define LOCHNAGAR_FIRMWARE_ID2 0x02
/* (0x0000) Software Reset */
#define LOCHNAGAR_DEVICE_ID_MASK 0xFFFC
#define LOCHNAGAR_DEVICE_ID_SHIFT 2
#define LOCHNAGAR_REV_ID_MASK 0x0003
#define LOCHNAGAR_REV_ID_SHIFT 0
int lochnagar_update_config(struct lochnagar *lochnagar);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lochnagar1_regs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Lochnagar1 register definitions
*
* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
*/
#ifndef LOCHNAGAR1_REGISTERS_H
#define LOCHNAGAR1_REGISTERS_H
/* Register Addresses */
#define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
#define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
#define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
#define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
#define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
#define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
#define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
#define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
#define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
#define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
#define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012
#define LOCHNAGAR1_DSP_AIF 0x0013
#define LOCHNAGAR1_GF_AIF1 0x0014
#define LOCHNAGAR1_GF_AIF2 0x0015
#define LOCHNAGAR1_PSIA_AIF 0x0016
#define LOCHNAGAR1_PSIA1_SEL 0x0017
#define LOCHNAGAR1_PSIA2_SEL 0x0018
#define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019
#define LOCHNAGAR1_GF_AIF3_SEL 0x001C
#define LOCHNAGAR1_GF_AIF4_SEL 0x001D
#define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E
#define LOCHNAGAR1_GF_AIF1_SEL 0x001F
#define LOCHNAGAR1_GF_AIF2_SEL 0x0020
#define LOCHNAGAR1_GF_GPIO2 0x0026
#define LOCHNAGAR1_GF_GPIO3 0x0027
#define LOCHNAGAR1_GF_GPIO7 0x0028
#define LOCHNAGAR1_RST 0x0029
#define LOCHNAGAR1_LED1 0x002A
#define LOCHNAGAR1_LED2 0x002B
#define LOCHNAGAR1_I2C_CTRL 0x0046
/*
* (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020)
* CDC_AIF1_SEL - GF_AIF2_SEL
*/
#define LOCHNAGAR1_SRC_MASK 0xFF
#define LOCHNAGAR1_SRC_SHIFT 0
/* (0x000D) CDC_AIF_CTRL1 */
#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10
#define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4
#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0
/* (0x000E) CDC_AIF_CTRL2 */
#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10
#define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4
#define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02
#define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1
#define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01
#define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0
/* (0x000F) EXT_AIF_CTRL */
#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08
#define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3
/* (0x0013) DSP_AIF */
#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10
#define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4
#define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08
#define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3
#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0
/* (0x0014) GF_AIF1 */
#define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40
#define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6
#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08
#define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3
#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0
/* (0x0015) GF_AIF2 */
#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08
#define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3
#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01
#define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0
/* (0x0016) PSIA_AIF */
#define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_PSIA2_ENA_MASK 0x10
#define LOCHNAGAR1_PSIA2_ENA_SHIFT 4
#define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_PSIA1_ENA_MASK 0x01
#define LOCHNAGAR1_PSIA1_ENA_SHIFT 0
/* (0x0029) RST */
#define LOCHNAGAR1_DSP_RESET_MASK 0x02
#define LOCHNAGAR1_DSP_RESET_SHIFT 1
#define LOCHNAGAR1_CDC_RESET_MASK 0x01
#define LOCHNAGAR1_CDC_RESET_SHIFT 0
/* (0x0046) I2C_CTRL */
#define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01
#define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lochnagar2_regs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Lochnagar2 register definitions
*
* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
*/
#ifndef LOCHNAGAR2_REGISTERS_H
#define LOCHNAGAR2_REGISTERS_H
/* Register Addresses */
#define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D
#define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E
#define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F
#define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010
#define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011
#define LOCHNAGAR2_PSIA1_CTRL 0x0012
#define LOCHNAGAR2_PSIA2_CTRL 0x0013
#define LOCHNAGAR2_GF_AIF3_CTRL 0x0014
#define LOCHNAGAR2_GF_AIF4_CTRL 0x0015
#define LOCHNAGAR2_GF_AIF1_CTRL 0x0016
#define LOCHNAGAR2_GF_AIF2_CTRL 0x0017
#define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018
#define LOCHNAGAR2_USB_AIF1_CTRL 0x0019
#define LOCHNAGAR2_USB_AIF2_CTRL 0x001A
#define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B
#define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E
#define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F
#define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020
#define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021
#define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022
#define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023
#define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024
#define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025
#define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026
#define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027
#define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031
#define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032
#define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033
#define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034
#define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035
#define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036
#define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037
#define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038
#define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039
#define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A
#define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B
#define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C
#define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D
#define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E
#define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F
#define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040
#define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041
#define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042
#define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043
#define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044
#define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045
#define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046
#define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047
#define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048
#define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049
#define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A
#define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B
#define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C
#define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D
#define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E
#define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F
#define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050
#define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051
#define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052
#define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053
#define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054
#define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055
#define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056
#define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057
#define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058
#define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059
#define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A
#define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B
#define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C
#define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D
#define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E
#define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F
#define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060
#define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061
#define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062
#define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063
#define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064
#define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065
#define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066
#define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067
#define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068
#define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069
#define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A
#define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B
#define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C
#define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D
#define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E
#define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F
#define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070
#define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071
#define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072
#define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073
#define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074
#define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075
#define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076
#define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077
#define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078
#define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079
#define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A
#define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C
#define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D
#define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E
#define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F
#define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080
#define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081
#define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082
#define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083
#define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084
#define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085
#define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086
#define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087
#define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088
#define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089
#define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A
#define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B
#define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C
#define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D
#define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E
#define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F
#define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090
#define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091
#define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092
#define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093
#define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094
#define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095
#define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096
#define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097
#define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098
#define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099
#define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A
#define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9
#define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA
#define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB
#define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC
#define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD
#define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE
#define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF
#define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0
#define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1
#define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2
#define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3
#define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4
#define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5
#define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6
#define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7
#define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8
#define LOCHNAGAR2_MINICARD_RESETS 0x00DF
#define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3
#define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4
#define LOCHNAGAR2_COMMS_CTRL4 0x00F0
#define LOCHNAGAR2_SPDIF_CTRL 0x00FE
#define LOCHNAGAR2_IMON_CTRL1 0x0108
#define LOCHNAGAR2_IMON_CTRL2 0x0109
#define LOCHNAGAR2_IMON_CTRL3 0x010A
#define LOCHNAGAR2_IMON_CTRL4 0x010B
#define LOCHNAGAR2_IMON_DATA1 0x010C
#define LOCHNAGAR2_IMON_DATA2 0x010D
#define LOCHNAGAR2_POWER_CTRL 0x0116
#define LOCHNAGAR2_MICVDD_CTRL1 0x0119
#define LOCHNAGAR2_MICVDD_CTRL2 0x011B
#define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E
#define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120
#define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180
/* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */
#define LOCHNAGAR2_AIF_ENA_MASK 0x8000
#define LOCHNAGAR2_AIF_ENA_SHIFT 15
#define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000
#define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14
#define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000
#define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13
#define LOCHNAGAR2_AIF_SRC_MASK 0x00FF
#define LOCHNAGAR2_AIF_SRC_SHIFT 0
/* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */
#define LOCHNAGAR2_CLK_ENA_MASK 0x8000
#define LOCHNAGAR2_CLK_ENA_SHIFT 15
#define LOCHNAGAR2_CLK_SRC_MASK 0x00FF
#define LOCHNAGAR2_CLK_SRC_SHIFT 0
/* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */
#define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF
#define LOCHNAGAR2_GPIO_SRC_SHIFT 0
/* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */
#define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000
#define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15
#define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF
#define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0
/* (0x00DF) MINICARD_RESETS */
#define LOCHNAGAR2_DSP_RESET_MASK 0x0002
#define LOCHNAGAR2_DSP_RESET_SHIFT 1
#define LOCHNAGAR2_CDC_RESET_MASK 0x0001
#define LOCHNAGAR2_CDC_RESET_SHIFT 0
/* (0x00E3) ANALOGUE_PATH_CTRL1 */
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14
/* (0x00E4) ANALOGUE_PATH_CTRL2 */
#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080
#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7
#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040
#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6
#define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038
#define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3
#define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007
#define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0
/* (0x00F0) COMMS_CTRL4 */
#define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001
#define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0
/* (0x00FE) SPDIF_CTRL */
#define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008
#define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3
#define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001
#define LOCHNAGAR2_SPDIF_RESET_SHIFT 0
/* (0x0108) IMON_CTRL1 */
#define LOCHNAGAR2_IMON_ENA_MASK 0x8000
#define LOCHNAGAR2_IMON_ENA_SHIFT 15
#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC
#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2
#define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003
#define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0
/* (0x0109) IMON_CTRL2 */
#define LOCHNAGAR2_IMON_FSR_MASK 0x03FF
#define LOCHNAGAR2_IMON_FSR_SHIFT 0
/* (0x010A) IMON_CTRL3 */
#define LOCHNAGAR2_IMON_DONE_MASK 0x0004
#define LOCHNAGAR2_IMON_DONE_SHIFT 2
#define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002
#define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1
#define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001
#define LOCHNAGAR2_IMON_MEASURE_SHIFT 0
/* (0x010B) IMON_CTRL4 */
#define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080
#define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7
#define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070
#define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4
#define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008
#define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3
#define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007
#define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0
/* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */
#define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF
#define LOCHNAGAR2_IMON_DATA_SHIFT 0
/* (0x0116) POWER_CTRL */
#define LOCHNAGAR2_PWR_ENA_MASK 0x0001
#define LOCHNAGAR2_PWR_ENA_SHIFT 0
/* (0x0119) MICVDD_CTRL1 */
#define LOCHNAGAR2_MICVDD_REG_ENA_MASK 0x8000
#define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT 15
/* (0x011B) MICVDD_CTRL2 */
#define LOCHNAGAR2_MICVDD_VSEL_MASK 0x001F
#define LOCHNAGAR2_MICVDD_VSEL_SHIFT 0
/* (0x011E) VDDCORE_CDC_CTRL1 */
#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK 0x8000
#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT 15
/* (0x0120) VDDCORE_CDC_CTRL2 */
#define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK 0x007F
#define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT 0
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/loongson-se.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2025 Loongson Technology Corporation Limited */
#ifndef __MFD_LOONGSON_SE_H__
#define __MFD_LOONGSON_SE_H__
#define LOONGSON_ENGINE_CMD_TIMEOUT_US 10000
#define SE_SEND_CMD_REG 0x0
#define SE_SEND_CMD_REG_LEN 0x8
/* Controller command ID */
#define SE_CMD_START 0x0
#define SE_CMD_SET_DMA 0x3
#define SE_CMD_SET_ENGINE_CMDBUF 0x4
#define SE_S2LINT_STAT 0x88
#define SE_S2LINT_EN 0x8c
#define SE_S2LINT_CL 0x94
#define SE_L2SINT_STAT 0x98
#define SE_L2SINT_SET 0xa0
#define SE_INT_ALL 0xffffffff
#define SE_INT_CONTROLLER BIT(0)
#define SE_ENGINE_MAX 16
#define SE_ENGINE_RNG 1
#define SE_CMD_RNG 0x100
#define SE_ENGINE_TPM 5
#define SE_CMD_TPM 0x500
#define SE_ENGINE_CMD_SIZE 32
struct loongson_se_engine {
struct loongson_se *se;
int id;
/* Command buffer */
void *command;
void *command_ret;
void *data_buffer;
uint buffer_size;
/* Data buffer offset to DMA base */
uint buffer_off;
struct completion completion;
};
struct loongson_se_engine *loongson_se_init_engine(struct device *dev, int id);
int loongson_se_send_engine_cmd(struct loongson_se_engine *engine);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lp3943.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI/National Semiconductor LP3943 Device
*
* Copyright 2013 Texas Instruments
*
* Author: Milo Kim <milo.kim@ti.com>
*/
#ifndef __MFD_LP3943_H__
#define __MFD_LP3943_H__
#include <linux/gpio.h>
#include <linux/regmap.h>
/* Registers */
#define LP3943_REG_GPIO_A 0x00
#define LP3943_REG_GPIO_B 0x01
#define LP3943_REG_PRESCALE0 0x02
#define LP3943_REG_PWM0 0x03
#define LP3943_REG_PRESCALE1 0x04
#define LP3943_REG_PWM1 0x05
#define LP3943_REG_MUX0 0x06
#define LP3943_REG_MUX1 0x07
#define LP3943_REG_MUX2 0x08
#define LP3943_REG_MUX3 0x09
/* Bit description for LP3943_REG_MUX0 ~ 3 */
#define LP3943_GPIO_IN 0x00
#define LP3943_GPIO_OUT_HIGH 0x00
#define LP3943_GPIO_OUT_LOW 0x01
#define LP3943_DIM_PWM0 0x02
#define LP3943_DIM_PWM1 0x03
#define LP3943_NUM_PWMS 2
enum lp3943_pwm_output {
LP3943_PWM_OUT0,
LP3943_PWM_OUT1,
LP3943_PWM_OUT2,
LP3943_PWM_OUT3,
LP3943_PWM_OUT4,
LP3943_PWM_OUT5,
LP3943_PWM_OUT6,
LP3943_PWM_OUT7,
LP3943_PWM_OUT8,
LP3943_PWM_OUT9,
LP3943_PWM_OUT10,
LP3943_PWM_OUT11,
LP3943_PWM_OUT12,
LP3943_PWM_OUT13,
LP3943_PWM_OUT14,
LP3943_PWM_OUT15,
};
/*
* struct lp3943_pwm_map
* @output: Output pins which are mapped to each PWM channel
* @num_outputs: Number of outputs
*/
struct lp3943_pwm_map {
enum lp3943_pwm_output *output;
int num_outputs;
};
/*
* struct lp3943_platform_data
* @pwms: Output channel definitions for PWM channel 0 and 1
*/
struct lp3943_platform_data {
struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS];
};
/*
* struct lp3943_reg_cfg
* @reg: Register address
* @mask: Register bit mask to be updated
* @shift: Register bit shift
*/
struct lp3943_reg_cfg {
u8 reg;
u8 mask;
u8 shift;
};
/*
* struct lp3943
* @dev: Parent device pointer
* @regmap: Used for I2C communication on accessing registers
* @pdata: LP3943 platform specific data
* @mux_cfg: Register configuration for pin MUX
* @pin_used: Bit mask for output pin used.
* This bitmask is used for pin assignment management.
* 1 = pin used, 0 = available.
* Only LSB 16 bits are used, but it is unsigned long type
* for atomic bitwise operations.
*/
struct lp3943 {
struct device *dev;
struct regmap *regmap;
struct lp3943_platform_data *pdata;
const struct lp3943_reg_cfg *mux_cfg;
unsigned long pin_used;
};
int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read);
int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data);
int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lp873x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Functions to access LP873X power management chip.
*
* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __LINUX_MFD_LP873X_H
#define __LINUX_MFD_LP873X_H
#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
/* LP873x chip id list */
#define LP873X 0x00
/* All register addresses */
#define LP873X_REG_DEV_REV 0X00
#define LP873X_REG_OTP_REV 0X01
#define LP873X_REG_BUCK0_CTRL_1 0X02
#define LP873X_REG_BUCK0_CTRL_2 0X03
#define LP873X_REG_BUCK1_CTRL_1 0X04
#define LP873X_REG_BUCK1_CTRL_2 0X05
#define LP873X_REG_BUCK0_VOUT 0X06
#define LP873X_REG_BUCK1_VOUT 0X07
#define LP873X_REG_LDO0_CTRL 0X08
#define LP873X_REG_LDO1_CTRL 0X09
#define LP873X_REG_LDO0_VOUT 0X0A
#define LP873X_REG_LDO1_VOUT 0X0B
#define LP873X_REG_BUCK0_DELAY 0X0C
#define LP873X_REG_BUCK1_DELAY 0X0D
#define LP873X_REG_LDO0_DELAY 0X0E
#define LP873X_REG_LDO1_DELAY 0X0F
#define LP873X_REG_GPO_DELAY 0X10
#define LP873X_REG_GPO2_DELAY 0X11
#define LP873X_REG_GPO_CTRL 0X12
#define LP873X_REG_CONFIG 0X13
#define LP873X_REG_PLL_CTRL 0X14
#define LP873X_REG_PGOOD_CTRL1 0X15
#define LP873X_REG_PGOOD_CTRL2 0X16
#define LP873X_REG_PG_FAULT 0X17
#define LP873X_REG_RESET 0X18
#define LP873X_REG_INT_TOP_1 0X19
#define LP873X_REG_INT_TOP_2 0X1A
#define LP873X_REG_INT_BUCK 0X1B
#define LP873X_REG_INT_LDO 0X1C
#define LP873X_REG_TOP_STAT 0X1D
#define LP873X_REG_BUCK_STAT 0X1E
#define LP873X_REG_LDO_STAT 0x1F
#define LP873X_REG_TOP_MASK_1 0x20
#define LP873X_REG_TOP_MASK_2 0x21
#define LP873X_REG_BUCK_MASK 0x22
#define LP873X_REG_LDO_MASK 0x23
#define LP873X_REG_SEL_I_LOAD 0x24
#define LP873X_REG_I_LOAD_2 0x25
#define LP873X_REG_I_LOAD_1 0x26
#define LP873X_REG_MAX LP873X_REG_I_LOAD_1
/* Register field definitions */
#define LP873X_DEV_REV_DEV_ID 0xC0
#define LP873X_DEV_REV_ALL_LAYER 0x30
#define LP873X_DEV_REV_METAL_LAYER 0x0F
#define LP873X_OTP_REV_OTP_ID 0xFF
#define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3)
#define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2)
#define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1)
#define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0)
#define LP873X_BUCK0_CTRL_2_BUCK0_ILIM 0x38
#define LP873X_BUCK0_CTRL_2_BUCK0_SLEW_RATE 0x07
#define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3)
#define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2)
#define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1)
#define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0)
#define LP873X_BUCK1_CTRL_2_BUCK1_ILIM 0x38
#define LP873X_BUCK1_CTRL_2_BUCK1_SLEW_RATE 0x07
#define LP873X_BUCK0_VOUT_BUCK0_VSET 0xFF
#define LP873X_BUCK1_VOUT_BUCK1_VSET 0xFF
#define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2)
#define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1)
#define LP873X_LDO0_CTRL_LDO0_EN BIT(0)
#define LP873X_LDO1_CTRL_LDO1_RDIS_EN BIT(2)
#define LP873X_LDO1_CTRL_LDO1_EN_PIN_CTRL BIT(1)
#define LP873X_LDO1_CTRL_LDO1_EN BIT(0)
#define LP873X_LDO0_VOUT_LDO0_VSET 0x1F
#define LP873X_LDO1_VOUT_LDO1_VSET 0x1F
#define LP873X_BUCK0_DELAY_BUCK0_SD_DELAY 0xF0
#define LP873X_BUCK0_DELAY_BUCK0_SU_DELAY 0x0F
#define LP873X_BUCK1_DELAY_BUCK1_SD_DELAY 0xF0
#define LP873X_BUCK1_DELAY_BUCK1_SU_DELAY 0x0F
#define LP873X_LDO0_DELAY_LDO0_SD_DELAY 0xF0
#define LP873X_LDO0_DELAY_LDO0_SU_DELAY 0x0F
#define LP873X_LDO1_DELAY_LDO1_SD_DELAY 0xF0
#define LP873X_LDO1_DELAY_LDO1_SU_DELAY 0x0F
#define LP873X_GPO_DELAY_GPO_SD_DELAY 0xF0
#define LP873X_GPO_DELAY_GPO_SU_DELAY 0x0F
#define LP873X_GPO2_DELAY_GPO2_SD_DELAY 0xF0
#define LP873X_GPO2_DELAY_GPO2_SU_DELAY 0x0F
#define LP873X_GPO_CTRL_GPO2_OD BIT(6)
#define LP873X_GPO_CTRL_GPO2_EN_PIN_CTRL BIT(5)
#define LP873X_GPO_CTRL_GPO2_EN BIT(4)
#define LP873X_GPO_CTRL_GPO_OD BIT(2)
#define LP873X_GPO_CTRL_GPO_EN_PIN_CTRL BIT(1)
#define LP873X_GPO_CTRL_GPO_EN BIT(0)
#define LP873X_CONFIG_SU_DELAY_SEL BIT(6)
#define LP873X_CONFIG_SD_DELAY_SEL BIT(5)
#define LP873X_CONFIG_CLKIN_PIN_SEL BIT(4)
#define LP873X_CONFIG_CLKIN_PD BIT(3)
#define LP873X_CONFIG_EN_PD BIT(2)
#define LP873X_CONFIG_TDIE_WARN_LEVEL BIT(1)
#define LP873X_EN_SPREAD_SPEC BIT(0)
#define LP873X_PLL_CTRL_EN_PLL BIT(6)
#define LP873X_EXT_CLK_FREQ 0x1F
#define LP873X_PGOOD_CTRL1_PGOOD_POL BIT(7)
#define LP873X_PGOOD_CTRL1_PGOOD_OD BIT(6)
#define LP873X_PGOOD_CTRL1_PGOOD_WINDOW_LDO BIT(5)
#define LP873X_PGOOD_CTRL1_PGOOD_WINDOWN_BUCK BIT(4)
#define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_LDO1 BIT(3)
#define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_LDO0 BIT(2)
#define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_BUCK1 BIT(1)
#define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_BUCK0 BIT(0)
#define LP873X_PGOOD_CTRL2_EN_PGOOD_TWARN BIT(2)
#define LP873X_PGOOD_CTRL2_EN_PG_FAULT_GATE BIT(1)
#define LP873X_PGOOD_CTRL2_PGOOD_MODE BIT(0)
#define LP873X_PG_FAULT_PG_FAULT_LDO1 BIT(3)
#define LP873X_PG_FAULT_PG_FAULT_LDO0 BIT(2)
#define LP873X_PG_FAULT_PG_FAULT_BUCK1 BIT(1)
#define LP873X_PG_FAULT_PG_FAULT_BUCK0 BIT(0)
#define LP873X_RESET_SW_RESET BIT(0)
#define LP873X_INT_TOP_1_PGOOD_INT BIT(7)
#define LP873X_INT_TOP_1_LDO_INT BIT(6)
#define LP873X_INT_TOP_1_BUCK_INT BIT(5)
#define LP873X_INT_TOP_1_SYNC_CLK_INT BIT(4)
#define LP873X_INT_TOP_1_TDIE_SD_INT BIT(3)
#define LP873X_INT_TOP_1_TDIE_WARN_INT BIT(2)
#define LP873X_INT_TOP_1_OVP_INT BIT(1)
#define LP873X_INT_TOP_1_I_MEAS_INT BIT(0)
#define LP873X_INT_TOP_2_RESET_REG_INT BIT(0)
#define LP873X_INT_BUCK_BUCK1_PG_INT BIT(6)
#define LP873X_INT_BUCK_BUCK1_SC_INT BIT(5)
#define LP873X_INT_BUCK_BUCK1_ILIM_INT BIT(4)
#define LP873X_INT_BUCK_BUCK0_PG_INT BIT(2)
#define LP873X_INT_BUCK_BUCK0_SC_INT BIT(1)
#define LP873X_INT_BUCK_BUCK0_ILIM_INT BIT(0)
#define LP873X_INT_LDO_LDO1_PG_INT BIT(6)
#define LP873X_INT_LDO_LDO1_SC_INT BIT(5)
#define LP873X_INT_LDO_LDO1_ILIM_INT BIT(4)
#define LP873X_INT_LDO_LDO0_PG_INT BIT(2)
#define LP873X_INT_LDO_LDO0_SC_INT BIT(1)
#define LP873X_INT_LDO_LDO0_ILIM_INT BIT(0)
#define LP873X_TOP_STAT_PGOOD_STAT BIT(7)
#define LP873X_TOP_STAT_SYNC_CLK_STAT BIT(4)
#define LP873X_TOP_STAT_TDIE_SD_STAT BIT(3)
#define LP873X_TOP_STAT_TDIE_WARN_STAT BIT(2)
#define LP873X_TOP_STAT_OVP_STAT BIT(1)
#define LP873X_BUCK_STAT_BUCK1_STAT BIT(7)
#define LP873X_BUCK_STAT_BUCK1_PG_STAT BIT(6)
#define LP873X_BUCK_STAT_BUCK1_ILIM_STAT BIT(4)
#define LP873X_BUCK_STAT_BUCK0_STAT BIT(3)
#define LP873X_BUCK_STAT_BUCK0_PG_STAT BIT(2)
#define LP873X_BUCK_STAT_BUCK0_ILIM_STAT BIT(0)
#define LP873X_LDO_STAT_LDO1_STAT BIT(7)
#define LP873X_LDO_STAT_LDO1_PG_STAT BIT(6)
#define LP873X_LDO_STAT_LDO1_ILIM_STAT BIT(4)
#define LP873X_LDO_STAT_LDO0_STAT BIT(3)
#define LP873X_LDO_STAT_LDO0_PG_STAT BIT(2)
#define LP873X_LDO_STAT_LDO0_ILIM_STAT BIT(0)
#define LP873X_TOP_MASK_1_PGOOD_INT_MASK BIT(7)
#define LP873X_TOP_MASK_1_SYNC_CLK_MASK BIT(4)
#define LP873X_TOP_MASK_1_TDIE_WARN_MASK BIT(2)
#define LP873X_TOP_MASK_1_I_MEAS_MASK BIT(0)
#define LP873X_TOP_MASK_2_RESET_REG_MASK BIT(0)
#define LP873X_BUCK_MASK_BUCK1_PGF_MASK BIT(7)
#define LP873X_BUCK_MASK_BUCK1_PGR_MASK BIT(6)
#define LP873X_BUCK_MASK_BUCK1_ILIM_MASK BIT(4)
#define LP873X_BUCK_MASK_BUCK0_PGF_MASK BIT(3)
#define LP873X_BUCK_MASK_BUCK0_PGR_MASK BIT(2)
#define LP873X_BUCK_MASK_BUCK0_ILIM_MASK BIT(0)
#define LP873X_LDO_MASK_LDO1_PGF_MASK BIT(7)
#define LP873X_LDO_MASK_LDO1_PGR_MASK BIT(6)
#define LP873X_LDO_MASK_LDO1_ILIM_MASK BIT(4)
#define LP873X_LDO_MASK_LDO0_PGF_MASK BIT(3)
#define LP873X_LDO_MASK_LDO0_PGR_MASK BIT(2)
#define LP873X_LDO_MASK_LDO0_ILIM_MASK BIT(0)
#define LP873X_SEL_I_LOAD_CURRENT_BUCK_SELECT BIT(0)
#define LP873X_I_LOAD_2_BUCK_LOAD_CURRENT BIT(0)
#define LP873X_I_LOAD_1_BUCK_LOAD_CURRENT 0xFF
#define LP873X_MAX_REG_ID LP873X_LDO_1
/* Number of step-down converters available */
#define LP873X_NUM_BUCK 2
/* Number of LDO voltage regulators available */
#define LP873X_NUM_LDO 2
/* Number of total regulators available */
#define LP873X_NUM_REGULATOR (LP873X_NUM_BUCK + LP873X_NUM_LDO)
enum lp873x_regulator_id {
/* BUCK's */
LP873X_BUCK_0,
LP873X_BUCK_1,
/* LDOs */
LP873X_LDO_0,
LP873X_LDO_1,
};
/**
* struct lp873x - state holder for the lp873x driver
* @dev: struct device pointer for MFD device
* @rev: revision of the lp873x
* @lock: lock guarding the data structure
* @regmap: register map of the lp873x PMIC
*
* Device data may be used to access the LP873X chip
*/
struct lp873x {
struct device *dev;
u8 rev;
struct regmap *regmap;
};
#endif /* __LINUX_MFD_LP873X_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/lp87565.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Functions to access LP87565 power management chip.
*
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __LINUX_MFD_LP87565_H
#define __LINUX_MFD_LP87565_H
#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
enum lp87565_device_type {
LP87565_DEVICE_TYPE_UNKNOWN = 0,
LP87565_DEVICE_TYPE_LP87524_Q1,
LP87565_DEVICE_TYPE_LP87561_Q1,
LP87565_DEVICE_TYPE_LP87565_Q1,
};
/* All register addresses */
#define LP87565_REG_DEV_REV 0X00
#define LP87565_REG_OTP_REV 0X01
#define LP87565_REG_BUCK0_CTRL_1 0X02
#define LP87565_REG_BUCK0_CTRL_2 0X03
#define LP87565_REG_BUCK1_CTRL_1 0X04
#define LP87565_REG_BUCK1_CTRL_2 0X05
#define LP87565_REG_BUCK2_CTRL_1 0X06
#define LP87565_REG_BUCK2_CTRL_2 0X07
#define LP87565_REG_BUCK3_CTRL_1 0X08
#define LP87565_REG_BUCK3_CTRL_2 0X09
#define LP87565_REG_BUCK0_VOUT 0X0A
#define LP87565_REG_BUCK0_FLOOR_VOUT 0X0B
#define LP87565_REG_BUCK1_VOUT 0X0C
#define LP87565_REG_BUCK1_FLOOR_VOUT 0X0D
#define LP87565_REG_BUCK2_VOUT 0X0E
#define LP87565_REG_BUCK2_FLOOR_VOUT 0X0F
#define LP87565_REG_BUCK3_VOUT 0X10
#define LP87565_REG_BUCK3_FLOOR_VOUT 0X11
#define LP87565_REG_BUCK0_DELAY 0X12
#define LP87565_REG_BUCK1_DELAY 0X13
#define LP87565_REG_BUCK2_DELAY 0X14
#define LP87565_REG_BUCK3_DELAY 0X15
#define LP87565_REG_GPO2_DELAY 0X16
#define LP87565_REG_GPO3_DELAY 0X17
#define LP87565_REG_RESET 0X18
#define LP87565_REG_CONFIG 0X19
#define LP87565_REG_INT_TOP_1 0X1A
#define LP87565_REG_INT_TOP_2 0X1B
#define LP87565_REG_INT_BUCK_0_1 0X1C
#define LP87565_REG_INT_BUCK_2_3 0X1D
#define LP87565_REG_TOP_STAT 0X1E
#define LP87565_REG_BUCK_0_1_STAT 0X1F
#define LP87565_REG_BUCK_2_3_STAT 0x20
#define LP87565_REG_TOP_MASK_1 0x21
#define LP87565_REG_TOP_MASK_2 0x22
#define LP87565_REG_BUCK_0_1_MASK 0x23
#define LP87565_REG_BUCK_2_3_MASK 0x24
#define LP87565_REG_SEL_I_LOAD 0x25
#define LP87565_REG_I_LOAD_2 0x26
#define LP87565_REG_I_LOAD_1 0x27
#define LP87565_REG_PGOOD_CTRL1 0x28
#define LP87565_REG_PGOOD_CTRL2 0x29
#define LP87565_REG_PGOOD_FLT 0x2A
#define LP87565_REG_PLL_CTRL 0x2B
#define LP87565_REG_PIN_FUNCTION 0x2C
#define LP87565_REG_GPIO_CONFIG 0x2D
#define LP87565_REG_GPIO_IN 0x2E
#define LP87565_REG_GPIO_OUT 0x2F
#define LP87565_REG_MAX LP87565_REG_GPIO_OUT
/* Register field definitions */
#define LP87565_DEV_REV_DEV_ID 0xC0
#define LP87565_DEV_REV_ALL_LAYER 0x30
#define LP87565_DEV_REV_METAL_LAYER 0x0F
#define LP87565_OTP_REV_OTP_ID 0xFF
#define LP87565_BUCK_CTRL_1_EN BIT(7)
#define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
#define LP87565_BUCK_CTRL_1_PIN_SELECT_EN 0x30
#define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
#define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
#define LP87565_BUCK_CTRL_1_FPWM BIT(1)
/* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */
#define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
#define LP87565_BUCK_CTRL_2_ILIM 0x38
#define LP87565_BUCK_CTRL_2_SLEW_RATE 0x07
#define LP87565_BUCK_VSET 0xFF
#define LP87565_BUCK_FLOOR_VSET 0xFF
#define LP87565_BUCK_SHUTDOWN_DELAY 0xF0
#define LP87565_BUCK_STARTUP_DELAY 0x0F
#define LP87565_GPIO_SHUTDOWN_DELAY 0xF0
#define LP87565_GPIO_STARTUP_DELAY 0x0F
#define LP87565_RESET_SW_RESET BIT(0)
#define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
#define LP87565_CONFIG_CLKIN_PD BIT(6)
#define LP87565_CONFIG_EN4_PD BIT(5)
#define LP87565_CONFIG_EN3_PD BIT(4)
#define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3)
#define LP87565_CONFIG_EN2_PD BIT(2)
#define LP87565_CONFIG_EN1_PD BIT(1)
#define LP87565_INT_GPIO BIT(7)
#define LP87565_INT_BUCK23 BIT(6)
#define LP87565_INT_BUCK01 BIT(5)
#define LP87565_NO_SYNC_CLK BIT(4)
#define LP87565_TDIE_SD BIT(3)
#define LP87565_TDIE_WARN BIT(2)
#define LP87565_INT_OVP BIT(1)
#define LP87565_I_LOAD_READY BIT(0)
#define LP87565_INT_TOP2_RESET_REG BIT(0)
#define LP87565_BUCK1_PG_INT BIT(6)
#define LP87565_BUCK1_SC_INT BIT(5)
#define LP87565_BUCK1_ILIM_INT BIT(4)
#define LP87565_BUCK0_PG_INT BIT(2)
#define LP87565_BUCK0_SC_INT BIT(1)
#define LP87565_BUCK0_ILIM_INT BIT(0)
#define LP87565_BUCK3_PG_INT BIT(6)
#define LP87565_BUCK3_SC_INT BIT(5)
#define LP87565_BUCK3_ILIM_INT BIT(4)
#define LP87565_BUCK2_PG_INT BIT(2)
#define LP87565_BUCK2_SC_INT BIT(1)
#define LP87565_BUCK2_ILIM_INT BIT(0)
#define LP87565_SYNC_CLK_STAT BIT(4)
#define LP87565_TDIE_SD_STAT BIT(3)
#define LP87565_TDIE_WARN_STAT BIT(2)
#define LP87565_OVP_STAT BIT(1)
#define LP87565_BUCK1_STAT BIT(7)
#define LP87565_BUCK1_PG_STAT BIT(6)
#define LP87565_BUCK1_ILIM_STAT BIT(4)
#define LP87565_BUCK0_STAT BIT(3)
#define LP87565_BUCK0_PG_STAT BIT(2)
#define LP87565_BUCK0_ILIM_STAT BIT(0)
#define LP87565_BUCK3_STAT BIT(7)
#define LP87565_BUCK3_PG_STAT BIT(6)
#define LP87565_BUCK3_ILIM_STAT BIT(4)
#define LP87565_BUCK2_STAT BIT(3)
#define LP87565_BUCK2_PG_STAT BIT(2)
#define LP87565_BUCK2_ILIM_STAT BIT(0)
#define LPL87565_GPIO_MASK BIT(7)
#define LPL87565_SYNC_CLK_MASK BIT(4)
#define LPL87565_TDIE_WARN_MASK BIT(2)
#define LPL87565_I_LOAD_READY_MASK BIT(0)
#define LPL87565_RESET_REG_MASK BIT(0)
#define LPL87565_BUCK1_PG_MASK BIT(6)
#define LPL87565_BUCK1_ILIM_MASK BIT(4)
#define LPL87565_BUCK0_PG_MASK BIT(2)
#define LPL87565_BUCK0_ILIM_MASK BIT(0)
#define LPL87565_BUCK3_PG_MASK BIT(6)
#define LPL87565_BUCK3_ILIM_MASK BIT(4)
#define LPL87565_BUCK2_PG_MASK BIT(2)
#define LPL87565_BUCK2_ILIM_MASK BIT(0)
#define LP87565_LOAD_CURRENT_BUCK_SELECT 0x3
#define LP87565_I_LOAD2_BUCK_LOAD_CURRENT 0x3
#define LP87565_I_LOAD1_BUCK_LOAD_CURRENT 0xFF
#define LP87565_PG3_SEL 0xC0
#define LP87565_PG2_SEL 0x30
#define LP87565_PG1_SEL 0x0C
#define LP87565_PG0_SEL 0x03
#define LP87565_HALF_DAY BIT(7)
#define LP87565_EN_PG0_NINT BIT(6)
#define LP87565_PGOOD_SET_DELAY BIT(5)
#define LP87565_EN_PGFLT_STAT BIT(4)
#define LP87565_PGOOD_WINDOW BIT(2)
#define LP87565_PGOOD_OD BIT(1)
#define LP87565_PGOOD_POL BIT(0)
#define LP87565_PG3_FLT BIT(3)
#define LP87565_PG2_FLT BIT(2)
#define LP87565_PG1_FLT BIT(1)
#define LP87565_PG0_FLT BIT(0)
#define LP87565_PLL_MODE 0xC0
#define LP87565_EXT_CLK_FREQ 0x1F
#define LP87565_EN_SPREAD_SPEC BIT(7)
#define LP87565_EN_PIN_CTRL_GPIO3 BIT(6)
#define LP87565_EN_PIN_SELECT_GPIO3 BIT(5)
#define LP87565_EN_PIN_CTRL_GPIO2 BIT(4)
#define LP87565_EN_PIN_SELECT_GPIO2 BIT(3)
#define LP87565_GPIO3_SEL BIT(2)
#define LP87565_GPIO2_SEL BIT(1)
#define LP87565_GPIO1_SEL BIT(0)
#define LP87565_GPIO3_OD BIT(6)
#define LP87565_GPIO2_OD BIT(5)
#define LP87565_GPIO1_OD BIT(4)
#define LP87565_GPIO3_DIR BIT(2)
#define LP87565_GPIO2_DIR BIT(1)
#define LP87565_GPIO1_DIR BIT(0)
#define LP87565_GPIO3_IN BIT(2)
#define LP87565_GPIO2_IN BIT(1)
#define LP87565_GPIO1_IN BIT(0)
#define LP87565_GPIO3_OUT BIT(2)
#define LP87565_GPIO2_OUT BIT(1)
#define LP87565_GPIO1_OUT BIT(0)
/**
* struct LP87565 - state holder for the LP87565 driver
* @dev: struct device pointer for MFD device
* @rev: revision of the LP87565
* @dev_type: The device type for example lp87565-q1
* @lock: lock guarding the data structure
* @regmap: register map of the LP87565 PMIC
*
* Device data may be used to access the LP87565 chip
*/
struct lp87565 {
struct device *dev;
u8 rev;
u8 dev_type;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
};
#endif /* __LINUX_MFD_LP87565_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/lp8788-isink.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI LP8788 MFD - common definitions for current sinks
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*/
#ifndef __ISINK_LP8788_H__
#define __ISINK_LP8788_H__
/* register address */
#define LP8788_ISINK_CTRL 0x99
#define LP8788_ISINK12_IOUT 0x9A
#define LP8788_ISINK3_IOUT 0x9B
#define LP8788_ISINK1_PWM 0x9C
#define LP8788_ISINK2_PWM 0x9D
#define LP8788_ISINK3_PWM 0x9E
/* mask bits */
#define LP8788_ISINK1_IOUT_M 0x0F /* Addr 9Ah */
#define LP8788_ISINK2_IOUT_M 0xF0
#define LP8788_ISINK3_IOUT_M 0x0F /* Addr 9Bh */
/* 6 bits used for PWM code : Addr 9C ~ 9Eh */
#define LP8788_ISINK_MAX_PWM 63
#define LP8788_ISINK_SCALE_OFFSET 3
static const u8 lp8788_iout_addr[] = {
LP8788_ISINK12_IOUT,
LP8788_ISINK12_IOUT,
LP8788_ISINK3_IOUT,
};
static const u8 lp8788_iout_mask[] = {
LP8788_ISINK1_IOUT_M,
LP8788_ISINK2_IOUT_M,
LP8788_ISINK3_IOUT_M,
};
static const u8 lp8788_pwm_addr[] = {
LP8788_ISINK1_PWM,
LP8788_ISINK2_PWM,
LP8788_ISINK3_PWM,
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lp8788.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI LP8788 MFD Device
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*/
#ifndef __MFD_LP8788_H__
#define __MFD_LP8788_H__
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#define LP8788_DEV_BUCK "lp8788-buck"
#define LP8788_DEV_DLDO "lp8788-dldo"
#define LP8788_DEV_ALDO "lp8788-aldo"
#define LP8788_DEV_CHARGER "lp8788-charger"
#define LP8788_DEV_RTC "lp8788-rtc"
#define LP8788_DEV_BACKLIGHT "lp8788-backlight"
#define LP8788_DEV_VIBRATOR "lp8788-vibrator"
#define LP8788_DEV_KEYLED "lp8788-keyled"
#define LP8788_DEV_ADC "lp8788-adc"
#define LP8788_NUM_BUCKS 4
#define LP8788_NUM_DLDOS 12
#define LP8788_NUM_ALDOS 10
#define LP8788_NUM_BUCK2_DVS 2
#define LP8788_CHG_IRQ "CHG_IRQ"
#define LP8788_PRSW_IRQ "PRSW_IRQ"
#define LP8788_BATT_IRQ "BATT_IRQ"
#define LP8788_ALM_IRQ "ALARM_IRQ"
enum lp8788_int_id {
/* interrup register 1 : Addr 00h */
LP8788_INT_TSDL,
LP8788_INT_TSDH,
LP8788_INT_UVLO,
LP8788_INT_FLAGMON,
LP8788_INT_PWRON_TIME,
LP8788_INT_PWRON,
LP8788_INT_COMP1,
LP8788_INT_COMP2,
/* interrupt register 2 : Addr 01h */
LP8788_INT_CHG_INPUT_STATE,
LP8788_INT_CHG_STATE,
LP8788_INT_EOC,
LP8788_INT_CHG_RESTART,
LP8788_INT_RESTART_TIMEOUT,
LP8788_INT_FULLCHG_TIMEOUT,
LP8788_INT_PRECHG_TIMEOUT,
/* interrupt register 3 : Addr 02h */
LP8788_INT_RTC_ALARM1 = 17,
LP8788_INT_RTC_ALARM2,
LP8788_INT_ENTER_SYS_SUPPORT,
LP8788_INT_EXIT_SYS_SUPPORT,
LP8788_INT_BATT_LOW,
LP8788_INT_NO_BATT,
LP8788_INT_MAX = 24,
};
enum lp8788_dvs_sel {
DVS_SEL_V0,
DVS_SEL_V1,
DVS_SEL_V2,
DVS_SEL_V3,
};
enum lp8788_ext_ldo_en_id {
EN_ALDO1,
EN_ALDO234,
EN_ALDO5,
EN_ALDO7,
EN_DLDO7,
EN_DLDO911,
EN_LDOS_MAX,
};
enum lp8788_charger_event {
NO_CHARGER,
CHARGER_DETECTED,
};
enum lp8788_bl_dim_mode {
LP8788_DIM_EXPONENTIAL,
LP8788_DIM_LINEAR,
};
enum lp8788_bl_full_scale_current {
LP8788_FULLSCALE_5000uA,
LP8788_FULLSCALE_8500uA,
LP8788_FULLSCALE_1200uA,
LP8788_FULLSCALE_1550uA,
LP8788_FULLSCALE_1900uA,
LP8788_FULLSCALE_2250uA,
LP8788_FULLSCALE_2600uA,
LP8788_FULLSCALE_2950uA,
};
enum lp8788_bl_ramp_step {
LP8788_RAMP_8us,
LP8788_RAMP_1024us,
LP8788_RAMP_2048us,
LP8788_RAMP_4096us,
LP8788_RAMP_8192us,
LP8788_RAMP_16384us,
LP8788_RAMP_32768us,
LP8788_RAMP_65538us,
};
enum lp8788_isink_scale {
LP8788_ISINK_SCALE_100mA,
LP8788_ISINK_SCALE_120mA,
};
enum lp8788_isink_number {
LP8788_ISINK_1,
LP8788_ISINK_2,
LP8788_ISINK_3,
};
enum lp8788_alarm_sel {
LP8788_ALARM_1,
LP8788_ALARM_2,
LP8788_ALARM_MAX,
};
enum lp8788_adc_id {
LPADC_VBATT_5P5,
LPADC_VIN_CHG,
LPADC_IBATT,
LPADC_IC_TEMP,
LPADC_VBATT_6P0,
LPADC_VBATT_5P0,
LPADC_ADC1,
LPADC_ADC2,
LPADC_VDD,
LPADC_VCOIN,
LPADC_VDD_LDO,
LPADC_ADC3,
LPADC_ADC4,
LPADC_MAX,
};
struct lp8788;
/*
* lp8788_buck1_dvs
* @vsel : dvs selector for buck v1 register
*/
struct lp8788_buck1_dvs {
enum lp8788_dvs_sel vsel;
};
/*
* lp8788_buck2_dvs
* @vsel : dvs selector for buck v2 register
*/
struct lp8788_buck2_dvs {
enum lp8788_dvs_sel vsel;
};
/*
* struct lp8788_chg_param
* @addr : charging control register address (range : 0x11 ~ 0x1C)
* @val : charging parameter value
*/
struct lp8788_chg_param {
u8 addr;
u8 val;
};
/*
* struct lp8788_charger_platform_data
* @adc_vbatt : adc channel name for battery voltage
* @adc_batt_temp : adc channel name for battery temperature
* @max_vbatt_mv : used for calculating battery capacity
* @chg_params : initial charging parameters
* @num_chg_params : numbers of charging parameters
* @charger_event : the charger event can be reported to the platform side
*/
struct lp8788_charger_platform_data {
const char *adc_vbatt;
const char *adc_batt_temp;
unsigned int max_vbatt_mv;
struct lp8788_chg_param *chg_params;
int num_chg_params;
void (*charger_event) (struct lp8788 *lp,
enum lp8788_charger_event event);
};
/*
* struct lp8788_led_platform_data
* @name : led driver name. (default: "keyboard-backlight")
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
*/
struct lp8788_led_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
};
/*
* struct lp8788_vib_platform_data
* @name : vibrator driver name
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
* @pwm_code : PWM code value (Addr 9Ch ~ 9Eh)
*/
struct lp8788_vib_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
int pwm_code;
};
/*
* struct lp8788_platform_data
* @init_func : used for initializing registers
* before mfd driver is registered
* @buck_data : regulator initial data for buck
* @dldo_data : regulator initial data for digital ldo
* @aldo_data : regulator initial data for analog ldo
* @buck1_dvs : configurations for buck1 dvs
* @buck2_dvs : configurations for buck2 dvs
* @chg_pdata : platform data for charger driver
* @alarm_sel : rtc alarm selection (1 or 2)
* @led_pdata : configurable data for led driver
* @vib_pdata : configurable data for vibrator driver
* @adc_pdata : iio map data for adc driver
*/
struct lp8788_platform_data {
/* general system information */
int (*init_func) (struct lp8788 *lp);
/* regulators */
struct regulator_init_data *buck_data[LP8788_NUM_BUCKS];
struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS];
struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS];
struct lp8788_buck1_dvs *buck1_dvs;
struct lp8788_buck2_dvs *buck2_dvs;
/* charger */
struct lp8788_charger_platform_data *chg_pdata;
/* rtc alarm */
enum lp8788_alarm_sel alarm_sel;
/* current sinks */
struct lp8788_led_platform_data *led_pdata;
struct lp8788_vib_platform_data *vib_pdata;
/* adc iio map data */
struct iio_map *adc_pdata;
};
/*
* struct lp8788
* @dev : parent device pointer
* @regmap : used for i2c communcation on accessing registers
* @irqdm : interrupt domain for handling nested interrupt
* @irq : pin number of IRQ_N
* @pdata : lp8788 platform specific data
*/
struct lp8788 {
struct device *dev;
struct regmap *regmap;
struct irq_domain *irqdm;
int irq;
struct lp8788_platform_data *pdata;
};
int lp8788_irq_init(struct lp8788 *lp, int chip_irq);
void lp8788_irq_exit(struct lp8788 *lp);
int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data);
int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count);
int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data);
int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data);
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/lpc_ich.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/drivers/mfd/lpc_ich.h
*
* Copyright (c) 2012 Extreme Engineering Solution, Inc.
* Author: Aaron Sierra <asierra@xes-inc.com>
*/
#ifndef LPC_ICH_H
#define LPC_ICH_H
#include <linux/platform_data/x86/spi-intel.h>
/* GPIO resources */
#define ICH_RES_GPIO 0
#define ICH_RES_GPE0 1
/* GPIO compatibility */
enum lpc_gpio_versions {
ICH_I3100_GPIO,
ICH_V5_GPIO,
ICH_V6_GPIO,
ICH_V7_GPIO,
ICH_V9_GPIO,
ICH_V10CORP_GPIO,
ICH_V10CONS_GPIO,
AVOTON_GPIO,
};
struct lpc_ich_gpio_info;
struct lpc_ich_info {
char name[32];
unsigned int iTCO_version;
enum lpc_gpio_versions gpio_version;
enum intel_spi_type spi_type;
const struct lpc_ich_gpio_info *gpio_info;
u8 use_gpio;
};
extern const struct software_node lpc_ich_gpio_swnode;
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/macsmc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* Apple SMC (System Management Controller) core definitions
*
* Copyright (C) The Asahi Linux Contributors
*/
#ifndef _LINUX_MFD_MACSMC_H
#define _LINUX_MFD_MACSMC_H
#include <linux/soc/apple/rtkit.h>
/**
* typedef smc_key - Alias for u32 to be used for SMC keys
*
* SMC keys are 32bit integers containing packed ASCII characters in natural
* integer order, i.e. 0xAABBCCDD, which represent the FourCC ABCD.
* The SMC driver is designed with this assumption and ensures the right
* endianness is used when these are stored to memory and sent to or received
* from the actual SMC firmware (which can be done in either shared memory or
* as 64bit mailbox message on Apple Silicon).
* Internally, SMC stores these keys in a table sorted lexicographically and
* allows resolving an index into this table to the corresponding SMC key.
* Thus, storing keys as u32 is very convenient as it allows to e.g. use
* normal comparison operators which directly map to the natural order used
* by SMC firmware.
*
* This simple type alias is introduced to allow easy recognition of SMC key
* variables and arguments.
*/
typedef u32 smc_key;
/**
* SMC_KEY - Convert FourCC SMC keys in source code to smc_key
*
* This macro can be used to easily define FourCC SMC keys in source code
* and convert these to u32 / smc_key, e.g. SMC_KEY(NTAP) will expand to
* 0x4e544150.
*
* @s: FourCC SMC key to be converted
*/
#define SMC_KEY(s) (smc_key)(_SMC_KEY(#s))
#define _SMC_KEY(s) (((s)[0] << 24) | ((s)[1] << 16) | ((s)[2] << 8) | (s)[3])
#define __SMC_KEY(a, b, c, d) (((u32)(a) << 24) | ((u32)(b) << 16) | ((u32)(c) << 8) | ((u32)(d)))
#define APPLE_SMC_READABLE BIT(7)
#define APPLE_SMC_WRITABLE BIT(6)
#define APPLE_SMC_FUNCTION BIT(4)
/**
* struct apple_smc_key_info - Information for a SMC key as returned by SMC
* @type_code: FourCC code indicating the type for this key.
* Known types:
* ch8*: ASCII string
* flag: Boolean, 1 or 0
* flt: 32-bit single-precision IEEE 754 float
* hex: Binary data
* ioft: 64bit Unsigned fixed-point intger (48.16)
* {si,ui}{8,16,32,64}: Signed/Unsigned 8-/16-/32-/64-bit integer
* @size: Size of the buffer associated with this key
* @flags: Bitfield encoding flags (APPLE_SMC_{READABLE,WRITABLE,FUNCTION})
*/
struct apple_smc_key_info {
u32 type_code;
u8 size;
u8 flags;
};
/**
* enum apple_smc_boot_stage - SMC boot stage
* @APPLE_SMC_BOOTING: SMC is booting
* @APPLE_SMC_INITIALIZED: SMC is initialized and ready to use
* @APPLE_SMC_ERROR_NO_SHMEM: Shared memory could not be initialized during boot
* @APPLE_SMC_ERROR_CRASHED: SMC has crashed
*/
enum apple_smc_boot_stage {
APPLE_SMC_BOOTING,
APPLE_SMC_INITIALIZED,
APPLE_SMC_ERROR_NO_SHMEM,
APPLE_SMC_ERROR_CRASHED
};
/**
* struct apple_smc
* @dev: Underlying device struct for the physical backend device
* @key_count: Number of available SMC keys
* @first_key: First valid SMC key
* @last_key: Last valid SMC key
* @event_handlers: Notifier call chain for events received from SMC
* @rtk: Pointer to Apple RTKit instance
* @init_done: Completion for initialization
* @boot_stage: Current boot stage of SMC
* @sram: Pointer to SRAM resource
* @sram_base: SRAM base address
* @shmem: RTKit shared memory structure for SRAM
* @msg_id: Current message id for commands, will be incremented for each command
* @atomic_mode: Flag set when atomic mode is entered
* @atomic_pending: Flag indicating pending atomic command
* @cmd_done: Completion for command execution in non-atomic mode
* @cmd_ret: Return value from SMC for last command
* @mutex: Mutex for non-atomic mode
* @lock: Spinlock for atomic mode
*/
struct apple_smc {
struct device *dev;
u32 key_count;
smc_key first_key;
smc_key last_key;
struct blocking_notifier_head event_handlers;
struct apple_rtkit *rtk;
struct completion init_done;
enum apple_smc_boot_stage boot_stage;
struct resource *sram;
void __iomem *sram_base;
struct apple_rtkit_shmem shmem;
unsigned int msg_id;
bool atomic_mode;
bool atomic_pending;
struct completion cmd_done;
u64 cmd_ret;
struct mutex mutex;
spinlock_t lock;
};
/**
* apple_smc_read - Read size bytes from given SMC key into buf
* @smc: Pointer to apple_smc struct
* @key: smc_key to be read
* @buf: Buffer into which size bytes of data will be read from SMC
* @size: Number of bytes to be read into buf
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_read(struct apple_smc *smc, smc_key key, void *buf, size_t size);
/**
* apple_smc_write - Write size bytes into given SMC key from buf
* @smc: Pointer to apple_smc struct
* @key: smc_key data will be written to
* @buf: Buffer from which size bytes of data will be written to SMC
* @size: Number of bytes to be written
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_write(struct apple_smc *smc, smc_key key, const void *buf, size_t size);
/**
* apple_smc_enter_atomic - Enter atomic mode to be able to use apple_smc_write_atomic
* @smc: Pointer to apple_smc struct
*
* This function switches the SMC backend to atomic mode which allows the
* use of apple_smc_write_atomic while disabling *all* other functions.
* This is only used for shutdown/reboot which requires writing to a SMC
* key from atomic context.
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_enter_atomic(struct apple_smc *smc);
/**
* apple_smc_write_atomic - Write size bytes into given SMC key from buf without sleeping
* @smc: Pointer to apple_smc struct
* @key: smc_key data will be written to
* @buf: Buffer from which size bytes of data will be written to SMC
* @size: Number of bytes to be written
*
* Note that this function will fail if apple_smc_enter_atomic hasn't been
* called before.
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_write_atomic(struct apple_smc *smc, smc_key key, const void *buf, size_t size);
/**
* apple_smc_rw - Write and then read using the given SMC key
* @smc: Pointer to apple_smc struct
* @key: smc_key data will be written to
* @wbuf: Buffer from which size bytes of data will be written to SMC
* @wsize: Number of bytes to be written
* @rbuf: Buffer to which size bytes of data will be read from SMC
* @rsize: Number of bytes to be read
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_rw(struct apple_smc *smc, smc_key key, const void *wbuf, size_t wsize,
void *rbuf, size_t rsize);
/**
* apple_smc_get_key_by_index - Given an index return the corresponding SMC key
* @smc: Pointer to apple_smc struct
* @index: Index to be resolved
* @key: Buffer for SMC key to be returned
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_get_key_by_index(struct apple_smc *smc, int index, smc_key *key);
/**
* apple_smc_get_key_info - Get key information from SMC
* @smc: Pointer to apple_smc struct
* @key: Key to acquire information for
* @info: Pointer to struct apple_smc_key_info which will be filled
*
* Return: Zero on success, negative errno on error
*/
int apple_smc_get_key_info(struct apple_smc *smc, smc_key key, struct apple_smc_key_info *info);
/**
* apple_smc_key_exists - Check if the given SMC key exists
* @smc: Pointer to apple_smc struct
* @key: smc_key to be checked
*
* Return: True if the key exists, false otherwise
*/
static inline bool apple_smc_key_exists(struct apple_smc *smc, smc_key key)
{
return apple_smc_get_key_info(smc, key, NULL) >= 0;
}
#define APPLE_SMC_TYPE_OPS(type) \
static inline int apple_smc_read_##type(struct apple_smc *smc, smc_key key, type *p) \
{ \
int ret = apple_smc_read(smc, key, p, sizeof(*p)); \
return (ret < 0) ? ret : ((ret != sizeof(*p)) ? -EINVAL : 0); \
} \
static inline int apple_smc_write_##type(struct apple_smc *smc, smc_key key, type p) \
{ \
return apple_smc_write(smc, key, &p, sizeof(p)); \
} \
static inline int apple_smc_write_##type##_atomic(struct apple_smc *smc, smc_key key, type p) \
{ \
return apple_smc_write_atomic(smc, key, &p, sizeof(p)); \
} \
static inline int apple_smc_rw_##type(struct apple_smc *smc, smc_key key, \
type w, type *r) \
{ \
int ret = apple_smc_rw(smc, key, &w, sizeof(w), r, sizeof(*r)); \
return (ret < 0) ? ret : ((ret != sizeof(*r)) ? -EINVAL : 0); \
}
APPLE_SMC_TYPE_OPS(u64)
APPLE_SMC_TYPE_OPS(u32)
APPLE_SMC_TYPE_OPS(u16)
APPLE_SMC_TYPE_OPS(u8)
APPLE_SMC_TYPE_OPS(s64)
APPLE_SMC_TYPE_OPS(s32)
APPLE_SMC_TYPE_OPS(s16)
APPLE_SMC_TYPE_OPS(s8)
static inline int apple_smc_read_flag(struct apple_smc *smc, smc_key key, bool *flag)
{
u8 val;
int ret = apple_smc_read_u8(smc, key, &val);
if (ret < 0)
return ret;
*flag = val ? true : false;
return ret;
}
static inline int apple_smc_write_flag(struct apple_smc *smc, smc_key key, bool state)
{
return apple_smc_write_u8(smc, key, state ? 1 : 0);
}
static inline int apple_smc_write_flag_atomic(struct apple_smc *smc, smc_key key, bool state)
{
return apple_smc_write_u8_atomic(smc, key, state ? 1 : 0);
}
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/madera/core.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MFD internals for Cirrus Logic Madera codecs
*
* Copyright (C) 2015-2018 Cirrus Logic
*/
#ifndef MADERA_CORE_H
#define MADERA_CORE_H
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/madera/pdata.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
enum madera_type {
/* 0 is reserved for indicating failure to identify */
CS47L35 = 1,
CS47L85 = 2,
CS47L90 = 3,
CS47L91 = 4,
CS47L92 = 5,
CS47L93 = 6,
WM1840 = 7,
CS47L15 = 8,
CS42L92 = 9,
};
enum {
MADERA_MCLK1,
MADERA_MCLK2,
MADERA_MCLK3,
MADERA_NUM_MCLK
};
#define MADERA_MAX_CORE_SUPPLIES 2
#define MADERA_MAX_GPIOS 40
#define CS47L15_NUM_GPIOS 15
#define CS47L35_NUM_GPIOS 16
#define CS47L85_NUM_GPIOS 40
#define CS47L90_NUM_GPIOS 38
#define CS47L92_NUM_GPIOS 16
#define MADERA_MAX_MICBIAS 4
#define MADERA_MAX_HP_OUTPUT 3
/* Notifier events */
#define MADERA_NOTIFY_VOICE_TRIGGER 0x1
#define MADERA_NOTIFY_HPDET 0x2
#define MADERA_NOTIFY_MICDET 0x4
/* GPIO Function Definitions */
#define MADERA_GP_FN_ALTERNATE 0x00
#define MADERA_GP_FN_GPIO 0x01
#define MADERA_GP_FN_DSP_GPIO 0x02
#define MADERA_GP_FN_IRQ1 0x03
#define MADERA_GP_FN_IRQ2 0x04
#define MADERA_GP_FN_FLL1_CLOCK 0x10
#define MADERA_GP_FN_FLL2_CLOCK 0x11
#define MADERA_GP_FN_FLL3_CLOCK 0x12
#define MADERA_GP_FN_FLLAO_CLOCK 0x13
#define MADERA_GP_FN_FLL1_LOCK 0x18
#define MADERA_GP_FN_FLL2_LOCK 0x19
#define MADERA_GP_FN_FLL3_LOCK 0x1A
#define MADERA_GP_FN_FLLAO_LOCK 0x1B
#define MADERA_GP_FN_OPCLK_OUT 0x40
#define MADERA_GP_FN_OPCLK_ASYNC_OUT 0x41
#define MADERA_GP_FN_PWM1 0x48
#define MADERA_GP_FN_PWM2 0x49
#define MADERA_GP_FN_SPDIF_OUT 0x4C
#define MADERA_GP_FN_HEADPHONE_DET 0x50
#define MADERA_GP_FN_MIC_DET 0x58
#define MADERA_GP_FN_DRC1_SIGNAL_DETECT 0x80
#define MADERA_GP_FN_DRC2_SIGNAL_DETECT 0x81
#define MADERA_GP_FN_ASRC1_IN1_LOCK 0x88
#define MADERA_GP_FN_ASRC1_IN2_LOCK 0x89
#define MADERA_GP_FN_ASRC2_IN1_LOCK 0x8A
#define MADERA_GP_FN_ASRC2_IN2_LOCK 0x8B
#define MADERA_GP_FN_DSP_IRQ1 0xA0
#define MADERA_GP_FN_DSP_IRQ2 0xA1
#define MADERA_GP_FN_DSP_IRQ3 0xA2
#define MADERA_GP_FN_DSP_IRQ4 0xA3
#define MADERA_GP_FN_DSP_IRQ5 0xA4
#define MADERA_GP_FN_DSP_IRQ6 0xA5
#define MADERA_GP_FN_DSP_IRQ7 0xA6
#define MADERA_GP_FN_DSP_IRQ8 0xA7
#define MADERA_GP_FN_DSP_IRQ9 0xA8
#define MADERA_GP_FN_DSP_IRQ10 0xA9
#define MADERA_GP_FN_DSP_IRQ11 0xAA
#define MADERA_GP_FN_DSP_IRQ12 0xAB
#define MADERA_GP_FN_DSP_IRQ13 0xAC
#define MADERA_GP_FN_DSP_IRQ14 0xAD
#define MADERA_GP_FN_DSP_IRQ15 0xAE
#define MADERA_GP_FN_DSP_IRQ16 0xAF
#define MADERA_GP_FN_HPOUT1L_SC 0xB0
#define MADERA_GP_FN_HPOUT1R_SC 0xB1
#define MADERA_GP_FN_HPOUT2L_SC 0xB2
#define MADERA_GP_FN_HPOUT2R_SC 0xB3
#define MADERA_GP_FN_HPOUT3L_SC 0xB4
#define MADERA_GP_FN_HPOUT4R_SC 0xB5
#define MADERA_GP_FN_SPKOUTL_SC 0xB6
#define MADERA_GP_FN_SPKOUTR_SC 0xB7
#define MADERA_GP_FN_HPOUT1L_ENA 0xC0
#define MADERA_GP_FN_HPOUT1R_ENA 0xC1
#define MADERA_GP_FN_HPOUT2L_ENA 0xC2
#define MADERA_GP_FN_HPOUT2R_ENA 0xC3
#define MADERA_GP_FN_HPOUT3L_ENA 0xC4
#define MADERA_GP_FN_HPOUT4R_ENA 0xC5
#define MADERA_GP_FN_SPKOUTL_ENA 0xC6
#define MADERA_GP_FN_SPKOUTR_ENA 0xC7
#define MADERA_GP_FN_HPOUT1L_DIS 0xD0
#define MADERA_GP_FN_HPOUT1R_DIS 0xD1
#define MADERA_GP_FN_HPOUT2L_DIS 0xD2
#define MADERA_GP_FN_HPOUT2R_DIS 0xD3
#define MADERA_GP_FN_HPOUT3L_DIS 0xD4
#define MADERA_GP_FN_HPOUT4R_DIS 0xD5
#define MADERA_GP_FN_SPKOUTL_DIS 0xD6
#define MADERA_GP_FN_SPKOUTR_DIS 0xD7
#define MADERA_GP_FN_SPK_SHUTDOWN 0xE0
#define MADERA_GP_FN_SPK_OVH_SHUTDOWN 0xE1
#define MADERA_GP_FN_SPK_OVH_WARN 0xE2
#define MADERA_GP_FN_TIMER1_STATUS 0x140
#define MADERA_GP_FN_TIMER2_STATUS 0x141
#define MADERA_GP_FN_TIMER3_STATUS 0x142
#define MADERA_GP_FN_TIMER4_STATUS 0x143
#define MADERA_GP_FN_TIMER5_STATUS 0x144
#define MADERA_GP_FN_TIMER6_STATUS 0x145
#define MADERA_GP_FN_TIMER7_STATUS 0x146
#define MADERA_GP_FN_TIMER8_STATUS 0x147
#define MADERA_GP_FN_EVENTLOG1_FIFO_STS 0x150
#define MADERA_GP_FN_EVENTLOG2_FIFO_STS 0x151
#define MADERA_GP_FN_EVENTLOG3_FIFO_STS 0x152
#define MADERA_GP_FN_EVENTLOG4_FIFO_STS 0x153
#define MADERA_GP_FN_EVENTLOG5_FIFO_STS 0x154
#define MADERA_GP_FN_EVENTLOG6_FIFO_STS 0x155
#define MADERA_GP_FN_EVENTLOG7_FIFO_STS 0x156
#define MADERA_GP_FN_EVENTLOG8_FIFO_STS 0x157
struct snd_soc_dapm_context;
/*
* struct madera - internal data shared by the set of Madera drivers
*
* This should not be used by anything except child drivers of the Madera MFD
*
* @regmap: pointer to the regmap instance for 16-bit registers
* @regmap_32bit: pointer to the regmap instance for 32-bit registers
* @dev: pointer to the MFD device
* @type: type of codec
* @rev: silicon revision
* @type_name: display name of this codec
* @num_core_supplies: number of core supply regulators
* @core_supplies: list of core supplies that are always required
* @dcvdd: pointer to DCVDD regulator
* @internal_dcvdd: true if DCVDD is supplied from the internal LDO1
* @pdata: our pdata
* @irq_dev: the irqchip child driver device
* @irq_data: pointer to irqchip data for the child irqchip driver
* @irq: host irq number from SPI or I2C configuration
* @mclk: Structure holding clock supplies
* @out_clamp: indicates output clamp state for each analogue output
* @out_shorted: indicates short circuit state for each analogue output
* @hp_ena: bitflags of enable state for the headphone outputs
* @num_micbias: number of MICBIAS outputs
* @num_childbias: number of child biases for each MICBIAS
* @dapm: pointer to codec driver DAPM context
* @notifier: notifier for signalling events to ASoC machine driver
*/
struct madera {
struct regmap *regmap;
struct regmap *regmap_32bit;
struct device *dev;
enum madera_type type;
unsigned int rev;
const char *type_name;
int num_core_supplies;
struct regulator_bulk_data core_supplies[MADERA_MAX_CORE_SUPPLIES];
struct regulator *dcvdd;
bool internal_dcvdd;
bool reset_errata;
struct madera_pdata pdata;
struct device *irq_dev;
struct regmap_irq_chip_data *irq_data;
int irq;
struct clk_bulk_data mclk[MADERA_NUM_MCLK];
unsigned int num_micbias;
unsigned int num_childbias[MADERA_MAX_MICBIAS];
struct snd_soc_dapm_context *dapm;
struct mutex dapm_ptr_lock;
unsigned int hp_ena;
bool out_clamp[MADERA_MAX_HP_OUTPUT];
bool out_shorted[MADERA_MAX_HP_OUTPUT];
struct blocking_notifier_head notifier;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/madera/pdata.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Platform data for Cirrus Logic Madera codecs
*
* Copyright (C) 2015-2018 Cirrus Logic
*/
#ifndef MADERA_PDATA_H
#define MADERA_PDATA_H
#include <linux/regulator/arizona-ldo1.h>
#include <linux/regulator/arizona-micsupp.h>
#include <linux/regulator/machine.h>
#include <linux/types.h>
#include <sound/madera-pdata.h>
#define MADERA_MAX_MICBIAS 4
#define MADERA_MAX_CHILD_MICBIAS 4
#define MADERA_MAX_GPSW 2
struct gpio_desc;
struct pinctrl_map;
/**
* struct madera_pdata - Configuration data for Madera devices
*
* @reset: GPIO controlling /RESET (NULL = none)
* @ldo1: Substruct of pdata for the LDO1 regulator
* @micvdd: Substruct of pdata for the MICVDD regulator
* @irq_flags: Mode for primary IRQ (defaults to active low)
* @gpio_base: Base GPIO number
* @gpio_configs: Array of GPIO configurations (See
* Documentation/driver-api/pin-control.rst)
* @n_gpio_configs: Number of entries in gpio_configs
* @gpsw: General purpose switch mode setting. Depends on the external
* hardware connected to the switch. (See the SW1_MODE field
* in the datasheet for the available values for your codec)
* @codec: Substruct of pdata for the ASoC codec driver
*/
struct madera_pdata {
struct gpio_desc *reset;
struct arizona_ldo1_pdata ldo1;
struct arizona_micsupp_pdata micvdd;
unsigned int irq_flags;
int gpio_base;
const struct pinctrl_map *gpio_configs;
int n_gpio_configs;
u32 gpsw[MADERA_MAX_GPSW];
struct madera_codec_pdata codec;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/madera/registers.h
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local/recipes/gpu/amdgpu-source/include/linux/mfd/max14577-private.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
*
* Copyright (C) 2014 Samsung Electronics
* Chanwoo Choi <cw00.choi@samsung.com>
* Krzysztof Kozlowski <krzk@kernel.org>
*/
#ifndef __MAX14577_PRIVATE_H__
#define __MAX14577_PRIVATE_H__
#include <linux/i2c.h>
#include <linux/regmap.h>
#define I2C_ADDR_PMIC (0x46 >> 1)
#define I2C_ADDR_MUIC (0x4A >> 1)
#define I2C_ADDR_FG (0x6C >> 1)
enum maxim_device_type {
MAXIM_DEVICE_TYPE_UNKNOWN = 0,
MAXIM_DEVICE_TYPE_MAX14577,
MAXIM_DEVICE_TYPE_MAX77836,
MAXIM_DEVICE_TYPE_NUM,
};
/* Slave addr = 0x4A: MUIC and Charger */
enum max14577_reg {
MAX14577_REG_DEVICEID = 0x00,
MAX14577_REG_INT1 = 0x01,
MAX14577_REG_INT2 = 0x02,
MAX14577_REG_INT3 = 0x03,
MAX14577_REG_STATUS1 = 0x04,
MAX14577_REG_STATUS2 = 0x05,
MAX14577_REG_STATUS3 = 0x06,
MAX14577_REG_INTMASK1 = 0x07,
MAX14577_REG_INTMASK2 = 0x08,
MAX14577_REG_INTMASK3 = 0x09,
MAX14577_REG_CDETCTRL1 = 0x0A,
MAX14577_REG_RFU = 0x0B,
MAX14577_REG_CONTROL1 = 0x0C,
MAX14577_REG_CONTROL2 = 0x0D,
MAX14577_REG_CONTROL3 = 0x0E,
MAX14577_REG_CHGCTRL1 = 0x0F,
MAX14577_REG_CHGCTRL2 = 0x10,
MAX14577_REG_CHGCTRL3 = 0x11,
MAX14577_REG_CHGCTRL4 = 0x12,
MAX14577_REG_CHGCTRL5 = 0x13,
MAX14577_REG_CHGCTRL6 = 0x14,
MAX14577_REG_CHGCTRL7 = 0x15,
MAX14577_REG_END,
};
/* Slave addr = 0x4A: MUIC */
enum max14577_muic_reg {
MAX14577_MUIC_REG_STATUS1 = 0x04,
MAX14577_MUIC_REG_STATUS2 = 0x05,
MAX14577_MUIC_REG_CONTROL1 = 0x0C,
MAX14577_MUIC_REG_CONTROL3 = 0x0E,
MAX14577_MUIC_REG_END,
};
/*
* Combined charger types for max14577 and max77836.
*
* On max14577 three lower bits map to STATUS2/CHGTYP field.
* However the max77836 has different two last values of STATUS2/CHGTYP.
* To indicate the difference enum has two additional values for max77836.
* These values are just a register value bitwise OR with 0x8.
*/
enum max14577_muic_charger_type {
MAX14577_CHARGER_TYPE_NONE = 0x0,
MAX14577_CHARGER_TYPE_USB = 0x1,
MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT = 0x2,
MAX14577_CHARGER_TYPE_DEDICATED_CHG = 0x3,
MAX14577_CHARGER_TYPE_SPECIAL_500MA = 0x4,
/* Special 1A or 2A charger */
MAX14577_CHARGER_TYPE_SPECIAL_1A = 0x5,
/* max14577: reserved, used on max77836 */
MAX14577_CHARGER_TYPE_RESERVED = 0x6,
/* max14577: dead-battery charing with maximum current 100mA */
MAX14577_CHARGER_TYPE_DEAD_BATTERY = 0x7,
/*
* max77836: special charger (bias on D+/D-),
* matches register value of 0x6
*/
MAX77836_CHARGER_TYPE_SPECIAL_BIAS = 0xe,
/* max77836: reserved, register value 0x7 */
MAX77836_CHARGER_TYPE_RESERVED = 0xf,
};
/* MAX14577 interrupts */
#define MAX14577_INT1_ADC_MASK BIT(0)
#define MAX14577_INT1_ADCLOW_MASK BIT(1)
#define MAX14577_INT1_ADCERR_MASK BIT(2)
#define MAX77836_INT1_ADC1K_MASK BIT(3)
#define MAX14577_INT2_CHGTYP_MASK BIT(0)
#define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
#define MAX14577_INT2_DCDTMR_MASK BIT(2)
#define MAX14577_INT2_DBCHG_MASK BIT(3)
#define MAX14577_INT2_VBVOLT_MASK BIT(4)
#define MAX77836_INT2_VIDRM_MASK BIT(5)
#define MAX14577_INT3_EOC_MASK BIT(0)
#define MAX14577_INT3_CGMBC_MASK BIT(1)
#define MAX14577_INT3_OVP_MASK BIT(2)
#define MAX14577_INT3_MBCCHGERR_MASK BIT(3)
/* MAX14577 DEVICE ID register */
#define DEVID_VENDORID_SHIFT 0
#define DEVID_DEVICEID_SHIFT 3
#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT)
#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT)
/* MAX14577 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCLOW_SHIFT 5
#define STATUS1_ADCERR_SHIFT 6
#define MAX77836_STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT)
#define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
/* MAX14577 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define MAX14577_STATUS2_DBCHG_SHIFT 5
#define MAX77836_STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define MAX77836_STATUS2_VIDRM_SHIFT 7
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
#define MAX14577_STATUS2_DBCHG_MASK BIT(MAX14577_STATUS2_DBCHG_SHIFT)
#define MAX77836_STATUS2_DXOVP_MASK BIT(MAX77836_STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
#define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
/* MAX14577 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define MICEN_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define MICEN_MASK BIT(MICEN_SHIFT)
#define IDBEN_MASK BIT(IDBEN_SHIFT)
#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
| (1 << COMN1SW_SHIFT))
#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
| (2 << COMN1SW_SHIFT))
#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \
| (3 << COMN1SW_SHIFT))
#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
| (0 << COMN1SW_SHIFT))
/* MAX14577 CONTROL2 register */
#define CTRL2_LOWPWR_SHIFT (0)
#define CTRL2_ADCEN_SHIFT (1)
#define CTRL2_CPEN_SHIFT (2)
#define CTRL2_SFOUTASRT_SHIFT (3)
#define CTRL2_SFOUTORD_SHIFT (4)
#define CTRL2_ACCDET_SHIFT (5)
#define CTRL2_USBCPINT_SHIFT (6)
#define CTRL2_RCPS_SHIFT (7)
#define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT)
#define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT)
#define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT)
#define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT)
#define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT)
#define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT)
#define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT)
#define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT)
#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
(0 << CTRL2_LOWPWR_SHIFT))
#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
(1 << CTRL2_LOWPWR_SHIFT))
/* MAX14577 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_BOOTSET_SHIFT 2
#define CTRL3_ADCDBSET_SHIFT 4
#define CTRL3_WBTH_SHIFT 6
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
#define CTRL3_WBTH_MASK (0x3 << CTRL3_WBTH_SHIFT)
/* Slave addr = 0x4A: Charger */
enum max14577_charger_reg {
MAX14577_CHG_REG_STATUS3 = 0x06,
MAX14577_CHG_REG_CHG_CTRL1 = 0x0F,
MAX14577_CHG_REG_CHG_CTRL2 = 0x10,
MAX14577_CHG_REG_CHG_CTRL3 = 0x11,
MAX14577_CHG_REG_CHG_CTRL4 = 0x12,
MAX14577_CHG_REG_CHG_CTRL5 = 0x13,
MAX14577_CHG_REG_CHG_CTRL6 = 0x14,
MAX14577_CHG_REG_CHG_CTRL7 = 0x15,
MAX14577_CHG_REG_END,
};
/* MAX14577 STATUS3 register */
#define STATUS3_EOC_SHIFT 0
#define STATUS3_CGMBC_SHIFT 1
#define STATUS3_OVP_SHIFT 2
#define STATUS3_MBCCHGERR_SHIFT 3
#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT)
#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT)
#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT)
/* MAX14577 CDETCTRL1 register */
#define CDETCTRL1_CHGDETEN_SHIFT 0
#define CDETCTRL1_CHGTYPMAN_SHIFT 1
#define CDETCTRL1_DCDEN_SHIFT 2
#define CDETCTRL1_DCD2SCT_SHIFT 3
#define MAX14577_CDETCTRL1_DCHKTM_SHIFT 4
#define MAX77836_CDETCTRL1_CDLY_SHIFT 4
#define MAX14577_CDETCTRL1_DBEXIT_SHIFT 5
#define MAX77836_CDETCTRL1_DCDCPL_SHIFT 5
#define CDETCTRL1_DBIDLE_SHIFT 6
#define CDETCTRL1_CDPDET_SHIFT 7
#define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT)
#define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
#define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT)
#define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT)
#define MAX14577_CDETCTRL1_DCHKTM_MASK BIT(MAX14577_CDETCTRL1_DCHKTM_SHIFT)
#define MAX77836_CDETCTRL1_CDDLY_MASK BIT(MAX77836_CDETCTRL1_CDDLY_SHIFT)
#define MAX14577_CDETCTRL1_DBEXIT_MASK BIT(MAX14577_CDETCTRL1_DBEXIT_SHIFT)
#define MAX77836_CDETCTRL1_DCDCPL_MASK BIT(MAX77836_CDETCTRL1_DCDCPL_SHIFT)
#define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT)
#define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT)
/* MAX14577 CHGCTRL1 register */
#define CHGCTRL1_TCHW_SHIFT 4
#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT)
/* MAX14577 CHGCTRL2 register */
#define CHGCTRL2_MBCHOSTEN_SHIFT 6
#define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
#define CHGCTRL2_VCHGR_RC_SHIFT 7
#define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT)
/* MAX14577 CHGCTRL3 register */
#define CHGCTRL3_MBCCVWRC_SHIFT 0
#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
/* MAX14577 CHGCTRL4 register */
#define CHGCTRL4_MBCICHWRCH_SHIFT 0
#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
#define CHGCTRL4_MBCICHWRCL_SHIFT 4
#define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
/* MAX14577 CHGCTRL5 register */
#define CHGCTRL5_EOCS_SHIFT 0
#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT)
/* MAX14577 CHGCTRL6 register */
#define CHGCTRL6_AUTOSTOP_SHIFT 5
#define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT)
/* MAX14577 CHGCTRL7 register */
#define CHGCTRL7_OTPCGHCVS_SHIFT 0
#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
/* MAX14577 charger current limits (as in CHGCTRL4 register), uA */
#define MAX14577_CHARGER_CURRENT_LIMIT_MIN 90000U
#define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START 200000U
#define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP 50000U
#define MAX14577_CHARGER_CURRENT_LIMIT_MAX 950000U
/* MAX77836 charger current limits (as in CHGCTRL4 register), uA */
#define MAX77836_CHARGER_CURRENT_LIMIT_MIN 45000U
#define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START 100000U
#define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP 25000U
#define MAX77836_CHARGER_CURRENT_LIMIT_MAX 475000U
/*
* MAX14577 charger End-Of-Charge current limits
* (as in CHGCTRL5 register), uA
*/
#define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MIN 50000U
#define MAX14577_CHARGER_EOC_CURRENT_LIMIT_STEP 10000U
#define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MAX 200000U
/*
* MAX14577/MAX77836 Battery Constant Voltage
* (as in CHGCTRL3 register), uV
*/
#define MAXIM_CHARGER_CONSTANT_VOLTAGE_MIN 4000000U
#define MAXIM_CHARGER_CONSTANT_VOLTAGE_STEP 20000U
#define MAXIM_CHARGER_CONSTANT_VOLTAGE_MAX 4350000U
/* Default value for fast charge timer, in hours */
#define MAXIM_CHARGER_FAST_CHARGE_TIMER_DEFAULT 5
/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
/* MAX77836 regulator LDOx voltage, uV */
#define MAX77836_REGULATOR_LDO_VOLTAGE_MIN 800000
#define MAX77836_REGULATOR_LDO_VOLTAGE_MAX 3950000
#define MAX77836_REGULATOR_LDO_VOLTAGE_STEP 50000
#define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM 64
/* Slave addr = 0x46: PMIC */
enum max77836_pmic_reg {
MAX77836_PMIC_REG_PMIC_ID = 0x20,
MAX77836_PMIC_REG_PMIC_REV = 0x21,
MAX77836_PMIC_REG_INTSRC = 0x22,
MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
MAX77836_PMIC_REG_LSCNFG = 0x2B,
MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
MAX77836_COMP_REG_COMP1 = 0x60,
MAX77836_PMIC_REG_END,
};
#define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1
#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
#define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
/* MAX77836 PMIC interrupts */
#define MAX77836_TOPSYS_INT_T120C_SHIFT 0
#define MAX77836_TOPSYS_INT_T140C_SHIFT 1
#define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
#define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
/* LDO1/LDO2 CONFIG1 register */
#define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6
#define MAX77836_CNFG1_LDO_TV_SHIFT 0
#define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
#define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
/* LDO1/LDO2 CONFIG2 register */
#define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT 7
#define MAX77836_CNFG2_LDO_ALPMEN_SHIFT 6
#define MAX77836_CNFG2_LDO_COMP_SHIFT 4
#define MAX77836_CNFG2_LDO_POK_SHIFT 3
#define MAX77836_CNFG2_LDO_ADE_SHIFT 1
#define MAX77836_CNFG2_LDO_SS_SHIFT 0
#define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
#define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
#define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
#define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
#define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
#define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
/* Slave addr = 0x6C: Fuel-Gauge/Battery */
enum max77836_fg_reg {
MAX77836_FG_REG_VCELL_MSB = 0x02,
MAX77836_FG_REG_VCELL_LSB = 0x03,
MAX77836_FG_REG_SOC_MSB = 0x04,
MAX77836_FG_REG_SOC_LSB = 0x05,
MAX77836_FG_REG_MODE_H = 0x06,
MAX77836_FG_REG_MODE_L = 0x07,
MAX77836_FG_REG_VERSION_MSB = 0x08,
MAX77836_FG_REG_VERSION_LSB = 0x09,
MAX77836_FG_REG_HIBRT_H = 0x0A,
MAX77836_FG_REG_HIBRT_L = 0x0B,
MAX77836_FG_REG_CONFIG_H = 0x0C,
MAX77836_FG_REG_CONFIG_L = 0x0D,
MAX77836_FG_REG_VALRT_MIN = 0x14,
MAX77836_FG_REG_VALRT_MAX = 0x15,
MAX77836_FG_REG_CRATE_MSB = 0x16,
MAX77836_FG_REG_CRATE_LSB = 0x17,
MAX77836_FG_REG_VRESET = 0x18,
MAX77836_FG_REG_FGID = 0x19,
MAX77836_FG_REG_STATUS_H = 0x1A,
MAX77836_FG_REG_STATUS_L = 0x1B,
/*
* TODO: TABLE registers
* TODO: CMD register
*/
MAX77836_FG_REG_END,
};
enum max14577_irq {
/* INT1 */
MAX14577_IRQ_INT1_ADC,
MAX14577_IRQ_INT1_ADCLOW,
MAX14577_IRQ_INT1_ADCERR,
MAX77836_IRQ_INT1_ADC1K,
/* INT2 */
MAX14577_IRQ_INT2_CHGTYP,
MAX14577_IRQ_INT2_CHGDETRUN,
MAX14577_IRQ_INT2_DCDTMR,
MAX14577_IRQ_INT2_DBCHG,
MAX14577_IRQ_INT2_VBVOLT,
MAX77836_IRQ_INT2_VIDRM,
/* INT3 */
MAX14577_IRQ_INT3_EOC,
MAX14577_IRQ_INT3_CGMBC,
MAX14577_IRQ_INT3_OVP,
MAX14577_IRQ_INT3_MBCCHGERR,
/* TOPSYS_INT, only MAX77836 */
MAX77836_IRQ_TOPSYS_T140C,
MAX77836_IRQ_TOPSYS_T120C,
MAX14577_IRQ_NUM,
};
struct max14577 {
struct device *dev;
struct i2c_client *i2c; /* Slave addr = 0x4A */
struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
enum maxim_device_type dev_type;
struct regmap *regmap; /* For MUIC and Charger */
struct regmap *regmap_pmic;
struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
struct regmap_irq_chip_data *irq_data_pmic;
int irq;
};
/* MAX14577 shared regmap API function */
static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
{
unsigned int val;
int ret;
ret = regmap_read(map, reg, &val);
*dest = val;
return ret;
}
static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
int count)
{
return regmap_bulk_read(map, reg, buf, count);
}
static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
{
return regmap_write(map, reg, value);
}
static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
int count)
{
return regmap_bulk_write(map, reg, buf, count);
}
static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
u8 val)
{
return regmap_update_bits(map, reg, mask, val);
}
#endif /* __MAX14577_PRIVATE_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max14577.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max14577.h - Driver for the Maxim 14577/77836
*
* Copyright (C) 2014 Samsung Electronics
* Chanwoo Choi <cw00.choi@samsung.com>
* Krzysztof Kozlowski <krzk@kernel.org>
*
* This driver is based on max8997.h
*
* MAX14577 has MUIC, Charger devices.
* The devices share the same I2C bus and interrupt line
* included in this mfd driver.
*
* MAX77836 has additional PMIC and Fuel-Gauge on different I2C slave
* addresses.
*/
#ifndef __MAX14577_H__
#define __MAX14577_H__
#include <linux/regulator/consumer.h>
/* MAX14577 regulator IDs */
enum max14577_regulators {
MAX14577_SAFEOUT = 0,
MAX14577_CHARGER,
MAX14577_REGULATOR_NUM,
};
/* MAX77836 regulator IDs */
enum max77836_regulators {
MAX77836_SAFEOUT = 0,
MAX77836_CHARGER,
MAX77836_LDO1,
MAX77836_LDO2,
MAX77836_REGULATOR_NUM,
};
struct max14577_regulator_platform_data {
int id;
struct regulator_init_data *initdata;
struct device_node *of_node;
};
struct max14577_charger_platform_data {
u32 constant_uvolt;
u32 fast_charge_uamp;
u32 eoc_uamp;
u32 ovp_uvolt;
};
/*
* MAX14577 MFD platform data
*/
struct max14577_platform_data {
/* IRQ */
int irq_base;
/* current control GPIOs */
int gpio_pogo_vbatt_en;
int gpio_pogo_vbus_en;
/* current control GPIO control function */
int (*set_gpio_pogo_vbatt_en) (int gpio_val);
int (*set_gpio_pogo_vbus_en) (int gpio_val);
int (*set_gpio_pogo_cb) (int new_dev);
struct max14577_regulator_platform_data *regulators;
};
/*
* Valid limits of current for max14577 and max77836 chargers.
* They must correspond to MBCICHWRCL and MBCICHWRCH fields in CHGCTRL4
* register for given chipset.
*/
struct maxim_charger_current {
/* Minimal current, set in CHGCTRL4/MBCICHWRCL, uA */
unsigned int min;
/*
* Minimal current when high setting is active,
* set in CHGCTRL4/MBCICHWRCH, uA
*/
unsigned int high_start;
/* Value of one step in high setting, uA */
unsigned int high_step;
/* Maximum current of high setting, uA */
unsigned int max;
};
extern const struct maxim_charger_current maxim_charger_currents[];
extern int maxim_charger_calc_reg_current(const struct maxim_charger_current *limits,
unsigned int min_ua, unsigned int max_ua, u8 *dst);
#endif /* __MAX14577_H__ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max5970.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device driver for regulators in MAX5970 and MAX5978 IC
*
* Copyright (c) 2022 9elements GmbH
*
* Author: Patrick Rudolph <patrick.rudolph@9elements.com>
*/
#ifndef _MFD_MAX5970_H
#define _MFD_MAX5970_H
#include <linux/regmap.h>
#define MAX5970_NUM_SWITCHES 2
#define MAX5978_NUM_SWITCHES 1
#define MAX5970_NUM_LEDS 4
#define MAX5970_REG_CURRENT_L(ch) (0x01 + (ch) * 4)
#define MAX5970_REG_CURRENT_H(ch) (0x00 + (ch) * 4)
#define MAX5970_REG_VOLTAGE_L(ch) (0x03 + (ch) * 4)
#define MAX5970_REG_VOLTAGE_H(ch) (0x02 + (ch) * 4)
#define MAX5970_REG_MON_RANGE 0x18
#define MAX5970_MON_MASK 0x3
#define MAX5970_MON(reg, ch) (((reg) >> ((ch) * 2)) & MAX5970_MON_MASK)
#define MAX5970_MON_MAX_RANGE_UV 16000000
#define MAX5970_REG_CH_UV_WARN_H(ch) (0x1A + (ch) * 10)
#define MAX5970_REG_CH_UV_WARN_L(ch) (0x1B + (ch) * 10)
#define MAX5970_REG_CH_UV_CRIT_H(ch) (0x1C + (ch) * 10)
#define MAX5970_REG_CH_UV_CRIT_L(ch) (0x1D + (ch) * 10)
#define MAX5970_REG_CH_OV_WARN_H(ch) (0x1E + (ch) * 10)
#define MAX5970_REG_CH_OV_WARN_L(ch) (0x1F + (ch) * 10)
#define MAX5970_REG_CH_OV_CRIT_H(ch) (0x20 + (ch) * 10)
#define MAX5970_REG_CH_OV_CRIT_L(ch) (0x21 + (ch) * 10)
#define MAX5970_VAL2REG_H(x) (((x) >> 2) & 0xFF)
#define MAX5970_VAL2REG_L(x) ((x) & 0x3)
#define MAX5970_REG_DAC_FAST(ch) (0x2E + (ch))
#define MAX5970_FAST2SLOW_RATIO 200
#define MAX5970_REG_STATUS0 0x31
#define MAX5970_CB_IFAULTF(ch) (1 << (ch))
#define MAX5970_CB_IFAULTS(ch) (1 << ((ch) + 4))
#define MAX5970_REG_STATUS1 0x32
#define STATUS1_PROT_MASK 0x3
#define STATUS1_PROT(reg) \
(((reg) >> 6) & STATUS1_PROT_MASK)
#define STATUS1_PROT_SHUTDOWN 0
#define STATUS1_PROT_CLEAR_PG 1
#define STATUS1_PROT_ALERT_ONLY 2
#define MAX5970_REG_STATUS2 0x33
#define MAX5970_IRNG_MASK 0x3
#define MAX5970_IRNG(reg, ch) \
(((reg) >> ((ch) * 2)) & MAX5970_IRNG_MASK)
#define MAX5970_REG_STATUS3 0x34
#define MAX5970_STATUS3_ALERT BIT(4)
#define MAX5970_STATUS3_PG(ch) BIT(ch)
#define MAX5970_REG_FAULT0 0x35
#define UV_STATUS_WARN(ch) (1 << (ch))
#define UV_STATUS_CRIT(ch) (1 << ((ch) + 4))
#define MAX5970_REG_FAULT1 0x36
#define OV_STATUS_WARN(ch) (1 << (ch))
#define OV_STATUS_CRIT(ch) (1 << ((ch) + 4))
#define MAX5970_REG_FAULT2 0x37
#define OC_STATUS_WARN(ch) (1 << (ch))
#define MAX5970_REG_CHXEN 0x3b
#define CHXEN(ch) (3 << ((ch) * 2))
#define MAX5970_REG_LED_FLASH 0x43
#define MAX_REGISTERS 0x49
#define ADC_MASK 0x3FF
#endif /* _MFD_MAX5970_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max7360.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __LINUX_MFD_MAX7360_H
#define __LINUX_MFD_MAX7360_H
#include <linux/bits.h>
#define MAX7360_MAX_KEY_ROWS 8
#define MAX7360_MAX_KEY_COLS 8
#define MAX7360_MAX_KEY_NUM (MAX7360_MAX_KEY_ROWS * MAX7360_MAX_KEY_COLS)
#define MAX7360_ROW_SHIFT 3
#define MAX7360_MAX_GPIO 8
#define MAX7360_MAX_GPO 6
#define MAX7360_PORT_PWM_COUNT 8
#define MAX7360_PORT_RTR_PIN (MAX7360_PORT_PWM_COUNT - 1)
/*
* MAX7360 registers
*/
#define MAX7360_REG_KEYFIFO 0x00
#define MAX7360_REG_CONFIG 0x01
#define MAX7360_REG_DEBOUNCE 0x02
#define MAX7360_REG_INTERRUPT 0x03
#define MAX7360_REG_PORTS 0x04
#define MAX7360_REG_KEYREP 0x05
#define MAX7360_REG_SLEEP 0x06
/*
* MAX7360 GPIO registers
*
* All these registers are reset together when writing bit 3 of
* MAX7360_REG_GPIOCFG.
*/
#define MAX7360_REG_GPIOCFG 0x40
#define MAX7360_REG_GPIOCTRL 0x41
#define MAX7360_REG_GPIODEB 0x42
#define MAX7360_REG_GPIOCURR 0x43
#define MAX7360_REG_GPIOOUTM 0x44
#define MAX7360_REG_PWMCOM 0x45
#define MAX7360_REG_RTRCFG 0x46
#define MAX7360_REG_I2C_TIMEOUT 0x48
#define MAX7360_REG_GPIOIN 0x49
#define MAX7360_REG_RTR_CNT 0x4A
#define MAX7360_REG_PWMBASE 0x50
#define MAX7360_REG_PWMCFGBASE 0x58
#define MAX7360_REG_GPIO_LAST 0x5F
#define MAX7360_REG_PWM(x) (MAX7360_REG_PWMBASE + (x))
#define MAX7360_REG_PWMCFG(x) (MAX7360_REG_PWMCFGBASE + (x))
/*
* Configuration register bits
*/
#define MAX7360_FIFO_EMPTY 0x3F
#define MAX7360_FIFO_OVERFLOW 0x7F
#define MAX7360_FIFO_RELEASE BIT(6)
#define MAX7360_FIFO_COL GENMASK(5, 3)
#define MAX7360_FIFO_ROW GENMASK(2, 0)
#define MAX7360_CFG_SLEEP BIT(7)
#define MAX7360_CFG_INTERRUPT BIT(5)
#define MAX7360_CFG_KEY_RELEASE BIT(3)
#define MAX7360_CFG_WAKEUP BIT(1)
#define MAX7360_CFG_TIMEOUT BIT(0)
#define MAX7360_DEBOUNCE GENMASK(4, 0)
#define MAX7360_DEBOUNCE_MIN 9
#define MAX7360_DEBOUNCE_MAX 40
#define MAX7360_PORTS GENMASK(8, 5)
#define MAX7360_INTERRUPT_TIME_MASK GENMASK(4, 0)
#define MAX7360_INTERRUPT_FIFO_MASK GENMASK(7, 5)
#define MAX7360_PORT_CFG_INTERRUPT_MASK BIT(7)
#define MAX7360_PORT_CFG_INTERRUPT_EDGES BIT(6)
#define MAX7360_PORT_CFG_COMMON_PWM BIT(5)
/*
* Autosleep register values
*/
#define MAX7360_AUTOSLEEP_8192MS 0x01
#define MAX7360_AUTOSLEEP_4096MS 0x02
#define MAX7360_AUTOSLEEP_2048MS 0x03
#define MAX7360_AUTOSLEEP_1024MS 0x04
#define MAX7360_AUTOSLEEP_512MS 0x05
#define MAX7360_AUTOSLEEP_256MS 0x06
#define MAX7360_GPIO_CFG_RTR_EN BIT(7)
#define MAX7360_GPIO_CFG_GPIO_EN BIT(4)
#define MAX7360_GPIO_CFG_GPIO_RST BIT(3)
#define MAX7360_ROT_DEBOUNCE GENMASK(3, 0)
#define MAX7360_ROT_DEBOUNCE_MIN 0
#define MAX7360_ROT_DEBOUNCE_MAX 15
#define MAX7360_ROT_INTCNT GENMASK(6, 4)
#define MAX7360_ROT_INTCNT_DLY BIT(7)
#define MAX7360_INT_INTI 0
#define MAX7360_INT_INTK 1
#define MAX7360_INT_GPIO 0
#define MAX7360_INT_KEYPAD 1
#define MAX7360_INT_ROTARY 2
#define MAX7360_NR_INTERNAL_IRQS 3
#endif
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77541.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MFD_MAX77541_H
#define __MFD_MAX77541_H
#include <linux/bits.h>
#include <linux/types.h>
/* REGISTERS */
#define MAX77541_REG_INT_SRC 0x00
#define MAX77541_REG_INT_SRC_M 0x01
#define MAX77541_BIT_INT_SRC_TOPSYS BIT(0)
#define MAX77541_BIT_INT_SRC_BUCK BIT(1)
#define MAX77541_REG_TOPSYS_INT 0x02
#define MAX77541_REG_TOPSYS_INT_M 0x03
#define MAX77541_BIT_TOPSYS_INT_TJ_120C BIT(0)
#define MAX77541_BIT_TOPSYS_INT_TJ_140C BIT(1)
#define MAX77541_BIT_TOPSYS_INT_TSHDN BIT(2)
#define MAX77541_BIT_TOPSYS_INT_UVLO BIT(3)
#define MAX77541_BIT_TOPSYS_INT_ALT_SWO BIT(4)
#define MAX77541_BIT_TOPSYS_INT_EXT_FREQ_DET BIT(5)
/* REGULATORS */
#define MAX77541_REG_BUCK_INT 0x20
#define MAX77541_REG_BUCK_INT_M 0x21
#define MAX77541_BIT_BUCK_INT_M1_POK_FLT BIT(0)
#define MAX77541_BIT_BUCK_INT_M2_POK_FLT BIT(1)
#define MAX77541_BIT_BUCK_INT_M1_SCFLT BIT(4)
#define MAX77541_BIT_BUCK_INT_M2_SCFLT BIT(5)
#define MAX77541_REG_EN_CTRL 0x0B
#define MAX77541_BIT_M1_EN BIT(0)
#define MAX77541_BIT_M2_EN BIT(1)
#define MAX77541_REG_M1_VOUT 0x23
#define MAX77541_REG_M2_VOUT 0x33
#define MAX77541_BITS_MX_VOUT GENMASK(7, 0)
#define MAX77541_REG_M1_CFG1 0x25
#define MAX77541_REG_M2_CFG1 0x35
#define MAX77541_BITS_MX_CFG1_RNG GENMASK(7, 6)
/* ADC */
#define MAX77541_REG_ADC_INT 0x70
#define MAX77541_REG_ADC_INT_M 0x71
#define MAX77541_BIT_ADC_INT_CH1_I BIT(0)
#define MAX77541_BIT_ADC_INT_CH2_I BIT(1)
#define MAX77541_BIT_ADC_INT_CH3_I BIT(2)
#define MAX77541_BIT_ADC_INT_CH6_I BIT(5)
#define MAX77541_REG_ADC_DATA_CH1 0x72
#define MAX77541_REG_ADC_DATA_CH2 0x73
#define MAX77541_REG_ADC_DATA_CH3 0x74
#define MAX77541_REG_ADC_DATA_CH6 0x77
/* INTERRUPT MASKS*/
#define MAX77541_REG_INT_SRC_MASK 0x00
#define MAX77541_REG_TOPSYS_INT_MASK 0x00
#define MAX77541_REG_BUCK_INT_MASK 0x00
#define MAX77541_MAX_REGULATORS 2
enum max7754x_ids {
MAX77540 = 1,
MAX77541,
};
struct regmap;
struct regmap_irq_chip_data;
struct i2c_client;
struct max77541 {
struct i2c_client *i2c;
struct regmap *regmap;
enum max7754x_ids id;
struct regmap_irq_chip_data *irq_data;
struct regmap_irq_chip_data *irq_buck;
struct regmap_irq_chip_data *irq_topsys;
struct regmap_irq_chip_data *irq_adc;
};
#endif /* __MFD_MAX77541_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77620.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defining registers address and its bit definitions of MAX77620 and MAX20024
*
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _MFD_MAX77620_H_
#define _MFD_MAX77620_H_
#include <linux/types.h>
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
#define MAX77620_REG_CNFGGLBL1 0x00
#define MAX77620_REG_CNFGGLBL2 0x01
#define MAX77620_REG_CNFGGLBL3 0x02
#define MAX77620_REG_CNFG1_32K 0x03
#define MAX77620_REG_CNFGBBC 0x04
#define MAX77620_REG_IRQTOP 0x05
#define MAX77620_REG_INTLBT 0x06
#define MAX77620_REG_IRQSD 0x07
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
#define MAX77620_REG_IRQ_LVL2_L8 0x09
#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
#define MAX77620_REG_ONOFFIRQ 0x0B
#define MAX77620_REG_NVERC 0x0C
#define MAX77620_REG_IRQTOPM 0x0D
#define MAX77620_REG_INTENLBT 0x0E
#define MAX77620_REG_IRQMASKSD 0x0F
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
#define MAX77620_REG_IRQ_MSK_L8 0x11
#define MAX77620_REG_ONOFFIRQM 0x12
#define MAX77620_REG_STATLBT 0x13
#define MAX77620_REG_STATSD 0x14
#define MAX77620_REG_ONOFFSTAT 0x15
/* SD and LDO Registers */
#define MAX77620_REG_SD0 0x16
#define MAX77620_REG_SD1 0x17
#define MAX77620_REG_SD2 0x18
#define MAX77620_REG_SD3 0x19
#define MAX77620_REG_SD4 0x1A
#define MAX77620_REG_DVSSD0 0x1B
#define MAX77620_REG_DVSSD1 0x1C
#define MAX77620_REG_SD0_CFG 0x1D
#define MAX77620_REG_SD1_CFG 0x1E
#define MAX77620_REG_SD2_CFG 0x1F
#define MAX77620_REG_SD3_CFG 0x20
#define MAX77620_REG_SD4_CFG 0x21
#define MAX77620_REG_SD_CFG2 0x22
#define MAX77620_REG_LDO0_CFG 0x23
#define MAX77620_REG_LDO0_CFG2 0x24
#define MAX77620_REG_LDO1_CFG 0x25
#define MAX77620_REG_LDO1_CFG2 0x26
#define MAX77620_REG_LDO2_CFG 0x27
#define MAX77620_REG_LDO2_CFG2 0x28
#define MAX77620_REG_LDO3_CFG 0x29
#define MAX77620_REG_LDO3_CFG2 0x2A
#define MAX77620_REG_LDO4_CFG 0x2B
#define MAX77620_REG_LDO4_CFG2 0x2C
#define MAX77620_REG_LDO5_CFG 0x2D
#define MAX77620_REG_LDO5_CFG2 0x2E
#define MAX77620_REG_LDO6_CFG 0x2F
#define MAX77620_REG_LDO6_CFG2 0x30
#define MAX77620_REG_LDO7_CFG 0x31
#define MAX77620_REG_LDO7_CFG2 0x32
#define MAX77620_REG_LDO8_CFG 0x33
#define MAX77620_REG_LDO8_CFG2 0x34
#define MAX77620_REG_LDO_CFG3 0x35
#define MAX77620_LDO_SLEW_RATE_MASK 0x1
/* LDO Configuration 3 */
#define MAX77620_TRACK4_MASK BIT(5)
#define MAX77620_TRACK4_SHIFT 5
/* Voltage */
#define MAX77620_SDX_VOLT_MASK 0xFF
#define MAX77620_SD0_VOLT_MASK 0x3F
#define MAX77620_SD1_VOLT_MASK 0x7F
#define MAX77620_LDO_VOLT_MASK 0x3F
#define MAX77620_REG_GPIO0 0x36
#define MAX77620_REG_GPIO1 0x37
#define MAX77620_REG_GPIO2 0x38
#define MAX77620_REG_GPIO3 0x39
#define MAX77620_REG_GPIO4 0x3A
#define MAX77620_REG_GPIO5 0x3B
#define MAX77620_REG_GPIO6 0x3C
#define MAX77620_REG_GPIO7 0x3D
#define MAX77620_REG_PUE_GPIO 0x3E
#define MAX77620_REG_PDE_GPIO 0x3F
#define MAX77620_REG_AME_GPIO 0x40
#define MAX77620_REG_ONOFFCNFG1 0x41
#define MAX77620_REG_ONOFFCNFG2 0x42
/* FPS Registers */
#define MAX77620_REG_FPS_CFG0 0x43
#define MAX77620_REG_FPS_CFG1 0x44
#define MAX77620_REG_FPS_CFG2 0x45
#define MAX77620_REG_FPS_LDO0 0x46
#define MAX77620_REG_FPS_LDO1 0x47
#define MAX77620_REG_FPS_LDO2 0x48
#define MAX77620_REG_FPS_LDO3 0x49
#define MAX77620_REG_FPS_LDO4 0x4A
#define MAX77620_REG_FPS_LDO5 0x4B
#define MAX77620_REG_FPS_LDO6 0x4C
#define MAX77620_REG_FPS_LDO7 0x4D
#define MAX77620_REG_FPS_LDO8 0x4E
#define MAX77620_REG_FPS_SD0 0x4F
#define MAX77620_REG_FPS_SD1 0x50
#define MAX77620_REG_FPS_SD2 0x51
#define MAX77620_REG_FPS_SD3 0x52
#define MAX77620_REG_FPS_SD4 0x53
#define MAX77620_REG_FPS_NONE 0
#define MAX77620_FPS_SRC_MASK 0xC0
#define MAX77620_FPS_SRC_SHIFT 6
#define MAX77620_FPS_PU_PERIOD_MASK 0x38
#define MAX77620_FPS_PU_PERIOD_SHIFT 3
#define MAX77620_FPS_PD_PERIOD_MASK 0x07
#define MAX77620_FPS_PD_PERIOD_SHIFT 0
#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
#define MAX77620_FPS_EN_SRC_MASK 0x06
#define MAX77620_FPS_EN_SRC_SHIFT 1
#define MAX77620_FPS_ENFPS_SW_MASK 0x01
#define MAX77620_FPS_ENFPS_SW 0x01
/* Minimum and maximum FPS period time (in microseconds) are
* different for MAX77620 and Max20024.
*/
#define MAX77620_FPS_PERIOD_MIN_US 40
#define MAX20024_FPS_PERIOD_MIN_US 20
#define MAX20024_FPS_PERIOD_MAX_US 2560
#define MAX77620_FPS_PERIOD_MAX_US 5120
#define MAX77620_REG_FPS_GPIO1 0x54
#define MAX77620_REG_FPS_GPIO2 0x55
#define MAX77620_REG_FPS_GPIO3 0x56
#define MAX77620_REG_FPS_RSO 0x57
#define MAX77620_REG_CID0 0x58
#define MAX77620_REG_CID1 0x59
#define MAX77620_REG_CID2 0x5A
#define MAX77620_REG_CID3 0x5B
#define MAX77620_REG_CID4 0x5C
#define MAX77620_REG_CID5 0x5D
#define MAX77620_REG_DVSSD4 0x5E
#define MAX20024_REG_MAX_ADD 0x70
#define MAX77620_CID_DIDM_MASK 0xF0
#define MAX77620_CID_DIDM_SHIFT 4
/* CNCG2SD */
#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
/* Device Identification Metal */
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
/* Device Indentification OTP */
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
/* SD CNFG1 */
#define MAX77620_SD_SR_MASK 0xC0
#define MAX77620_SD_SR_SHIFT 6
#define MAX77620_SD_POWER_MODE_MASK 0x30
#define MAX77620_SD_POWER_MODE_SHIFT 4
#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
#define MAX77620_SD_CFG1_ADE_DISABLE 0
#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
#define MAX77620_SD_FPWM_MASK 0x04
#define MAX77620_SD_FPWM_SHIFT 2
#define MAX77620_SD_FSRADE_MASK 0x01
#define MAX77620_SD_FSRADE_SHIFT 0
#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
#define MAX20024_SD_CFG1_MPOK_MASK BIT(1)
#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
/* LDO_CNFG2 */
#define MAX77620_LDO_POWER_MODE_MASK 0xC0
#define MAX77620_LDO_POWER_MODE_SHIFT 6
#define MAX20024_LDO_CFG2_MPOK_MASK BIT(2)
#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
#define MAX77620_LDO_CFG2_ADE_DISABLE 0
#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
#define MAX77620_LDO_CFG2_SS_SLOW 0
#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
#define MAX77620_IRQ_LBM_MASK BIT(3)
#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
#define MAX77620_PWR_I2C_ADDR 0x3c
#define MAX77620_RTC_I2C_ADDR 0x68
#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
#define MAX77620_GLBLM_MASK BIT(0)
#define MAX77620_WDTC_MASK 0x3
#define MAX77620_WDTOFFC BIT(4)
#define MAX77620_WDTSLPC BIT(3)
#define MAX77620_WDTEN BIT(2)
#define MAX77620_TWD_MASK 0x3
#define MAX77620_TWD_2s 0x0
#define MAX77620_TWD_16s 0x1
#define MAX77620_TWD_64s 0x2
#define MAX77620_TWD_128s 0x3
#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
#define MAX77620_CNFGGLBL1_LBDAC 0x0E
#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
/* CNFG BBC registers */
#define MAX77620_CNFGBBC_ENABLE BIT(0)
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
#define MAX77620_FPS_COUNT 3
/* Interrupts */
enum {
MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
MAX77620_IRQ_TOP_SD, /* SD power fail */
MAX77620_IRQ_TOP_LDO, /* LDO power fail */
MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
MAX77620_IRQ_TOP_RTC, /* RTC */
MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
};
/* GPIOs */
enum {
MAX77620_GPIO0,
MAX77620_GPIO1,
MAX77620_GPIO2,
MAX77620_GPIO3,
MAX77620_GPIO4,
MAX77620_GPIO5,
MAX77620_GPIO6,
MAX77620_GPIO7,
MAX77620_GPIO_NR,
};
/* FPS Source */
enum max77620_fps_src {
MAX77620_FPS_SRC_0,
MAX77620_FPS_SRC_1,
MAX77620_FPS_SRC_2,
MAX77620_FPS_SRC_NONE,
MAX77620_FPS_SRC_DEF,
};
enum max77620_chip_id {
MAX77620,
MAX20024,
MAX77663,
};
struct max77620_chip {
struct device *dev;
struct regmap *rmap;
int chip_irq;
/* chip id */
enum max77620_chip_id chip_id;
bool sleep_enable;
bool enable_global_lpm;
int shutdown_fps_period[MAX77620_FPS_COUNT];
int suspend_fps_period[MAX77620_FPS_COUNT];
struct regmap_irq_chip_data *top_irq_data;
struct regmap_irq_chip_data *gpio_irq_data;
};
#endif /* _MFD_MAX77620_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77650.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 BayLibre SAS
* Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
*
* Common definitions for MAXIM 77650/77651 charger/power-supply.
*/
#ifndef MAX77650_H
#define MAX77650_H
#include <linux/bits.h>
#define MAX77650_REG_INT_GLBL 0x00
#define MAX77650_REG_INT_CHG 0x01
#define MAX77650_REG_STAT_CHG_A 0x02
#define MAX77650_REG_STAT_CHG_B 0x03
#define MAX77650_REG_ERCFLAG 0x04
#define MAX77650_REG_STAT_GLBL 0x05
#define MAX77650_REG_INTM_GLBL 0x06
#define MAX77650_REG_INTM_CHG 0x07
#define MAX77650_REG_CNFG_GLBL 0x10
#define MAX77650_REG_CID 0x11
#define MAX77650_REG_CNFG_GPIO 0x12
#define MAX77650_REG_CNFG_CHG_A 0x18
#define MAX77650_REG_CNFG_CHG_B 0x19
#define MAX77650_REG_CNFG_CHG_C 0x1a
#define MAX77650_REG_CNFG_CHG_D 0x1b
#define MAX77650_REG_CNFG_CHG_E 0x1c
#define MAX77650_REG_CNFG_CHG_F 0x1d
#define MAX77650_REG_CNFG_CHG_G 0x1e
#define MAX77650_REG_CNFG_CHG_H 0x1f
#define MAX77650_REG_CNFG_CHG_I 0x20
#define MAX77650_REG_CNFG_SBB_TOP 0x28
#define MAX77650_REG_CNFG_SBB0_A 0x29
#define MAX77650_REG_CNFG_SBB0_B 0x2a
#define MAX77650_REG_CNFG_SBB1_A 0x2b
#define MAX77650_REG_CNFG_SBB1_B 0x2c
#define MAX77650_REG_CNFG_SBB2_A 0x2d
#define MAX77650_REG_CNFG_SBB2_B 0x2e
#define MAX77650_REG_CNFG_LDO_A 0x38
#define MAX77650_REG_CNFG_LDO_B 0x39
#define MAX77650_REG_CNFG_LED0_A 0x40
#define MAX77650_REG_CNFG_LED1_A 0x41
#define MAX77650_REG_CNFG_LED2_A 0x42
#define MAX77650_REG_CNFG_LED0_B 0x43
#define MAX77650_REG_CNFG_LED1_B 0x44
#define MAX77650_REG_CNFG_LED2_B 0x45
#define MAX77650_REG_CNFG_LED_TOP 0x46
#define MAX77650_CID_MASK GENMASK(3, 0)
#define MAX77650_CID_BITS(_reg) (_reg & MAX77650_CID_MASK)
#define MAX77650_CID_77650A 0x03
#define MAX77650_CID_77650C 0x0a
#define MAX77650_CID_77651A 0x06
#define MAX77650_CID_77651B 0x08
#endif /* MAX77650_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77686-private.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max77686-private.h - Voltage regulator driver for the Maxim 77686/802
*
* Copyright (C) 2012 Samsung Electronics
* Chiwoong Byun <woong.byun@samsung.com>
*/
#ifndef __LINUX_MFD_MAX77686_PRIV_H
#define __LINUX_MFD_MAX77686_PRIV_H
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/module.h>
#define MAX77686_REG_INVALID (0xff)
/* MAX77686 PMIC registers */
enum max77686_pmic_reg {
MAX77686_REG_DEVICE_ID = 0x00,
MAX77686_REG_INTSRC = 0x01,
MAX77686_REG_INT1 = 0x02,
MAX77686_REG_INT2 = 0x03,
MAX77686_REG_INT1MSK = 0x04,
MAX77686_REG_INT2MSK = 0x05,
MAX77686_REG_STATUS1 = 0x06,
MAX77686_REG_STATUS2 = 0x07,
MAX77686_REG_PWRON = 0x08,
MAX77686_REG_ONOFF_DELAY = 0x09,
MAX77686_REG_MRSTB = 0x0A,
/* Reserved: 0x0B-0x0F */
MAX77686_REG_BUCK1CTRL = 0x10,
MAX77686_REG_BUCK1OUT = 0x11,
MAX77686_REG_BUCK2CTRL1 = 0x12,
MAX77686_REG_BUCK234FREQ = 0x13,
MAX77686_REG_BUCK2DVS1 = 0x14,
MAX77686_REG_BUCK2DVS2 = 0x15,
MAX77686_REG_BUCK2DVS3 = 0x16,
MAX77686_REG_BUCK2DVS4 = 0x17,
MAX77686_REG_BUCK2DVS5 = 0x18,
MAX77686_REG_BUCK2DVS6 = 0x19,
MAX77686_REG_BUCK2DVS7 = 0x1A,
MAX77686_REG_BUCK2DVS8 = 0x1B,
MAX77686_REG_BUCK3CTRL1 = 0x1C,
/* Reserved: 0x1D */
MAX77686_REG_BUCK3DVS1 = 0x1E,
MAX77686_REG_BUCK3DVS2 = 0x1F,
MAX77686_REG_BUCK3DVS3 = 0x20,
MAX77686_REG_BUCK3DVS4 = 0x21,
MAX77686_REG_BUCK3DVS5 = 0x22,
MAX77686_REG_BUCK3DVS6 = 0x23,
MAX77686_REG_BUCK3DVS7 = 0x24,
MAX77686_REG_BUCK3DVS8 = 0x25,
MAX77686_REG_BUCK4CTRL1 = 0x26,
/* Reserved: 0x27 */
MAX77686_REG_BUCK4DVS1 = 0x28,
MAX77686_REG_BUCK4DVS2 = 0x29,
MAX77686_REG_BUCK4DVS3 = 0x2A,
MAX77686_REG_BUCK4DVS4 = 0x2B,
MAX77686_REG_BUCK4DVS5 = 0x2C,
MAX77686_REG_BUCK4DVS6 = 0x2D,
MAX77686_REG_BUCK4DVS7 = 0x2E,
MAX77686_REG_BUCK4DVS8 = 0x2F,
MAX77686_REG_BUCK5CTRL = 0x30,
MAX77686_REG_BUCK5OUT = 0x31,
MAX77686_REG_BUCK6CTRL = 0x32,
MAX77686_REG_BUCK6OUT = 0x33,
MAX77686_REG_BUCK7CTRL = 0x34,
MAX77686_REG_BUCK7OUT = 0x35,
MAX77686_REG_BUCK8CTRL = 0x36,
MAX77686_REG_BUCK8OUT = 0x37,
MAX77686_REG_BUCK9CTRL = 0x38,
MAX77686_REG_BUCK9OUT = 0x39,
/* Reserved: 0x3A-0x3F */
MAX77686_REG_LDO1CTRL1 = 0x40,
MAX77686_REG_LDO2CTRL1 = 0x41,
MAX77686_REG_LDO3CTRL1 = 0x42,
MAX77686_REG_LDO4CTRL1 = 0x43,
MAX77686_REG_LDO5CTRL1 = 0x44,
MAX77686_REG_LDO6CTRL1 = 0x45,
MAX77686_REG_LDO7CTRL1 = 0x46,
MAX77686_REG_LDO8CTRL1 = 0x47,
MAX77686_REG_LDO9CTRL1 = 0x48,
MAX77686_REG_LDO10CTRL1 = 0x49,
MAX77686_REG_LDO11CTRL1 = 0x4A,
MAX77686_REG_LDO12CTRL1 = 0x4B,
MAX77686_REG_LDO13CTRL1 = 0x4C,
MAX77686_REG_LDO14CTRL1 = 0x4D,
MAX77686_REG_LDO15CTRL1 = 0x4E,
MAX77686_REG_LDO16CTRL1 = 0x4F,
MAX77686_REG_LDO17CTRL1 = 0x50,
MAX77686_REG_LDO18CTRL1 = 0x51,
MAX77686_REG_LDO19CTRL1 = 0x52,
MAX77686_REG_LDO20CTRL1 = 0x53,
MAX77686_REG_LDO21CTRL1 = 0x54,
MAX77686_REG_LDO22CTRL1 = 0x55,
MAX77686_REG_LDO23CTRL1 = 0x56,
MAX77686_REG_LDO24CTRL1 = 0x57,
MAX77686_REG_LDO25CTRL1 = 0x58,
MAX77686_REG_LDO26CTRL1 = 0x59,
/* Reserved: 0x5A-0x5F */
MAX77686_REG_LDO1CTRL2 = 0x60,
MAX77686_REG_LDO2CTRL2 = 0x61,
MAX77686_REG_LDO3CTRL2 = 0x62,
MAX77686_REG_LDO4CTRL2 = 0x63,
MAX77686_REG_LDO5CTRL2 = 0x64,
MAX77686_REG_LDO6CTRL2 = 0x65,
MAX77686_REG_LDO7CTRL2 = 0x66,
MAX77686_REG_LDO8CTRL2 = 0x67,
MAX77686_REG_LDO9CTRL2 = 0x68,
MAX77686_REG_LDO10CTRL2 = 0x69,
MAX77686_REG_LDO11CTRL2 = 0x6A,
MAX77686_REG_LDO12CTRL2 = 0x6B,
MAX77686_REG_LDO13CTRL2 = 0x6C,
MAX77686_REG_LDO14CTRL2 = 0x6D,
MAX77686_REG_LDO15CTRL2 = 0x6E,
MAX77686_REG_LDO16CTRL2 = 0x6F,
MAX77686_REG_LDO17CTRL2 = 0x70,
MAX77686_REG_LDO18CTRL2 = 0x71,
MAX77686_REG_LDO19CTRL2 = 0x72,
MAX77686_REG_LDO20CTRL2 = 0x73,
MAX77686_REG_LDO21CTRL2 = 0x74,
MAX77686_REG_LDO22CTRL2 = 0x75,
MAX77686_REG_LDO23CTRL2 = 0x76,
MAX77686_REG_LDO24CTRL2 = 0x77,
MAX77686_REG_LDO25CTRL2 = 0x78,
MAX77686_REG_LDO26CTRL2 = 0x79,
/* Reserved: 0x7A-0x7D */
MAX77686_REG_BBAT_CHG = 0x7E,
MAX77686_REG_32KHZ = 0x7F,
MAX77686_REG_PMIC_END = 0x80,
};
enum max77686_rtc_reg {
MAX77686_RTC_INT = 0x00,
MAX77686_RTC_INTM = 0x01,
MAX77686_RTC_CONTROLM = 0x02,
MAX77686_RTC_CONTROL = 0x03,
MAX77686_RTC_UPDATE0 = 0x04,
/* Reserved: 0x5 */
MAX77686_WTSR_SMPL_CNTL = 0x06,
MAX77686_RTC_SEC = 0x07,
MAX77686_RTC_MIN = 0x08,
MAX77686_RTC_HOUR = 0x09,
MAX77686_RTC_WEEKDAY = 0x0A,
MAX77686_RTC_MONTH = 0x0B,
MAX77686_RTC_YEAR = 0x0C,
MAX77686_RTC_MONTHDAY = 0x0D,
MAX77686_ALARM1_SEC = 0x0E,
MAX77686_ALARM1_MIN = 0x0F,
MAX77686_ALARM1_HOUR = 0x10,
MAX77686_ALARM1_WEEKDAY = 0x11,
MAX77686_ALARM1_MONTH = 0x12,
MAX77686_ALARM1_YEAR = 0x13,
MAX77686_ALARM1_DATE = 0x14,
MAX77686_ALARM2_SEC = 0x15,
MAX77686_ALARM2_MIN = 0x16,
MAX77686_ALARM2_HOUR = 0x17,
MAX77686_ALARM2_WEEKDAY = 0x18,
MAX77686_ALARM2_MONTH = 0x19,
MAX77686_ALARM2_YEAR = 0x1A,
MAX77686_ALARM2_DATE = 0x1B,
};
/* MAX77802 PMIC registers */
enum max77802_pmic_reg {
MAX77802_REG_DEVICE_ID = 0x00,
MAX77802_REG_INTSRC = 0x01,
MAX77802_REG_INT1 = 0x02,
MAX77802_REG_INT2 = 0x03,
MAX77802_REG_INT1MSK = 0x04,
MAX77802_REG_INT2MSK = 0x05,
MAX77802_REG_STATUS1 = 0x06,
MAX77802_REG_STATUS2 = 0x07,
MAX77802_REG_PWRON = 0x08,
/* Reserved: 0x09 */
MAX77802_REG_MRSTB = 0x0A,
MAX77802_REG_EPWRHOLD = 0x0B,
/* Reserved: 0x0C-0x0D */
MAX77802_REG_BOOSTCTRL = 0x0E,
MAX77802_REG_BOOSTOUT = 0x0F,
MAX77802_REG_BUCK1CTRL = 0x10,
MAX77802_REG_BUCK1DVS1 = 0x11,
MAX77802_REG_BUCK1DVS2 = 0x12,
MAX77802_REG_BUCK1DVS3 = 0x13,
MAX77802_REG_BUCK1DVS4 = 0x14,
MAX77802_REG_BUCK1DVS5 = 0x15,
MAX77802_REG_BUCK1DVS6 = 0x16,
MAX77802_REG_BUCK1DVS7 = 0x17,
MAX77802_REG_BUCK1DVS8 = 0x18,
/* Reserved: 0x19 */
MAX77802_REG_BUCK2CTRL1 = 0x1A,
MAX77802_REG_BUCK2CTRL2 = 0x1B,
MAX77802_REG_BUCK2PHTRAN = 0x1C,
MAX77802_REG_BUCK2DVS1 = 0x1D,
MAX77802_REG_BUCK2DVS2 = 0x1E,
MAX77802_REG_BUCK2DVS3 = 0x1F,
MAX77802_REG_BUCK2DVS4 = 0x20,
MAX77802_REG_BUCK2DVS5 = 0x21,
MAX77802_REG_BUCK2DVS6 = 0x22,
MAX77802_REG_BUCK2DVS7 = 0x23,
MAX77802_REG_BUCK2DVS8 = 0x24,
/* Reserved: 0x25-0x26 */
MAX77802_REG_BUCK3CTRL1 = 0x27,
MAX77802_REG_BUCK3DVS1 = 0x28,
MAX77802_REG_BUCK3DVS2 = 0x29,
MAX77802_REG_BUCK3DVS3 = 0x2A,
MAX77802_REG_BUCK3DVS4 = 0x2B,
MAX77802_REG_BUCK3DVS5 = 0x2C,
MAX77802_REG_BUCK3DVS6 = 0x2D,
MAX77802_REG_BUCK3DVS7 = 0x2E,
MAX77802_REG_BUCK3DVS8 = 0x2F,
/* Reserved: 0x30-0x36 */
MAX77802_REG_BUCK4CTRL1 = 0x37,
MAX77802_REG_BUCK4DVS1 = 0x38,
MAX77802_REG_BUCK4DVS2 = 0x39,
MAX77802_REG_BUCK4DVS3 = 0x3A,
MAX77802_REG_BUCK4DVS4 = 0x3B,
MAX77802_REG_BUCK4DVS5 = 0x3C,
MAX77802_REG_BUCK4DVS6 = 0x3D,
MAX77802_REG_BUCK4DVS7 = 0x3E,
MAX77802_REG_BUCK4DVS8 = 0x3F,
/* Reserved: 0x40 */
MAX77802_REG_BUCK5CTRL = 0x41,
MAX77802_REG_BUCK5OUT = 0x42,
/* Reserved: 0x43 */
MAX77802_REG_BUCK6CTRL = 0x44,
MAX77802_REG_BUCK6DVS1 = 0x45,
MAX77802_REG_BUCK6DVS2 = 0x46,
MAX77802_REG_BUCK6DVS3 = 0x47,
MAX77802_REG_BUCK6DVS4 = 0x48,
MAX77802_REG_BUCK6DVS5 = 0x49,
MAX77802_REG_BUCK6DVS6 = 0x4A,
MAX77802_REG_BUCK6DVS7 = 0x4B,
MAX77802_REG_BUCK6DVS8 = 0x4C,
/* Reserved: 0x4D */
MAX77802_REG_BUCK7CTRL = 0x4E,
MAX77802_REG_BUCK7OUT = 0x4F,
/* Reserved: 0x50 */
MAX77802_REG_BUCK8CTRL = 0x51,
MAX77802_REG_BUCK8OUT = 0x52,
/* Reserved: 0x53 */
MAX77802_REG_BUCK9CTRL = 0x54,
MAX77802_REG_BUCK9OUT = 0x55,
/* Reserved: 0x56 */
MAX77802_REG_BUCK10CTRL = 0x57,
MAX77802_REG_BUCK10OUT = 0x58,
/* Reserved: 0x59-0x5F */
MAX77802_REG_LDO1CTRL1 = 0x60,
MAX77802_REG_LDO2CTRL1 = 0x61,
MAX77802_REG_LDO3CTRL1 = 0x62,
MAX77802_REG_LDO4CTRL1 = 0x63,
MAX77802_REG_LDO5CTRL1 = 0x64,
MAX77802_REG_LDO6CTRL1 = 0x65,
MAX77802_REG_LDO7CTRL1 = 0x66,
MAX77802_REG_LDO8CTRL1 = 0x67,
MAX77802_REG_LDO9CTRL1 = 0x68,
MAX77802_REG_LDO10CTRL1 = 0x69,
MAX77802_REG_LDO11CTRL1 = 0x6A,
MAX77802_REG_LDO12CTRL1 = 0x6B,
MAX77802_REG_LDO13CTRL1 = 0x6C,
MAX77802_REG_LDO14CTRL1 = 0x6D,
MAX77802_REG_LDO15CTRL1 = 0x6E,
/* Reserved: 0x6F */
MAX77802_REG_LDO17CTRL1 = 0x70,
MAX77802_REG_LDO18CTRL1 = 0x71,
MAX77802_REG_LDO19CTRL1 = 0x72,
MAX77802_REG_LDO20CTRL1 = 0x73,
MAX77802_REG_LDO21CTRL1 = 0x74,
MAX77802_REG_LDO22CTRL1 = 0x75,
MAX77802_REG_LDO23CTRL1 = 0x76,
MAX77802_REG_LDO24CTRL1 = 0x77,
MAX77802_REG_LDO25CTRL1 = 0x78,
MAX77802_REG_LDO26CTRL1 = 0x79,
MAX77802_REG_LDO27CTRL1 = 0x7A,
MAX77802_REG_LDO28CTRL1 = 0x7B,
MAX77802_REG_LDO29CTRL1 = 0x7C,
MAX77802_REG_LDO30CTRL1 = 0x7D,
/* Reserved: 0x7E */
MAX77802_REG_LDO32CTRL1 = 0x7F,
MAX77802_REG_LDO33CTRL1 = 0x80,
MAX77802_REG_LDO34CTRL1 = 0x81,
MAX77802_REG_LDO35CTRL1 = 0x82,
/* Reserved: 0x83-0x8F */
MAX77802_REG_LDO1CTRL2 = 0x90,
MAX77802_REG_LDO2CTRL2 = 0x91,
MAX77802_REG_LDO3CTRL2 = 0x92,
MAX77802_REG_LDO4CTRL2 = 0x93,
MAX77802_REG_LDO5CTRL2 = 0x94,
MAX77802_REG_LDO6CTRL2 = 0x95,
MAX77802_REG_LDO7CTRL2 = 0x96,
MAX77802_REG_LDO8CTRL2 = 0x97,
MAX77802_REG_LDO9CTRL2 = 0x98,
MAX77802_REG_LDO10CTRL2 = 0x99,
MAX77802_REG_LDO11CTRL2 = 0x9A,
MAX77802_REG_LDO12CTRL2 = 0x9B,
MAX77802_REG_LDO13CTRL2 = 0x9C,
MAX77802_REG_LDO14CTRL2 = 0x9D,
MAX77802_REG_LDO15CTRL2 = 0x9E,
/* Reserved: 0x9F */
MAX77802_REG_LDO17CTRL2 = 0xA0,
MAX77802_REG_LDO18CTRL2 = 0xA1,
MAX77802_REG_LDO19CTRL2 = 0xA2,
MAX77802_REG_LDO20CTRL2 = 0xA3,
MAX77802_REG_LDO21CTRL2 = 0xA4,
MAX77802_REG_LDO22CTRL2 = 0xA5,
MAX77802_REG_LDO23CTRL2 = 0xA6,
MAX77802_REG_LDO24CTRL2 = 0xA7,
MAX77802_REG_LDO25CTRL2 = 0xA8,
MAX77802_REG_LDO26CTRL2 = 0xA9,
MAX77802_REG_LDO27CTRL2 = 0xAA,
MAX77802_REG_LDO28CTRL2 = 0xAB,
MAX77802_REG_LDO29CTRL2 = 0xAC,
MAX77802_REG_LDO30CTRL2 = 0xAD,
/* Reserved: 0xAE */
MAX77802_REG_LDO32CTRL2 = 0xAF,
MAX77802_REG_LDO33CTRL2 = 0xB0,
MAX77802_REG_LDO34CTRL2 = 0xB1,
MAX77802_REG_LDO35CTRL2 = 0xB2,
/* Reserved: 0xB3 */
MAX77802_REG_BBAT_CHG = 0xB4,
MAX77802_REG_32KHZ = 0xB5,
MAX77802_REG_PMIC_END = 0xB6,
};
enum max77802_rtc_reg {
MAX77802_RTC_INT = 0xC0,
MAX77802_RTC_INTM = 0xC1,
MAX77802_RTC_CONTROLM = 0xC2,
MAX77802_RTC_CONTROL = 0xC3,
MAX77802_RTC_UPDATE0 = 0xC4,
MAX77802_RTC_UPDATE1 = 0xC5,
MAX77802_WTSR_SMPL_CNTL = 0xC6,
MAX77802_RTC_SEC = 0xC7,
MAX77802_RTC_MIN = 0xC8,
MAX77802_RTC_HOUR = 0xC9,
MAX77802_RTC_WEEKDAY = 0xCA,
MAX77802_RTC_MONTH = 0xCB,
MAX77802_RTC_YEAR = 0xCC,
MAX77802_RTC_MONTHDAY = 0xCD,
MAX77802_RTC_AE1 = 0xCE,
MAX77802_ALARM1_SEC = 0xCF,
MAX77802_ALARM1_MIN = 0xD0,
MAX77802_ALARM1_HOUR = 0xD1,
MAX77802_ALARM1_WEEKDAY = 0xD2,
MAX77802_ALARM1_MONTH = 0xD3,
MAX77802_ALARM1_YEAR = 0xD4,
MAX77802_ALARM1_DATE = 0xD5,
MAX77802_RTC_AE2 = 0xD6,
MAX77802_ALARM2_SEC = 0xD7,
MAX77802_ALARM2_MIN = 0xD8,
MAX77802_ALARM2_HOUR = 0xD9,
MAX77802_ALARM2_WEEKDAY = 0xDA,
MAX77802_ALARM2_MONTH = 0xDB,
MAX77802_ALARM2_YEAR = 0xDC,
MAX77802_ALARM2_DATE = 0xDD,
MAX77802_RTC_END = 0xDF,
};
enum max77686_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
RTC_INT,
MAX77686_IRQ_GROUP_NR,
};
enum max77686_irq {
MAX77686_PMICIRQ_PWRONF,
MAX77686_PMICIRQ_PWRONR,
MAX77686_PMICIRQ_JIGONBF,
MAX77686_PMICIRQ_JIGONBR,
MAX77686_PMICIRQ_ACOKBF,
MAX77686_PMICIRQ_ACOKBR,
MAX77686_PMICIRQ_ONKEY1S,
MAX77686_PMICIRQ_MRSTB,
MAX77686_PMICIRQ_140C,
MAX77686_PMICIRQ_120C,
MAX77686_RTCIRQ_RTC60S = 0,
MAX77686_RTCIRQ_RTCA1,
MAX77686_RTCIRQ_RTCA2,
MAX77686_RTCIRQ_SMPL,
MAX77686_RTCIRQ_RTC1S,
MAX77686_RTCIRQ_WTSR,
};
#define MAX77686_INT1_PWRONF_MSK BIT(0)
#define MAX77686_INT1_PWRONR_MSK BIT(1)
#define MAX77686_INT1_JIGONBF_MSK BIT(2)
#define MAX77686_INT1_JIGONBR_MSK BIT(3)
#define MAX77686_INT1_ACOKBF_MSK BIT(4)
#define MAX77686_INT1_ACOKBR_MSK BIT(5)
#define MAX77686_INT1_ONKEY1S_MSK BIT(6)
#define MAX77686_INT1_MRSTB_MSK BIT(7)
#define MAX77686_INT2_140C_MSK BIT(0)
#define MAX77686_INT2_120C_MSK BIT(1)
#define MAX77686_RTCINT_RTC60S_MSK BIT(0)
#define MAX77686_RTCINT_RTCA1_MSK BIT(1)
#define MAX77686_RTCINT_RTCA2_MSK BIT(2)
#define MAX77686_RTCINT_SMPL_MSK BIT(3)
#define MAX77686_RTCINT_RTC1S_MSK BIT(4)
#define MAX77686_RTCINT_WTSR_MSK BIT(5)
struct max77686_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
unsigned long type;
struct regmap *regmap; /* regmap for mfd */
struct regmap_irq_chip_data *irq_data;
int irq;
struct mutex irqlock;
int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
};
enum max77686_types {
TYPE_MAX77686,
TYPE_MAX77802,
};
#endif /* __LINUX_MFD_MAX77686_PRIV_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77686.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max77686.h - Driver for the Maxim 77686/802
*
* Copyright (C) 2012 Samsung Electronics
* Chiwoong Byun <woong.byun@samsung.com>
*
* This driver is based on max8997.h
*
* MAX77686 has PMIC, RTC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __LINUX_MFD_MAX77686_H
#define __LINUX_MFD_MAX77686_H
#include <linux/regulator/consumer.h>
/* MAX77686 regulator IDs */
enum max77686_regulators {
MAX77686_LDO1 = 0,
MAX77686_LDO2,
MAX77686_LDO3,
MAX77686_LDO4,
MAX77686_LDO5,
MAX77686_LDO6,
MAX77686_LDO7,
MAX77686_LDO8,
MAX77686_LDO9,
MAX77686_LDO10,
MAX77686_LDO11,
MAX77686_LDO12,
MAX77686_LDO13,
MAX77686_LDO14,
MAX77686_LDO15,
MAX77686_LDO16,
MAX77686_LDO17,
MAX77686_LDO18,
MAX77686_LDO19,
MAX77686_LDO20,
MAX77686_LDO21,
MAX77686_LDO22,
MAX77686_LDO23,
MAX77686_LDO24,
MAX77686_LDO25,
MAX77686_LDO26,
MAX77686_BUCK1,
MAX77686_BUCK2,
MAX77686_BUCK3,
MAX77686_BUCK4,
MAX77686_BUCK5,
MAX77686_BUCK6,
MAX77686_BUCK7,
MAX77686_BUCK8,
MAX77686_BUCK9,
MAX77686_REG_MAX,
};
/* MAX77802 regulator IDs */
enum max77802_regulators {
MAX77802_BUCK1 = 0,
MAX77802_BUCK2,
MAX77802_BUCK3,
MAX77802_BUCK4,
MAX77802_BUCK5,
MAX77802_BUCK6,
MAX77802_BUCK7,
MAX77802_BUCK8,
MAX77802_BUCK9,
MAX77802_BUCK10,
MAX77802_LDO1,
MAX77802_LDO2,
MAX77802_LDO3,
MAX77802_LDO4,
MAX77802_LDO5,
MAX77802_LDO6,
MAX77802_LDO7,
MAX77802_LDO8,
MAX77802_LDO9,
MAX77802_LDO10,
MAX77802_LDO11,
MAX77802_LDO12,
MAX77802_LDO13,
MAX77802_LDO14,
MAX77802_LDO15,
MAX77802_LDO17,
MAX77802_LDO18,
MAX77802_LDO19,
MAX77802_LDO20,
MAX77802_LDO21,
MAX77802_LDO23,
MAX77802_LDO24,
MAX77802_LDO25,
MAX77802_LDO26,
MAX77802_LDO27,
MAX77802_LDO28,
MAX77802_LDO29,
MAX77802_LDO30,
MAX77802_LDO32,
MAX77802_LDO33,
MAX77802_LDO34,
MAX77802_LDO35,
MAX77802_REG_MAX,
};
enum max77686_opmode {
MAX77686_OPMODE_NORMAL,
MAX77686_OPMODE_LP,
MAX77686_OPMODE_STANDBY,
};
#endif /* __LINUX_MFD_MAX77686_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77693-common.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Common data shared between Maxim 77693, 77705 and 77843 drivers
*
* Copyright (C) 2015 Samsung Electronics
*/
#ifndef __LINUX_MFD_MAX77693_COMMON_H
#define __LINUX_MFD_MAX77693_COMMON_H
enum max77693_types {
TYPE_MAX77693_UNKNOWN,
TYPE_MAX77693,
TYPE_MAX77705,
TYPE_MAX77843,
TYPE_MAX77693_NUM,
};
/*
* Shared also with max77843.
*/
struct max77693_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
struct i2c_client *i2c_muic; /* 0x4A , MUIC */
struct i2c_client *i2c_haptic; /* MAX77693: 0x90 , Haptic */
struct i2c_client *i2c_chg; /* MAX77843: 0xD2, Charger */
enum max77693_types type;
struct regmap *regmap;
struct regmap *regmap_muic;
struct regmap *regmap_haptic; /* Only MAX77693 */
struct regmap *regmap_chg; /* Only MAX77843 */
struct regmap *regmap_leds; /* Only MAX77705 */
struct regmap_irq_chip_data *irq_data_led;
struct regmap_irq_chip_data *irq_data_topsys;
struct regmap_irq_chip_data *irq_data_chg; /* Only MAX77693 */
struct regmap_irq_chip_data *irq_data_muic;
int irq;
};
#endif /* __LINUX_MFD_MAX77693_COMMON_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77693-private.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max77693-private.h - Voltage regulator driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electronics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*/
#ifndef __LINUX_MFD_MAX77693_PRIV_H
#define __LINUX_MFD_MAX77693_PRIV_H
#include <linux/i2c.h>
#define MAX77693_REG_INVALID (0xff)
/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
enum max77693_pmic_reg {
MAX77693_LED_REG_IFLASH1 = 0x00,
MAX77693_LED_REG_IFLASH2 = 0x01,
MAX77693_LED_REG_ITORCH = 0x02,
MAX77693_LED_REG_ITORCHTIMER = 0x03,
MAX77693_LED_REG_FLASH_TIMER = 0x04,
MAX77693_LED_REG_FLASH_EN = 0x05,
MAX77693_LED_REG_MAX_FLASH1 = 0x06,
MAX77693_LED_REG_MAX_FLASH2 = 0x07,
MAX77693_LED_REG_MAX_FLASH3 = 0x08,
MAX77693_LED_REG_MAX_FLASH4 = 0x09,
MAX77693_LED_REG_VOUT_CNTL = 0x0A,
MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
MAX77693_LED_REG_FLASH_INT = 0x0E,
MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
MAX77693_LED_REG_FLASH_STATUS = 0x10,
MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
MAX77693_PMIC_REG_INTSRC = 0x22,
MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
MAX77693_PMIC_REG_LSCNFG = 0x2B,
MAX77693_CHG_REG_CHG_INT = 0xB0,
MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
MAX77693_PMIC_REG_END,
};
/* MAX77693 ITORCH register */
#define TORCH_IOUT1_SHIFT 0
#define TORCH_IOUT2_SHIFT 4
#define TORCH_IOUT_MASK(x) (0xf << (x))
#define TORCH_IOUT_MIN 15625
#define TORCH_IOUT_MAX 250000
#define TORCH_IOUT_STEP 15625
/* MAX77693 IFLASH1 and IFLASH2 registers */
#define FLASH_IOUT_MIN 15625
#define FLASH_IOUT_MAX_1LED 1000000
#define FLASH_IOUT_MAX_2LEDS 625000
#define FLASH_IOUT_STEP 15625
/* MAX77693 TORCH_TIMER register */
#define TORCH_TMR_NO_TIMER 0x40
#define TORCH_TIMEOUT_MIN 262000
#define TORCH_TIMEOUT_MAX 15728000
/* MAX77693 FLASH_TIMER register */
#define FLASH_TMR_LEVEL 0x80
#define FLASH_TIMEOUT_MIN 62500
#define FLASH_TIMEOUT_MAX 1000000
#define FLASH_TIMEOUT_STEP 62500
/* MAX77693 FLASH_EN register */
#define FLASH_EN_OFF 0x0
#define FLASH_EN_FLASH 0x1
#define FLASH_EN_TORCH 0x2
#define FLASH_EN_ON 0x3
#define FLASH_EN_SHIFT(x) (6 - (x) * 2)
#define TORCH_EN_SHIFT(x) (2 - (x) * 2)
/* MAX77693 MAX_FLASH1 register */
#define MAX_FLASH1_MAX_FL_EN 0x80
#define MAX_FLASH1_VSYS_MIN 2400
#define MAX_FLASH1_VSYS_MAX 3400
#define MAX_FLASH1_VSYS_STEP 33
/* MAX77693 VOUT_CNTL register */
#define FLASH_BOOST_FIXED 0x04
#define FLASH_BOOST_LEDNUM_2 0x80
/* MAX77693 VOUT_FLASH1 register */
#define FLASH_VOUT_MIN 3300
#define FLASH_VOUT_MAX 5500
#define FLASH_VOUT_STEP 25
#define FLASH_VOUT_RMIN 0x0c
/* MAX77693 FLASH_STATUS register */
#define FLASH_STATUS_FLASH_ON BIT(3)
#define FLASH_STATUS_TORCH_ON BIT(2)
/* MAX77693 FLASH_INT register */
#define FLASH_INT_FLED2_OPEN BIT(0)
#define FLASH_INT_FLED2_SHORT BIT(1)
#define FLASH_INT_FLED1_OPEN BIT(2)
#define FLASH_INT_FLED1_SHORT BIT(3)
#define FLASH_INT_OVER_CURRENT BIT(4)
/* Fast charge timer in hours */
#define DEFAULT_FAST_CHARGE_TIMER 4
/* microamps */
#define DEFAULT_TOP_OFF_THRESHOLD_CURRENT 150000
/* minutes */
#define DEFAULT_TOP_OFF_TIMER 30
/* microvolts */
#define DEFAULT_CONSTANT_VOLT 4200000
/* microvolts */
#define DEFAULT_MIN_SYSTEM_VOLT 3600000
/* celsius */
#define DEFAULT_THERMAL_REGULATION_TEMP 100
/* microamps */
#define DEFAULT_BATTERY_OVERCURRENT 3500000
/* microvolts */
#define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT 4300000
/* MAX77693_CHG_REG_CHG_INT_OK register */
#define CHG_INT_OK_BYP_SHIFT 0
#define CHG_INT_OK_BAT_SHIFT 3
#define CHG_INT_OK_CHG_SHIFT 4
#define CHG_INT_OK_CHGIN_SHIFT 6
#define CHG_INT_OK_DETBAT_SHIFT 7
#define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT)
#define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT)
#define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT)
#define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT)
#define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT)
/* MAX77693_CHG_REG_CHG_DETAILS_00 register */
#define CHG_DETAILS_00_CHGIN_SHIFT 5
#define CHG_DETAILS_00_CHGIN_MASK (0x3 << CHG_DETAILS_00_CHGIN_SHIFT)
/* MAX77693_CHG_REG_CHG_DETAILS_01 register */
#define CHG_DETAILS_01_CHG_SHIFT 0
#define CHG_DETAILS_01_BAT_SHIFT 4
#define CHG_DETAILS_01_TREG_SHIFT 7
#define CHG_DETAILS_01_CHG_MASK (0xf << CHG_DETAILS_01_CHG_SHIFT)
#define CHG_DETAILS_01_BAT_MASK (0x7 << CHG_DETAILS_01_BAT_SHIFT)
#define CHG_DETAILS_01_TREG_MASK BIT(7)
/* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */
enum max77693_charger_charging_state {
MAX77693_CHARGING_PREQUALIFICATION = 0x0,
MAX77693_CHARGING_FAST_CONST_CURRENT,
MAX77693_CHARGING_FAST_CONST_VOLTAGE,
MAX77693_CHARGING_TOP_OFF,
MAX77693_CHARGING_DONE,
MAX77693_CHARGING_HIGH_TEMP,
MAX77693_CHARGING_TIMER_EXPIRED,
MAX77693_CHARGING_THERMISTOR_SUSPEND,
MAX77693_CHARGING_OFF,
MAX77693_CHARGING_RESERVED,
MAX77693_CHARGING_OVER_TEMP,
MAX77693_CHARGING_WATCHDOG_EXPIRED,
};
/* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */
enum max77693_charger_battery_state {
MAX77693_BATTERY_NOBAT = 0x0,
/* Dead-battery or low-battery prequalification */
MAX77693_BATTERY_PREQUALIFICATION,
MAX77693_BATTERY_TIMER_EXPIRED,
MAX77693_BATTERY_GOOD,
MAX77693_BATTERY_LOWVOLTAGE,
MAX77693_BATTERY_OVERVOLTAGE,
MAX77693_BATTERY_OVERCURRENT,
MAX77693_BATTERY_RESERVED,
};
/* MAX77693_CHG_REG_CHG_DETAILS_02 register */
#define CHG_DETAILS_02_BYP_SHIFT 0
#define CHG_DETAILS_02_BYP_MASK (0xf << CHG_DETAILS_02_BYP_SHIFT)
/* MAX77693 CHG_CNFG_00 register */
#define CHG_CNFG_00_CHG_MASK 0x1
#define CHG_CNFG_00_BUCK_MASK 0x4
/* MAX77693_CHG_REG_CHG_CNFG_01 register */
#define CHG_CNFG_01_FCHGTIME_SHIFT 0
#define CHG_CNFG_01_CHGRSTRT_SHIFT 4
#define CHG_CNFG_01_PQEN_SHIFT 7
#define CHG_CNFG_01_FCHGTIME_MASK (0x7 << CHG_CNFG_01_FCHGTIME_SHIFT)
#define CHG_CNFG_01_CHGRSTRT_MASK (0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT)
#define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT)
/* MAX77693_CHG_REG_CHG_CNFG_02 register */
#define CHG_CNFG_02_CC_SHIFT 0
#define CHG_CNFG_02_CC_MASK 0x3F
/* MAX77693_CHG_REG_CHG_CNFG_03 register */
#define CHG_CNFG_03_TOITH_SHIFT 0
#define CHG_CNFG_03_TOTIME_SHIFT 3
#define CHG_CNFG_03_TOITH_MASK (0x7 << CHG_CNFG_03_TOITH_SHIFT)
#define CHG_CNFG_03_TOTIME_MASK (0x7 << CHG_CNFG_03_TOTIME_SHIFT)
/* MAX77693_CHG_REG_CHG_CNFG_04 register */
#define CHG_CNFG_04_CHGCVPRM_SHIFT 0
#define CHG_CNFG_04_MINVSYS_SHIFT 5
#define CHG_CNFG_04_CHGCVPRM_MASK (0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT)
#define CHG_CNFG_04_MINVSYS_MASK (0x7 << CHG_CNFG_04_MINVSYS_SHIFT)
/* MAX77693_CHG_REG_CHG_CNFG_06 register */
#define CHG_CNFG_06_CHGPROT_SHIFT 2
#define CHG_CNFG_06_CHGPROT_MASK (0x3 << CHG_CNFG_06_CHGPROT_SHIFT)
/* MAX77693_CHG_REG_CHG_CNFG_07 register */
#define CHG_CNFG_07_REGTEMP_SHIFT 5
#define CHG_CNFG_07_REGTEMP_MASK (0x3 << CHG_CNFG_07_REGTEMP_SHIFT)
/* MAX77693_CHG_REG_CHG_CNFG_12 register */
#define CHG_CNFG_12_B2SOVRC_SHIFT 0
#define CHG_CNFG_12_VCHGINREG_SHIFT 3
#define CHG_CNFG_12_B2SOVRC_MASK (0x7 << CHG_CNFG_12_B2SOVRC_SHIFT)
#define CHG_CNFG_12_VCHGINREG_MASK (0x3 << CHG_CNFG_12_VCHGINREG_SHIFT)
/* MAX77693 CHG_CNFG_09 Register */
#define CHG_CNFG_09_CHGIN_ILIM_SHIFT 0
#define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
/* MAX77693 CHG_CTRL Register */
#define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
#define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
#define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
#define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
/* Slave addr = 0x4A: MUIC */
enum max77693_muic_reg {
MAX77693_MUIC_REG_ID = 0x00,
MAX77693_MUIC_REG_INT1 = 0x01,
MAX77693_MUIC_REG_INT2 = 0x02,
MAX77693_MUIC_REG_INT3 = 0x03,
MAX77693_MUIC_REG_STATUS1 = 0x04,
MAX77693_MUIC_REG_STATUS2 = 0x05,
MAX77693_MUIC_REG_STATUS3 = 0x06,
MAX77693_MUIC_REG_INTMASK1 = 0x07,
MAX77693_MUIC_REG_INTMASK2 = 0x08,
MAX77693_MUIC_REG_INTMASK3 = 0x09,
MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
MAX77693_MUIC_REG_CTRL1 = 0x0C,
MAX77693_MUIC_REG_CTRL2 = 0x0D,
MAX77693_MUIC_REG_CTRL3 = 0x0E,
MAX77693_MUIC_REG_END,
};
/* MAX77693 INTMASK1~2 Register */
#define INTMASK1_ADC1K_SHIFT 3
#define INTMASK1_ADCERR_SHIFT 2
#define INTMASK1_ADCLOW_SHIFT 1
#define INTMASK1_ADC_SHIFT 0
#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
#define INTMASK2_VIDRM_SHIFT 5
#define INTMASK2_VBVOLT_SHIFT 4
#define INTMASK2_DXOVP_SHIFT 3
#define INTMASK2_DCDTMR_SHIFT 2
#define INTMASK2_CHGDETRUN_SHIFT 1
#define INTMASK2_CHGTYP_SHIFT 0
#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
/* MAX77693 MUIC - STATUS1~3 Register */
#define MAX77693_STATUS1_ADC_SHIFT 0
#define MAX77693_STATUS1_ADCLOW_SHIFT 5
#define MAX77693_STATUS1_ADCERR_SHIFT 6
#define MAX77693_STATUS1_ADC1K_SHIFT 7
#define MAX77693_STATUS1_ADC_MASK (0x1f << MAX77693_STATUS1_ADC_SHIFT)
#define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT)
#define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT)
#define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT)
#define MAX77693_STATUS2_CHGTYP_SHIFT 0
#define MAX77693_STATUS2_CHGDETRUN_SHIFT 3
#define MAX77693_STATUS2_DCDTMR_SHIFT 4
#define MAX77693_STATUS2_DXOVP_SHIFT 5
#define MAX77693_STATUS2_VBVOLT_SHIFT 6
#define MAX77693_STATUS2_VIDRM_SHIFT 7
#define MAX77693_STATUS2_CHGTYP_MASK (0x7 << MAX77693_STATUS2_CHGTYP_SHIFT)
#define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT)
#define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT)
#define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT)
#define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT)
#define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT)
#define MAX77693_STATUS3_OVP_SHIFT 2
#define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT)
/* MAX77693 CDETCTRL1~2 register */
#define CDETCTRL1_CHGDETEN_SHIFT (0)
#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
#define CDETCTRL1_DCDEN_SHIFT (2)
#define CDETCTRL1_DCD2SCT_SHIFT (3)
#define CDETCTRL1_CDDELAY_SHIFT (4)
#define CDETCTRL1_DCDCPL_SHIFT (5)
#define CDETCTRL1_CDPDET_SHIFT (7)
#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
#define CDETCTRL2_VIDRMEN_SHIFT (1)
#define CDETCTRL2_DXOVPEN_SHIFT (3)
#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
/* MAX77693 MUIC - CONTROL1~3 register */
#define COMN1SW_SHIFT (0)
#define COMP2SW_SHIFT (3)
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
#define MAX77693_CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
| (1 << COMN1SW_SHIFT))
#define MAX77693_CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
| (2 << COMN1SW_SHIFT))
#define MAX77693_CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
| (3 << COMN1SW_SHIFT))
#define MAX77693_CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
| (0 << COMN1SW_SHIFT))
#define MAX77693_CONTROL2_LOWPWR_SHIFT 0
#define MAX77693_CONTROL2_ADCEN_SHIFT 1
#define MAX77693_CONTROL2_CPEN_SHIFT 2
#define MAX77693_CONTROL2_SFOUTASRT_SHIFT 3
#define MAX77693_CONTROL2_SFOUTORD_SHIFT 4
#define MAX77693_CONTROL2_ACCDET_SHIFT 5
#define MAX77693_CONTROL2_USBCPINT_SHIFT 6
#define MAX77693_CONTROL2_RCPS_SHIFT 7
#define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT)
#define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT)
#define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT)
#define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT)
#define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT)
#define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT)
#define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT)
#define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT)
#define MAX77693_CONTROL3_JIGSET_SHIFT 0
#define MAX77693_CONTROL3_BTLDSET_SHIFT 2
#define MAX77693_CONTROL3_ADCDBSET_SHIFT 4
#define MAX77693_CONTROL3_JIGSET_MASK (0x3 << MAX77693_CONTROL3_JIGSET_SHIFT)
#define MAX77693_CONTROL3_BTLDSET_MASK (0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT)
#define MAX77693_CONTROL3_ADCDBSET_MASK (0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT)
/* Slave addr = 0x90: Haptic */
enum max77693_haptic_reg {
MAX77693_HAPTIC_REG_STATUS = 0x00,
MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
MAX77693_HAPTIC_REG_REV = 0x10,
MAX77693_HAPTIC_REG_END,
};
/* max77693-pmic LSCNFG configuration register */
#define MAX77693_PMIC_LOW_SYS_MASK 0x80
#define MAX77693_PMIC_LOW_SYS_SHIFT 7
/* max77693-haptic configuration register */
#define MAX77693_CONFIG2_MODE 7
#define MAX77693_CONFIG2_MEN 6
#define MAX77693_CONFIG2_HTYP 5
#define SRC_IRQ_CHARGER BIT(0)
#define SRC_IRQ_TOP BIT(1)
#define SRC_IRQ_FLASH BIT(2)
#define SRC_IRQ_MUIC BIT(3)
#define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \
| SRC_IRQ_FLASH | SRC_IRQ_MUIC)
#define LED_IRQ_FLED2_OPEN BIT(0)
#define LED_IRQ_FLED2_SHORT BIT(1)
#define LED_IRQ_FLED1_OPEN BIT(2)
#define LED_IRQ_FLED1_SHORT BIT(3)
#define LED_IRQ_MAX_FLASH BIT(4)
#define TOPSYS_IRQ_T120C_INT BIT(0)
#define TOPSYS_IRQ_T140C_INT BIT(1)
#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
#define CHG_IRQ_BYP_I BIT(0)
#define CHG_IRQ_THM_I BIT(2)
#define CHG_IRQ_BAT_I BIT(3)
#define CHG_IRQ_CHG_I BIT(4)
#define CHG_IRQ_CHGIN_I BIT(6)
#define MUIC_IRQ_INT1_ADC BIT(0)
#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
#define MUIC_IRQ_INT1_ADC1K BIT(3)
#define MUIC_IRQ_INT2_CHGTYP BIT(0)
#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
#define MUIC_IRQ_INT2_DCDTMR BIT(2)
#define MUIC_IRQ_INT2_DXOVP BIT(3)
#define MUIC_IRQ_INT2_VBVOLT BIT(4)
#define MUIC_IRQ_INT2_VIDRM BIT(5)
#define MUIC_IRQ_INT3_EOC BIT(0)
#define MUIC_IRQ_INT3_CGMBC BIT(1)
#define MUIC_IRQ_INT3_OVP BIT(2)
#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
#define MUIC_IRQ_INT3_BAT_DET BIT(5)
enum max77693_irq {
/* PMIC - FLASH */
MAX77693_LED_IRQ_FLED2_OPEN,
MAX77693_LED_IRQ_FLED2_SHORT,
MAX77693_LED_IRQ_FLED1_OPEN,
MAX77693_LED_IRQ_FLED1_SHORT,
MAX77693_LED_IRQ_MAX_FLASH,
/* PMIC - TOPSYS */
MAX77693_TOPSYS_IRQ_T120C_INT,
MAX77693_TOPSYS_IRQ_T140C_INT,
MAX77693_TOPSYS_IRQ_LOWSYS_INT,
/* PMIC - Charger */
MAX77693_CHG_IRQ_BYP_I,
MAX77693_CHG_IRQ_THM_I,
MAX77693_CHG_IRQ_BAT_I,
MAX77693_CHG_IRQ_CHG_I,
MAX77693_CHG_IRQ_CHGIN_I,
MAX77693_IRQ_NR,
};
enum max77693_irq_muic {
/* MUIC INT1 */
MAX77693_MUIC_IRQ_INT1_ADC,
MAX77693_MUIC_IRQ_INT1_ADC_LOW,
MAX77693_MUIC_IRQ_INT1_ADC_ERR,
MAX77693_MUIC_IRQ_INT1_ADC1K,
/* MUIC INT2 */
MAX77693_MUIC_IRQ_INT2_CHGTYP,
MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
MAX77693_MUIC_IRQ_INT2_DCDTMR,
MAX77693_MUIC_IRQ_INT2_DXOVP,
MAX77693_MUIC_IRQ_INT2_VBVOLT,
MAX77693_MUIC_IRQ_INT2_VIDRM,
/* MUIC INT3 */
MAX77693_MUIC_IRQ_INT3_EOC,
MAX77693_MUIC_IRQ_INT3_CGMBC,
MAX77693_MUIC_IRQ_INT3_OVP,
MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
MAX77693_MUIC_IRQ_INT3_BAT_DET,
MAX77693_MUIC_IRQ_NR,
};
#endif /* __LINUX_MFD_MAX77693_PRIV_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77693.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* max77693.h - Driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electronics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*
* This driver is based on max8997.h
*
* MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __LINUX_MFD_MAX77693_H
#define __LINUX_MFD_MAX77693_H
/* MAX77693 regulator IDs */
enum max77693_regulators {
MAX77693_ESAFEOUT1 = 0,
MAX77693_ESAFEOUT2,
MAX77693_CHARGER,
MAX77693_REG_MAX,
};
struct max77693_reg_data {
u8 addr;
u8 data;
};
struct max77693_muic_platform_data {
struct max77693_reg_data *init_data;
int num_init_data;
int detcable_delay_ms;
/*
* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
* h/w path of COMP2/COMN1 on CONTROL1 register.
*/
int path_usb;
int path_uart;
};
/* MAX77693 led flash */
/* triggers */
enum max77693_led_trigger {
MAX77693_LED_TRIG_OFF,
MAX77693_LED_TRIG_FLASH,
MAX77693_LED_TRIG_TORCH,
MAX77693_LED_TRIG_EXT,
MAX77693_LED_TRIG_SOFT,
};
/* trigger types */
enum max77693_led_trigger_type {
MAX77693_LED_TRIG_TYPE_EDGE,
MAX77693_LED_TRIG_TYPE_LEVEL,
};
/* boost modes */
enum max77693_led_boost_mode {
MAX77693_LED_BOOST_NONE,
MAX77693_LED_BOOST_ADAPTIVE,
MAX77693_LED_BOOST_FIXED,
};
/* MAX77693 */
struct max77693_platform_data {
/* muic data */
struct max77693_muic_platform_data *muic_data;
struct max77693_led_platform_data *led_data;
};
#endif /* __LINUX_MFD_MAX77693_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77705-private.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Maxim MAX77705 definitions.
*
* Copyright (C) 2015 Samsung Electronics, Inc.
* Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com>
*/
#ifndef __LINUX_MFD_MAX77705_PRIV_H
#define __LINUX_MFD_MAX77705_PRIV_H
#define MAX77705_SRC_IRQ_CHG BIT(0)
#define MAX77705_SRC_IRQ_TOP BIT(1)
#define MAX77705_SRC_IRQ_FG BIT(2)
#define MAX77705_SRC_IRQ_USBC BIT(3)
#define MAX77705_SRC_IRQ_ALL (MAX77705_SRC_IRQ_CHG | MAX77705_SRC_IRQ_TOP | \
MAX77705_SRC_IRQ_FG | MAX77705_SRC_IRQ_USBC)
/* MAX77705_PMIC_REG_PMICREV register */
#define MAX77705_VERSION_SHIFT 3
#define MAX77705_REVISION_MASK GENMASK(2, 0)
#define MAX77705_VERSION_MASK GENMASK(7, MAX77705_VERSION_SHIFT)
/* MAX77705_PMIC_REG_MAINCTRL1 register */
#define MAX77705_MAINCTRL1_BIASEN_SHIFT 7
#define MAX77705_MAINCTRL1_BIASEN_MASK BIT(MAX77705_MAINCTRL1_BIASEN_SHIFT)
/* MAX77705_PMIC_REG_MCONFIG2 (haptics) register */
#define MAX77705_CONFIG2_MEN_SHIFT 6
#define MAX77705_CONFIG2_MODE_SHIFT 7
#define MAX77705_CONFIG2_HTYP_SHIFT 5
/* MAX77705_PMIC_REG_SYSTEM_INT_MASK register */
#define MAX77705_SYSTEM_IRQ_BSTEN_INT BIT(3)
#define MAX77705_SYSTEM_IRQ_SYSUVLO_INT BIT(4)
#define MAX77705_SYSTEM_IRQ_SYSOVLO_INT BIT(5)
#define MAX77705_SYSTEM_IRQ_TSHDN_INT BIT(6)
#define MAX77705_SYSTEM_IRQ_TM_INT BIT(7)
/* MAX77705_RGBLED_REG_LEDEN register */
#define MAX77705_RGBLED_EN_WIDTH 2
/* MAX77705_RGBLED_REG_LEDBLNK register */
#define MAX77705_RGB_DELAY_100_STEP_LIM 500
#define MAX77705_RGB_DELAY_100_STEP_COUNT 4
#define MAX77705_RGB_DELAY_100_STEP 100
#define MAX77705_RGB_DELAY_250_STEP_LIM 3250
#define MAX77705_RGB_DELAY_250_STEP 250
#define MAX77705_RGB_DELAY_500_STEP 500
#define MAX77705_RGB_DELAY_500_STEP_COUNT 10
#define MAX77705_RGB_DELAY_500_STEP_LIM 5000
#define MAX77705_RGB_DELAY_1000_STEP_LIM 8000
#define MAX77705_RGB_DELAY_1000_STEP_COUNT 13
#define MAX77705_RGB_DELAY_1000_STEP 1000
#define MAX77705_RGB_DELAY_2000_STEP 2000
#define MAX77705_RGB_DELAY_2000_STEP_COUNT 13
#define MAX77705_RGB_DELAY_2000_STEP_LIM 12000
enum max77705_hw_rev {
MAX77705_PASS1 = 1,
MAX77705_PASS2,
MAX77705_PASS3
};
enum max77705_reg {
MAX77705_PMIC_REG_PMICID1 = 0x00,
MAX77705_PMIC_REG_PMICREV = 0x01,
MAX77705_PMIC_REG_MAINCTRL1 = 0x02,
MAX77705_PMIC_REG_BSTOUT_MASK = 0x03,
MAX77705_PMIC_REG_FORCE_EN_MASK = 0x08,
MAX77705_PMIC_REG_MCONFIG = 0x10,
MAX77705_PMIC_REG_MCONFIG2 = 0x11,
MAX77705_PMIC_REG_INTSRC = 0x22,
MAX77705_PMIC_REG_INTSRC_MASK = 0x23,
MAX77705_PMIC_REG_SYSTEM_INT = 0x24,
MAX77705_PMIC_REG_RESERVED_25 = 0x25,
MAX77705_PMIC_REG_SYSTEM_INT_MASK = 0x26,
MAX77705_PMIC_REG_RESERVED_27 = 0x27,
MAX77705_PMIC_REG_RESERVED_28 = 0x28,
MAX77705_PMIC_REG_RESERVED_29 = 0x29,
MAX77705_PMIC_REG_BOOSTCONTROL1 = 0x4C,
MAX77705_PMIC_REG_BOOSTCONTROL2 = 0x4F,
MAX77705_PMIC_REG_SW_RESET = 0x50,
MAX77705_PMIC_REG_USBC_RESET = 0x51,
MAX77705_PMIC_REG_END
};
enum max77705_chg_reg {
MAX77705_CHG_REG_BASE = 0xB0,
MAX77705_CHG_REG_INT = 0,
MAX77705_CHG_REG_INT_MASK,
MAX77705_CHG_REG_INT_OK,
MAX77705_CHG_REG_DETAILS_00,
MAX77705_CHG_REG_DETAILS_01,
MAX77705_CHG_REG_DETAILS_02,
MAX77705_CHG_REG_DTLS_03,
MAX77705_CHG_REG_CNFG_00,
MAX77705_CHG_REG_CNFG_01,
MAX77705_CHG_REG_CNFG_02,
MAX77705_CHG_REG_CNFG_03,
MAX77705_CHG_REG_CNFG_04,
MAX77705_CHG_REG_CNFG_05,
MAX77705_CHG_REG_CNFG_06,
MAX77705_CHG_REG_CNFG_07,
MAX77705_CHG_REG_CNFG_08,
MAX77705_CHG_REG_CNFG_09,
MAX77705_CHG_REG_CNFG_10,
MAX77705_CHG_REG_CNFG_11,
MAX77705_CHG_REG_CNFG_12,
MAX77705_CHG_REG_CNFG_13,
MAX77705_CHG_REG_CNFG_14,
MAX77705_CHG_REG_SAFEOUT_CTRL
};
enum max77705_fuelgauge_reg {
STATUS_REG = 0x00,
VALRT_THRESHOLD_REG = 0x01,
TALRT_THRESHOLD_REG = 0x02,
SALRT_THRESHOLD_REG = 0x03,
REMCAP_REP_REG = 0x05,
SOCREP_REG = 0x06,
TEMPERATURE_REG = 0x08,
VCELL_REG = 0x09,
TIME_TO_EMPTY_REG = 0x11,
FULLSOCTHR_REG = 0x13,
CURRENT_REG = 0x0A,
AVG_CURRENT_REG = 0x0B,
SOCMIX_REG = 0x0D,
SOCAV_REG = 0x0E,
REMCAP_MIX_REG = 0x0F,
FULLCAP_REG = 0x10,
RFAST_REG = 0x15,
AVR_TEMPERATURE_REG = 0x16,
CYCLES_REG = 0x17,
DESIGNCAP_REG = 0x18,
AVR_VCELL_REG = 0x19,
TIME_TO_FULL_REG = 0x20,
CONFIG_REG = 0x1D,
ICHGTERM_REG = 0x1E,
REMCAP_AV_REG = 0x1F,
FULLCAP_NOM_REG = 0x23,
LEARN_CFG_REG = 0x28,
FILTER_CFG_REG = 0x29,
MISCCFG_REG = 0x2B,
QRTABLE20_REG = 0x32,
FULLCAP_REP_REG = 0x35,
RCOMP_REG = 0x38,
VEMPTY_REG = 0x3A,
FSTAT_REG = 0x3D,
DISCHARGE_THRESHOLD_REG = 0x40,
QRTABLE30_REG = 0x42,
ISYS_REG = 0x43,
DQACC_REG = 0x45,
DPACC_REG = 0x46,
AVGISYS_REG = 0x4B,
QH_REG = 0x4D,
VSYS_REG = 0xB1,
TALRTTH2_REG = 0xB2,
VBYP_REG = 0xB3,
CONFIG2_REG = 0xBB,
IIN_REG = 0xD0,
OCV_REG = 0xEE,
VFOCV_REG = 0xFB,
VFSOC_REG = 0xFF,
MAX77705_FG_END
};
enum max77705_led_reg {
MAX77705_RGBLED_REG_BASE = 0x30,
MAX77705_RGBLED_REG_LEDEN = 0,
MAX77705_RGBLED_REG_LED0BRT,
MAX77705_RGBLED_REG_LED1BRT,
MAX77705_RGBLED_REG_LED2BRT,
MAX77705_RGBLED_REG_LED3BRT,
MAX77705_RGBLED_REG_LEDRMP,
MAX77705_RGBLED_REG_LEDBLNK,
MAX77705_LED_REG_END
};
enum max77705_charger_battery_state {
MAX77705_BATTERY_NOBAT,
MAX77705_BATTERY_PREQUALIFICATION,
MAX77705_BATTERY_DEAD,
MAX77705_BATTERY_GOOD,
MAX77705_BATTERY_LOWVOLTAGE,
MAX77705_BATTERY_OVERVOLTAGE,
MAX77705_BATTERY_RESERVED
};
enum max77705_charger_charge_type {
MAX77705_CHARGER_CONSTANT_CURRENT = 1,
MAX77705_CHARGER_CONSTANT_VOLTAGE,
MAX77705_CHARGER_END_OF_CHARGE,
MAX77705_CHARGER_DONE
};
#endif /* __LINUX_MFD_MAX77705_PRIV_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77714.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Maxim MAX77714 Register and data structures definition.
*
* Copyright (C) 2022 Luca Ceresoli
* Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
*/
#ifndef __LINUX_MFD_MAX77714_H_
#define __LINUX_MFD_MAX77714_H_
#include <linux/bits.h>
#define MAX77714_INT_TOP 0x00
#define MAX77714_INT_TOPM 0x07 /* Datasheet says "read only", but it is RW */
#define MAX77714_INT_TOP_ONOFF BIT(1)
#define MAX77714_INT_TOP_RTC BIT(3)
#define MAX77714_INT_TOP_GPIO BIT(4)
#define MAX77714_INT_TOP_LDO BIT(5)
#define MAX77714_INT_TOP_SD BIT(6)
#define MAX77714_INT_TOP_GLBL BIT(7)
#define MAX77714_32K_STATUS 0x30
#define MAX77714_32K_STATUS_SIOSCOK BIT(5)
#define MAX77714_32K_STATUS_XOSCOK BIT(4)
#define MAX77714_32K_STATUS_32KSOURCE BIT(3)
#define MAX77714_32K_STATUS_32KLOAD_MSK 0x3
#define MAX77714_32K_STATUS_32KLOAD_SHF 1
#define MAX77714_32K_STATUS_CRYSTAL_CFG BIT(0)
#define MAX77714_32K_CONFIG 0x31
#define MAX77714_32K_CONFIG_XOSC_RETRY BIT(4)
#define MAX77714_CNFG_GLBL2 0x91
#define MAX77714_WDTEN BIT(2)
#define MAX77714_WDTSLPC BIT(3)
#define MAX77714_TWD_MASK 0x3
#define MAX77714_TWD_2s 0x0
#define MAX77714_TWD_16s 0x1
#define MAX77714_TWD_64s 0x2
#define MAX77714_TWD_128s 0x3
#define MAX77714_CNFG_GLBL3 0x92
#define MAX77714_WDTC BIT(0)
#define MAX77714_CNFG2_ONOFF 0x94
#define MAX77714_WD_RST_WK BIT(5)
/* Interrupts */
enum {
MAX77714_IRQ_TOP_ONOFF,
MAX77714_IRQ_TOP_RTC, /* Real-time clock */
MAX77714_IRQ_TOP_GPIO, /* GPIOs */
MAX77714_IRQ_TOP_LDO, /* Low-dropout regulators */
MAX77714_IRQ_TOP_SD, /* Step-down regulators */
MAX77714_IRQ_TOP_GLBL, /* "Global resources": Low-Battery, overtemp... */
};
#endif /* __LINUX_MFD_MAX77714_H_ */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77759.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2020 Google Inc.
* Copyright 2025 Linaro Ltd.
*
* Maxim MAX77759 core driver
*/
#ifndef __LINUX_MFD_MAX77759_H
#define __LINUX_MFD_MAX77759_H
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#define MAX77759_PMIC_REG_PMIC_ID 0x00
#define MAX77759_PMIC_REG_PMIC_REVISION 0x01
#define MAX77759_PMIC_REG_OTP_REVISION 0x02
#define MAX77759_PMIC_REG_INTSRC 0x22
#define MAX77759_PMIC_REG_INTSRCMASK 0x23
#define MAX77759_PMIC_REG_INTSRC_MAXQ BIT(3)
#define MAX77759_PMIC_REG_INTSRC_TOPSYS BIT(1)
#define MAX77759_PMIC_REG_INTSRC_CHGR BIT(0)
#define MAX77759_PMIC_REG_TOPSYS_INT 0x24
#define MAX77759_PMIC_REG_TOPSYS_INT_MASK 0x26
#define MAX77759_PMIC_REG_TOPSYS_INT_TSHDN BIT(6)
#define MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO BIT(5)
#define MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO BIT(4)
#define MAX77759_PMIC_REG_TOPSYS_INT_FSHIP BIT(0)
#define MAX77759_PMIC_REG_I2C_CNFG 0x40
#define MAX77759_PMIC_REG_SWRESET 0x50
#define MAX77759_PMIC_REG_CONTROL_FG 0x51
#define MAX77759_MAXQ_REG_UIC_INT1 0x64
#define MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI BIT(7)
#define MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI BIT(6)
#define MAX77759_MAXQ_REG_UIC_INT1_GPIO6I BIT(1)
#define MAX77759_MAXQ_REG_UIC_INT1_GPIO5I BIT(0)
#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, en) (((en) & 1) << (offs))
#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(offs) \
MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, ~0)
#define MAX77759_MAXQ_REG_UIC_INT2 0x65
#define MAX77759_MAXQ_REG_UIC_INT3 0x66
#define MAX77759_MAXQ_REG_UIC_INT4 0x67
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS1 0x68
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS2 0x69
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS3 0x6a
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS4 0x6b
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS5 0x6c
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS6 0x6d
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS7 0x6f
#define MAX77759_MAXQ_REG_UIC_UIC_STATUS8 0x6f
#define MAX77759_MAXQ_REG_UIC_INT1_M 0x70
#define MAX77759_MAXQ_REG_UIC_INT2_M 0x71
#define MAX77759_MAXQ_REG_UIC_INT3_M 0x72
#define MAX77759_MAXQ_REG_UIC_INT4_M 0x73
#define MAX77759_MAXQ_REG_AP_DATAOUT0 0x81
#define MAX77759_MAXQ_REG_AP_DATAOUT32 0xa1
#define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1
#define MAX77759_MAXQ_REG_UIC_SWRST 0xe0
#define MAX77759_CHGR_REG_CHG_INT 0xb0
#define MAX77759_CHGR_REG_CHG_INT_AICL BIT(7)
#define MAX77759_CHGR_REG_CHG_INT_CHGIN BIT(6)
#define MAX77759_CHGR_REG_CHG_INT_WCIN BIT(5)
#define MAX77759_CHGR_REG_CHG_INT_CHG BIT(4)
#define MAX77759_CHGR_REG_CHG_INT_BAT BIT(3)
#define MAX77759_CHGR_REG_CHG_INT_INLIM BIT(2)
#define MAX77759_CHGR_REG_CHG_INT_THM2 BIT(1)
#define MAX77759_CHGR_REG_CHG_INT_BYP BIT(0)
#define MAX77759_CHGR_REG_CHG_INT2 0xb1
#define MAX77759_CHGR_REG_CHG_INT2_INSEL BIT(7)
#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1 BIT(6)
#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2 BIT(5)
#define MAX77759_CHGR_REG_CHG_INT2_BAT_OILO BIT(4)
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC BIT(3)
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV BIT(2)
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO BIT(1)
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE BIT(0)
#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
#define MAX77759_CHGR_REG_CHG_DETAILS_00_CHGIN_DTLS GENMASK(6, 5)
#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
#define MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS GENMASK(6, 4)
#define MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS GENMASK(3, 0)
#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
#define MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS BIT(5)
#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
#define MAX77759_CHGR_REG_CHG_CNFG_00_MODE GENMASK(3, 0)
#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
#define MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC GENMASK(5, 0)
#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
#define MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM GENMASK(5, 0)
#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
#define MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT GENMASK(3, 2)
#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
#define MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM GENMASK(6, 0)
#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
/* Wireless Charging input channel select */
#define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6)
/* CHGIN/USB input channel select */
#define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5)
#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
#define MAX77759_CHGR_REG_CHG_CNFG_18_WDTEN BIT(0)
#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
/* MaxQ opcodes for max77759_maxq_command() */
#define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \
MAX77759_MAXQ_REG_AP_DATAOUT0 + \
1)
#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ 0x21
#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE 0x22
#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ 0x23
#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24
#define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81
#define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82
/**
* enum max77759_chgr_chgin_dtls_status - Charger Input Status
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE:
* Charger input voltage (Vchgin) < Under Voltage Threshold (Vuvlo)
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE:
* Vchgin > Vuvlo and Vchgin < (Battery Voltage (Vbatt) + system voltage (Vsys))
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE:
* Vchgin > Over Voltage threshold (Vovlo)
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID:
* Vchgin > Vuvlo, Vchgin < Vovlo and Vchgin > (Vsys + Vbatt)
*/
enum max77759_chgr_chgin_dtls_status {
MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE,
MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE,
MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE,
MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID,
};
/**
* enum max77759_chgr_bat_dtls_states - Battery Details
* @MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP: No battery and the charger suspended
* @MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY: Vbatt < Vtrickle
* @MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT: Charging suspended due to timer fault
* @MAX77759_CHGR_BAT_DTLS_BAT_OKAY: Battery okay and Vbatt > Min Sys Voltage (Vsysmin)
* @MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE: Battery is okay. Vtrickle < Vbatt < Vsysmin
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE: Battery voltage > Overvoltage threshold
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT: Battery current exceeds overcurrent threshold
* @MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE: Battery only mode and battery level not available
*/
enum max77759_chgr_bat_dtls_states {
MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP,
MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY,
MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT,
MAX77759_CHGR_BAT_DTLS_BAT_OKAY,
MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE,
MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE,
MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT,
MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE,
};
/**
* enum max77759_chgr_chg_dtls_states - Charger Details
* @MAX77759_CHGR_CHG_DTLS_PREQUAL: Charger in prequalification mode
* @MAX77759_CHGR_CHG_DTLS_CC: Charger in fast charge const curr mode
* @MAX77759_CHGR_CHG_DTLS_CV: Charger in fast charge const voltage mode
* @MAX77759_CHGR_CHG_DTLS_TO: Charger is in top off mode
* @MAX77759_CHGR_CHG_DTLS_DONE: Charger is done
* @MAX77759_CHGR_CHG_DTLS_RSVD_1: Reserved
* @MAX77759_CHGR_CHG_DTLS_TIMER_FAULT: Charger is in timer fault mode
* @MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM: Charger is suspended as battery removal detected
* @MAX77759_CHGR_CHG_DTLS_OFF: Charger is off. Input invalid or charger disabled
* @MAX77759_CHGR_CHG_DTLS_RSVD_2: Reserved
* @MAX77759_CHGR_CHG_DTLS_RSVD_3: Reserved
* @MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER: Charger is off as watchdog timer expired
* @MAX77759_CHGR_CHG_DTLS_SUSP_JEITA: Charger is in JEITA control mode
*/
enum max77759_chgr_chg_dtls_states {
MAX77759_CHGR_CHG_DTLS_PREQUAL,
MAX77759_CHGR_CHG_DTLS_CC,
MAX77759_CHGR_CHG_DTLS_CV,
MAX77759_CHGR_CHG_DTLS_TO,
MAX77759_CHGR_CHG_DTLS_DONE,
MAX77759_CHGR_CHG_DTLS_RSVD_1,
MAX77759_CHGR_CHG_DTLS_TIMER_FAULT,
MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM,
MAX77759_CHGR_CHG_DTLS_OFF,
MAX77759_CHGR_CHG_DTLS_RSVD_2,
MAX77759_CHGR_CHG_DTLS_RSVD_3,
MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER,
MAX77759_CHGR_CHG_DTLS_SUSP_JEITA,
};
enum max77759_chgr_mode {
MAX77759_CHGR_MODE_OFF,
MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5,
MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA,
};
/**
* struct max77759 - core max77759 internal data structure
*
* @regmap_top: Regmap for accessing TOP registers
* @maxq_lock: Lock for serializing access to MaxQ
* @regmap_maxq: Regmap for accessing MaxQ registers
* @cmd_done: Used to signal completion of a MaxQ command
* @regmap_charger: Regmap for accessing charger registers
*
* The MAX77759 comprises several sub-blocks, namely TOP, MaxQ, Charger,
* Fuel Gauge, and TCPCI.
*/
struct max77759 {
struct regmap *regmap_top;
/* This protects MaxQ commands - only one can be active */
struct mutex maxq_lock;
struct regmap *regmap_maxq;
struct completion cmd_done;
struct regmap *regmap_charger;
};
/**
* struct max77759_maxq_command - structure containing the MaxQ command to
* send
*
* @length: The number of bytes to send.
* @cmd: The data to send.
*/
struct max77759_maxq_command {
u8 length;
u8 cmd[] __counted_by(length);
};
/**
* struct max77759_maxq_response - structure containing the MaxQ response
*
* @length: The number of bytes to receive.
* @rsp: The data received. Must have at least @length bytes space.
*/
struct max77759_maxq_response {
u8 length;
u8 rsp[] __counted_by(length);
};
/**
* max77759_maxq_command() - issue a MaxQ command and wait for the response
* and associated data
*
* @max77759: The core max77759 device handle.
* @cmd: The command to be sent.
* @rsp: Any response data associated with the command will be copied here;
* can be %NULL if the command has no response (other than ACK).
*
* Return: 0 on success, a negative error number otherwise.
*/
int max77759_maxq_command(struct max77759 *max77759,
const struct max77759_maxq_command *cmd,
struct max77759_maxq_response *rsp);
#endif /* __LINUX_MFD_MAX77759_H */
local/recipes/gpu/amdgpu-source/include/linux/mfd/max77843-private.h
+435
View File
@@ -0,0 +1,435 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Common variables for the Maxim MAX77843 driver
*
* Copyright (C) 2015 Samsung Electronics
* Author: Jaewon Kim <jaewon02.kim@samsung.com>
* Author: Beomho Seo <beomho.seo@samsung.com>
*/
#ifndef __MAX77843_PRIVATE_H_
#define __MAX77843_PRIVATE_H_
#include <linux/i2c.h>
#include <linux/regmap.h>
#define I2C_ADDR_TOPSYS (0xCC >> 1)
#define I2C_ADDR_CHG (0xD2 >> 1)
#define I2C_ADDR_FG (0x6C >> 1)
#define I2C_ADDR_MUIC (0x4A >> 1)
/* Topsys, Haptic and LED registers */
enum max77843_sys_reg {
MAX77843_SYS_REG_PMICID = 0x00,
MAX77843_SYS_REG_PMICREV = 0x01,
MAX77843_SYS_REG_MAINCTRL1 = 0x02,
MAX77843_SYS_REG_INTSRC = 0x22,
MAX77843_SYS_REG_INTSRCMASK = 0x23,
MAX77843_SYS_REG_SYSINTSRC = 0x24,
MAX77843_SYS_REG_SYSINTMASK = 0x26,
MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
MAX77843_SYS_REG_END,
};
enum max77843_haptic_reg {
MAX77843_HAP_REG_MCONFIG = 0x10,
MAX77843_HAP_REG_END,
};
enum max77843_led_reg {
MAX77843_LED_REG_LEDEN = 0x30,
MAX77843_LED_REG_LED0BRT = 0x31,
MAX77843_LED_REG_LED1BRT = 0x32,
MAX77843_LED_REG_LED2BRT = 0x33,
MAX77843_LED_REG_LED3BRT = 0x34,
MAX77843_LED_REG_LEDBLNK = 0x38,
MAX77843_LED_REG_LEDRAMP = 0x36,
MAX77843_LED_REG_END,
};
/* Charger registers */
enum max77843_charger_reg {
MAX77843_CHG_REG_CHG_INT = 0xB0,
MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
MAX77843_CHG_REG_END,
};
/* Fuel gauge registers */
enum max77843_fuelgauge {
MAX77843_FG_REG_STATUS = 0x00,
MAX77843_FG_REG_VALRT_TH = 0x01,
MAX77843_FG_REG_TALRT_TH = 0x02,
MAX77843_FG_REG_SALRT_TH = 0x03,
MAX77843_FG_RATE_AT_RATE = 0x04,
MAX77843_FG_REG_REMCAP_REP = 0x05,
MAX77843_FG_REG_SOCREP = 0x06,
MAX77843_FG_REG_AGE = 0x07,
MAX77843_FG_REG_TEMP = 0x08,
MAX77843_FG_REG_VCELL = 0x09,
MAX77843_FG_REG_CURRENT = 0x0A,
MAX77843_FG_REG_AVG_CURRENT = 0x0B,
MAX77843_FG_REG_SOCMIX = 0x0D,
MAX77843_FG_REG_SOCAV = 0x0E,
MAX77843_FG_REG_REMCAP_MIX = 0x0F,
MAX77843_FG_REG_FULLCAP = 0x10,
MAX77843_FG_REG_AVG_TEMP = 0x16,
MAX77843_FG_REG_CYCLES = 0x17,
MAX77843_FG_REG_AVG_VCELL = 0x19,
MAX77843_FG_REG_CONFIG = 0x1D,
MAX77843_FG_REG_REMCAP_AV = 0x1F,
MAX77843_FG_REG_FULLCAP_NOM = 0x23,
MAX77843_FG_REG_MISCCFG = 0x2B,
MAX77843_FG_REG_RCOMP = 0x38,
MAX77843_FG_REG_FSTAT = 0x3D,
MAX77843_FG_REG_DQACC = 0x45,
MAX77843_FG_REG_DPACC = 0x46,
MAX77843_FG_REG_OCV = 0xEE,
MAX77843_FG_REG_VFOCV = 0xFB,
MAX77843_FG_SOCVF = 0xFF,
MAX77843_FG_END,
};
/* MUIC registers */
enum max77843_muic_reg {
MAX77843_MUIC_REG_ID = 0x00,
MAX77843_MUIC_REG_INT1 = 0x01,
MAX77843_MUIC_REG_INT2 = 0x02,
MAX77843_MUIC_REG_INT3 = 0x03,
MAX77843_MUIC_REG_STATUS1 = 0x04,
MAX77843_MUIC_REG_STATUS2 = 0x05,
MAX77843_MUIC_REG_STATUS3 = 0x06,
MAX77843_MUIC_REG_INTMASK1 = 0x07,
MAX77843_MUIC_REG_INTMASK2 = 0x08,
MAX77843_MUIC_REG_INTMASK3 = 0x09,
MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
MAX77843_MUIC_REG_CONTROL1 = 0x0C,
MAX77843_MUIC_REG_CONTROL2 = 0x0D,
MAX77843_MUIC_REG_CONTROL3 = 0x0E,
MAX77843_MUIC_REG_CONTROL4 = 0x16,
MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
MAX77843_MUIC_REG_END,
};
enum max77843_irq {
/* Topsys: SYSTEM */
MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
/* Charger: CHG_INT */
MAX77843_CHG_IRQ_CHG_INT_BYP_I,
MAX77843_CHG_IRQ_CHG_INT_BATP_I,
MAX77843_CHG_IRQ_CHG_INT_BAT_I,
MAX77843_CHG_IRQ_CHG_INT_CHG_I,
MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
MAX77843_CHG_IRQ_CHG_INT_AICL_I,
MAX77843_IRQ_NUM,
};
enum max77843_irq_muic {
/* MUIC: INT1 */
MAX77843_MUIC_IRQ_INT1_ADC,
MAX77843_MUIC_IRQ_INT1_ADCERROR,
MAX77843_MUIC_IRQ_INT1_ADC1K,
/* MUIC: INT2 */
MAX77843_MUIC_IRQ_INT2_CHGTYP,
MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
MAX77843_MUIC_IRQ_INT2_DCDTMR,
MAX77843_MUIC_IRQ_INT2_DXOVP,
MAX77843_MUIC_IRQ_INT2_VBVOLT,
/* MUIC: INT3 */
MAX77843_MUIC_IRQ_INT3_VBADC,
MAX77843_MUIC_IRQ_INT3_VDNMON,
MAX77843_MUIC_IRQ_INT3_DNRES,
MAX77843_MUIC_IRQ_INT3_MPNACK,
MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
MAX77843_MUIC_IRQ_INT3_MRXTRF,
MAX77843_MUIC_IRQ_INT3_MRXPERR,
MAX77843_MUIC_IRQ_INT3_MRXRDY,
MAX77843_MUIC_IRQ_NUM,
};
/* MAX77843 interrupts */
#define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
#define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
#define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
#define MAX77843_SYS_IRQ_TM_INT BIT(3)
/* MAX77843 MAINCTRL1 register */
#define MAINCTRL1_BIASEN_SHIFT 7
#define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
/* MAX77843 MCONFIG register */
#define MCONFIG_MODE_SHIFT 7
#define MCONFIG_MEN_SHIFT 6
#define MCONFIG_PDIV_SHIFT 0
#define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
#define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
#define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
/* Max77843 charger interrupts */
#define MAX77843_CHG_BYP_I BIT(0)
#define MAX77843_CHG_BATP_I BIT(2)
#define MAX77843_CHG_BAT_I BIT(3)
#define MAX77843_CHG_CHG_I BIT(4)
#define MAX77843_CHG_WCIN_I BIT(5)
#define MAX77843_CHG_CHGIN_I BIT(6)
#define MAX77843_CHG_AICL_I BIT(7)
/* MAX77843 CHG_INT_OK register */
#define MAX77843_CHG_BYP_OK BIT(0)
#define MAX77843_CHG_BATP_OK BIT(2)
#define MAX77843_CHG_BAT_OK BIT(3)
#define MAX77843_CHG_CHG_OK BIT(4)
#define MAX77843_CHG_WCIN_OK BIT(5)
#define MAX77843_CHG_CHGIN_OK BIT(6)
#define MAX77843_CHG_AICL_OK BIT(7)
/* MAX77843 CHG_DETAILS_00 register */
#define MAX77843_CHG_BAT_DTLS BIT(0)
/* MAX77843 CHG_DETAILS_01 register */
#define MAX77843_CHG_DTLS_MASK 0x0f
#define MAX77843_CHG_PQ_MODE 0x00
#define MAX77843_CHG_CC_MODE 0x01
#define MAX77843_CHG_CV_MODE 0x02
#define MAX77843_CHG_TO_MODE 0x03
#define MAX77843_CHG_DO_MODE 0x04
#define MAX77843_CHG_HT_MODE 0x05
#define MAX77843_CHG_TF_MODE 0x06
#define MAX77843_CHG_TS_MODE 0x07
#define MAX77843_CHG_OFF_MODE 0x08
#define MAX77843_CHG_BAT_DTLS_MASK 0xf0
#define MAX77843_CHG_NO_BAT (0x00 << 4)
#define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
#define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
#define MAX77843_CHG_OK_BAT (0x03 << 4)
#define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
#define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
#define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
/* MAX77843 CHG_CNFG_00 register */
#define MAX77843_CHG_MODE_MASK 0x0f
#define MAX77843_CHG_DISABLE 0x00
#define MAX77843_CHG_ENABLE 0x05
#define MAX77843_CHG_MASK 0x01
#define MAX77843_CHG_OTG_MASK 0x02
#define MAX77843_CHG_BUCK_MASK 0x04
#define MAX77843_CHG_BOOST_MASK 0x08
/* MAX77843 CHG_CNFG_01 register */
#define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
#define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
#define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
/* MAX77843 CHG_CNFG_02 register */
#define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
#define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
#define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
#define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
#define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
#define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
#define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
/* MAX77843 CHG_CNFG_03 register */
#define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
#define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
#define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
#define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
/* MAX77843 CHG_CNFG_06 register */
#define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
#define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
/* MAX77843_CHG_CNFG_09_register */
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
#define MAX77843_MUIC_ADC BIT(0)
#define MAX77843_MUIC_ADCERROR BIT(2)
#define MAX77843_MUIC_ADC1K BIT(3)
#define MAX77843_MUIC_CHGTYP BIT(0)
#define MAX77843_MUIC_CHGDETRUN BIT(1)
#define MAX77843_MUIC_DCDTMR BIT(2)
#define MAX77843_MUIC_DXOVP BIT(3)
#define MAX77843_MUIC_VBVOLT BIT(4)
#define MAX77843_MUIC_VBADC BIT(0)
#define MAX77843_MUIC_VDNMON BIT(1)
#define MAX77843_MUIC_DNRES BIT(2)
#define MAX77843_MUIC_MPNACK BIT(3)
#define MAX77843_MUIC_MRXBUFOW BIT(4)
#define MAX77843_MUIC_MRXTRF BIT(5)
#define MAX77843_MUIC_MRXPERR BIT(6)
#define MAX77843_MUIC_MRXRDY BIT(7)
/* MAX77843 INTSRCMASK register */
#define MAX77843_INTSRCMASK_CHGR 0
#define MAX77843_INTSRCMASK_SYS 1
#define MAX77843_INTSRCMASK_FG 2
#define MAX77843_INTSRCMASK_MUIC 3
#define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
#define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
#define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
#define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
#define MAX77843_INTSRC_MASK_MASK \
(MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)
/* MAX77843 STATUS register*/
#define MAX77843_MUIC_STATUS1_ADC_SHIFT 0
#define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6
#define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7
#define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0
#define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3
#define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4
#define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5
#define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6
#define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0
#define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4
#define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5
#define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6
#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT)
#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT)
#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT)
#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT)
#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT)
#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT)
#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT)
#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT)
#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT)
#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT)
/* MAX77843 CONTROL register */
#define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0
#define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT 6
#define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7
#define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0
#define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1
#define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2
#define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5
#define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6
#define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7
#define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0
#define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0
#define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4
#define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5
#define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6
#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT)
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT)
#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT)
#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT)
#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT)
#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT)
#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT)
/* MAX77843 switch port */
#define COM_OPEN 0
#define COM_USB 1
#define COM_AUDIO 2
#define COM_UART 3
#define COM_AUX_USB 4
#define COM_AUX_UART 5
#define MAX77843_MUIC_CONTROL1_COM_SW \
((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
#define MAX77843_MUIC_CONTROL1_SW_OPEN \
((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_USB \
((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUDIO \
((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_UART \
((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_USB \
((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_UART \
((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_DISABLE 0
#define MAX77843_ENABLE 1
#define CONTROL4_AUTO_DISABLE \
((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
(MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
#define CONTROL4_AUTO_ENABLE \
((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
(MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
/* MAX77843 SAFEOUT LDO Control register */
#define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
#define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
#endif /* __MAX77843_H__ */

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