restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
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@@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MDIO I2C bridge
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*
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* Copyright (C) 2015 Russell King
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*/
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#ifndef MDIO_I2C_H
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#define MDIO_I2C_H
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struct device;
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struct i2c_adapter;
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struct mii_bus;
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enum mdio_i2c_proto {
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MDIO_I2C_NONE,
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MDIO_I2C_MARVELL_C22,
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MDIO_I2C_C45,
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MDIO_I2C_ROLLBALL,
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};
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struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c,
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enum mdio_i2c_proto protocol);
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#endif
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@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Driver for the MDIO interface of Microsemi network switches.
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*
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* Author: Colin Foster <colin.foster@in-advantage.com>
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* Copyright (C) 2021 Innovative Advantage
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*/
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#ifndef MDIO_MSCC_MIIM_H
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#define MDIO_MSCC_MIIM_H
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#include <linux/device.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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int mscc_miim_setup(struct device *device, struct mii_bus **bus,
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const char *name, struct regmap *mii_regmap,
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int status_offset, bool ignore_read_errors);
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#endif
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@@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS
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* within the MMIO-mapped area
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*
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* Copyright (C) 2023 Maxime Chevallier <maxime.chevallier@bootlin.com>
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*/
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#ifndef MDIO_REGMAP_H
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#define MDIO_REGMAP_H
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#include <linux/phy.h>
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struct device;
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struct regmap;
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struct mdio_regmap_config {
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struct device *parent;
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struct regmap *regmap;
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char name[MII_BUS_ID_SIZE];
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u8 valid_addr;
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bool autoscan;
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};
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struct mii_bus *devm_mdio_regmap_register(struct device *dev,
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const struct mdio_regmap_config *config);
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#endif
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@@ -0,0 +1,134 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Applied Micro X-Gene SoC MDIO Driver
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*
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* Copyright (c) 2016, Applied Micro Circuits Corporation
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* Author: Iyappan Subramanian <isubramanian@apm.com>
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*/
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#ifndef __MDIO_XGENE_H__
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#define __MDIO_XGENE_H__
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#include <linux/bits.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
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#define BLOCK_DIAG_CSR_OFFSET 0xd000
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#define XGENET_CONFIG_REG_ADDR 0x20
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#define MAC_ADDR_REG_OFFSET 0x00
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#define MAC_COMMAND_REG_OFFSET 0x04
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#define MAC_WRITE_REG_OFFSET 0x08
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#define MAC_READ_REG_OFFSET 0x0c
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#define MAC_COMMAND_DONE_REG_OFFSET 0x10
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#define CLKEN_OFFSET 0x08
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#define SRST_OFFSET 0x00
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#define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
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#define MENET_BLOCK_MEM_RDY_ADDR 0x74
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#define MAC_CONFIG_1_ADDR 0x00
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define SOFT_RESET BIT(31)
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#define MII_MGMT_CONFIG_ADDR 0x20
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define MIIM_COMMAND_ADDR 0x20
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#define MIIM_FIELD_ADDR 0x24
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#define MIIM_CONFIGURATION_ADDR 0x28
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#define MIIM_LINKFAILVECTOR_ADDR 0x2c
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#define MIIM_INDICATOR_ADDR 0x30
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#define MIIMRD_FIELD_ADDR 0x34
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#define MDIO_CSR_OFFSET 0x5000
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#define REG_ADDR_POS 0
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#define REG_ADDR_LEN 5
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#define PHY_ADDR_POS 8
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#define PHY_ADDR_LEN 5
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#define HSTMIIMWRDAT_POS 0
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#define HSTMIIMWRDAT_LEN 16
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#define HSTPHYADX_POS 23
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#define HSTPHYADX_LEN 5
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#define HSTREGADX_POS 18
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#define HSTREGADX_LEN 5
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#define HSTLDCMD BIT(3)
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#define HSTMIIMCMD_POS 0
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#define HSTMIIMCMD_LEN 3
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#define BUSY_MASK BIT(0)
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#define READ_CYCLE_MASK BIT(0)
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enum xgene_enet_cmd {
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XGENE_ENET_WR_CMD = BIT(31),
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XGENE_ENET_RD_CMD = BIT(30)
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};
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enum {
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MIIM_CMD_IDLE,
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MIIM_CMD_LEGACY_WRITE,
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MIIM_CMD_LEGACY_READ,
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};
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enum xgene_mdio_id {
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XGENE_MDIO_RGMII = 1,
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XGENE_MDIO_XFI
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};
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struct xgene_mdio_pdata {
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struct clk *clk;
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struct device *dev;
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void __iomem *mac_csr_addr;
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void __iomem *diag_csr_addr;
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void __iomem *mdio_csr_addr;
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struct mii_bus *mdio_bus;
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int mdio_id;
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spinlock_t mac_lock; /* mac lock */
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};
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/* Set the specified value into a bit-field defined by its starting position
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* and length within a single u64.
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*/
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static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
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{
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return (val & ((1ULL << len) - 1)) << pos;
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}
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#define SET_VAL(field, val) \
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xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
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#define SET_BIT(field) \
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xgene_enet_set_field_value(field ## _POS, 1, 1)
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/* Get the value from a bit-field defined by its starting position
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* and length within the specified u64.
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*/
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static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
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{
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return (src >> pos) & ((1ULL << len) - 1);
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}
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#define GET_VAL(field, src) \
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xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
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#define GET_BIT(field, src) \
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xgene_enet_get_field_value(field ## _POS, 1, src)
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u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr);
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void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data);
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int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg);
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int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data);
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struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr);
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#endif /* __MDIO_XGENE_H__ */
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