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restore lost packages from 0.2.3 + fix overwritten 0.2.4 files

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- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.)
- Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber)
- Restore 20+ local/scripts (audit, lint, test, build helpers)
- Restore src/cook/scheduler.rs, status.rs, gnu-config/
- Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh
- Recover TLC source from HEAD (was overwritten by 0.2.3 checkout)
- Recover 11 local/docs plans from HEAD (were overwritten)
- Recover qt6-wayland-smoke symlink from HEAD
- Fix MOTD: remove garbled ASCII art, use clean text
- Update version: 0.2.0 -> 0.2.4 in os-release, motd, config
- Reduce filesystem_size: 1536 -> 512 MiB
- Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages
- Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
vasilito
2026-06-19 12:39:14 +03:00
parent ffbe098ef8
commit dc68054305
6418 changed files with 7066233 additions and 8670 deletions
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local/recipes/gpu/amdgpu-source/include/linux/generic_pt/common.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES
*/
#ifndef __GENERIC_PT_COMMON_H
#define __GENERIC_PT_COMMON_H
#include <linux/types.h>
#include <linux/build_bug.h>
#include <linux/bits.h>
/**
* DOC: Generic Radix Page Table
*
* Generic Radix Page Table is a set of functions and helpers to efficiently
* parse radix style page tables typically seen in HW implementations. The
* interface is built to deliver similar code generation as the mm's pte/pmd/etc
* system by fully inlining the exact code required to handle each table level.
*
* Like the mm subsystem each format contributes its parsing implementation
* under common names and the common code implements the required algorithms.
*
* The system is divided into three logical levels:
*
* - The page table format and its manipulation functions
* - Generic helpers to give a consistent API regardless of underlying format
* - An algorithm implementation (e.g. IOMMU/DRM/KVM/MM)
*
* Multiple implementations are supported. The intention is to have the generic
* format code be re-usable for whatever specialized implementation is required.
* The generic code is solely about the format of the radix tree; it does not
* include memory allocation or higher level decisions that are left for the
* implementation.
*
* The generic framework supports a superset of functions across many HW
* implementations:
*
* - Entries comprised of contiguous blocks of IO PTEs for larger page sizes
* - Multi-level tables, up to 6 levels. Runtime selected top level
* - Runtime variable table level size (ARM's concatenated tables)
* - Expandable top level allowing dynamic sizing of table levels
* - Optional leaf entries at any level
* - 32-bit/64-bit virtual and output addresses, using every address bit
* - Dirty tracking
* - Sign extended addressing
*/
/**
* struct pt_common - struct for all page table implementations
*/
struct pt_common {
/**
* @top_of_table: Encodes the table top pointer and the top level in a
* single value. Must use READ_ONCE/WRITE_ONCE to access it. The lower
* bits of the aligned table pointer are used for the level.
*/
uintptr_t top_of_table;
/**
* @max_oasz_lg2: Maximum number of bits the OA can contain. Upper bits
* must be zero. This may be less than what the page table format
* supports, but must not be more.
*/
u8 max_oasz_lg2;
/**
* @max_vasz_lg2: Maximum number of bits the VA can contain. Upper bits
* are 0 or 1 depending on pt_full_va_prefix(). This may be less than
* what the page table format supports, but must not be more. When
* PT_FEAT_DYNAMIC_TOP is set this reflects the maximum VA capability.
*/
u8 max_vasz_lg2;
/**
* @features: Bitmap of `enum pt_features`
*/
unsigned int features;
};
/* Encoding parameters for top_of_table */
enum {
PT_TOP_LEVEL_BITS = 3,
PT_TOP_LEVEL_MASK = GENMASK(PT_TOP_LEVEL_BITS - 1, 0),
};
/**
* enum pt_features - Features turned on in the table. Each symbol is a bit
* position.
*/
enum pt_features {
/**
* @PT_FEAT_DMA_INCOHERENT: Cache flush page table memory before
* assuming the HW can read it. Otherwise a SMP release is sufficient
* for HW to read it.
*/
PT_FEAT_DMA_INCOHERENT,
/**
* @PT_FEAT_FULL_VA: The table can span the full VA range from 0 to
* PT_VADDR_MAX.
*/
PT_FEAT_FULL_VA,
/**
* @PT_FEAT_DYNAMIC_TOP: The table's top level can be increased
* dynamically during map. This requires HW support for atomically
* setting both the table top pointer and the starting table level.
*/
PT_FEAT_DYNAMIC_TOP,
/**
* @PT_FEAT_SIGN_EXTEND: The top most bit of the valid VA range sign
* extends up to the full pt_vaddr_t. This divides the page table into
* three VA ranges::
*
* 0 -> 2^N - 1 Lower
* 2^N -> (MAX - 2^N - 1) Non-Canonical
* MAX - 2^N -> MAX Upper
*
* In this mode pt_common::max_vasz_lg2 includes the sign bit and the
* upper bits that don't fall within the translation are just validated.
*
* If not set there is no sign extension and valid VA goes from 0 to 2^N
* - 1.
*/
PT_FEAT_SIGN_EXTEND,
/**
* @PT_FEAT_FLUSH_RANGE: IOTLB maintenance is done by flushing IOVA
* ranges which will clean out any walk cache or any IOPTE fully
* contained by the range. The optimization objective is to minimize the
* number of flushes even if ranges include IOVA gaps that do not need
* to be flushed.
*/
PT_FEAT_FLUSH_RANGE,
/**
* @PT_FEAT_FLUSH_RANGE_NO_GAPS: Like PT_FEAT_FLUSH_RANGE except that
* the optimization objective is to only flush IOVA that has been
* changed. This mode is suitable for cases like hypervisor shadowing
* where flushing unchanged ranges may cause the hypervisor to reparse
* significant amount of page table.
*/
PT_FEAT_FLUSH_RANGE_NO_GAPS,
/* private: */
PT_FEAT_FMT_START,
};
struct pt_amdv1 {
struct pt_common common;
};
enum {
/*
* The memory backing the tables is encrypted. Use __sme_set() to adjust
* the page table pointers in the tree. This only works with
* CONFIG_AMD_MEM_ENCRYPT.
*/
PT_FEAT_AMDV1_ENCRYPT_TABLES = PT_FEAT_FMT_START,
/*
* The PTEs are set to prevent cache incoherent traffic, such as PCI no
* snoop. This is set either at creation time or before the first map
* operation.
*/
PT_FEAT_AMDV1_FORCE_COHERENCE,
};
struct pt_vtdss {
struct pt_common common;
};
enum {
/*
* The PTEs are set to prevent cache incoherent traffic, such as PCI no
* snoop. This is set either at creation time or before the first map
* operation.
*/
PT_FEAT_VTDSS_FORCE_COHERENCE = PT_FEAT_FMT_START,
/*
* Prevent creating read-only PTEs. Used to work around HW errata
* ERRATA_772415_SPR17.
*/
PT_FEAT_VTDSS_FORCE_WRITEABLE,
};
struct pt_riscv_32 {
struct pt_common common;
};
struct pt_riscv_64 {
struct pt_common common;
};
enum {
/*
* Support the 64k contiguous page size following the Svnapot extension.
*/
PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
};
struct pt_x86_64 {
struct pt_common common;
};
enum {
/*
* The memory backing the tables is encrypted. Use __sme_set() to adjust
* the page table pointers in the tree. This only works with
* CONFIG_AMD_MEM_ENCRYPT.
*/
PT_FEAT_X86_64_AMD_ENCRYPT_TABLES = PT_FEAT_FMT_START,
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/generic_pt/iommu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES
*/
#ifndef __GENERIC_PT_IOMMU_H
#define __GENERIC_PT_IOMMU_H
#include <linux/generic_pt/common.h>
#include <linux/iommu.h>
#include <linux/mm_types.h>
struct iommu_iotlb_gather;
struct pt_iommu_ops;
struct pt_iommu_driver_ops;
struct iommu_dirty_bitmap;
/**
* DOC: IOMMU Radix Page Table
*
* The IOMMU implementation of the Generic Page Table provides an ops struct
* that is useful to go with an iommu_domain to serve the DMA API, IOMMUFD and
* the generic map/unmap interface.
*
* This interface uses a caller provided locking approach. The caller must have
* a VA range lock concept that prevents concurrent threads from calling ops on
* the same VA. Generally the range lock must be at least as large as a single
* map call.
*/
/**
* struct pt_iommu - Base structure for IOMMU page tables
*
* The format-specific struct will include this as the first member.
*/
struct pt_iommu {
/**
* @domain: The core IOMMU domain. The driver should use a union to
* overlay this memory with its previously existing domain struct to
* create an alias.
*/
struct iommu_domain domain;
/**
* @ops: Function pointers to access the API
*/
const struct pt_iommu_ops *ops;
/**
* @driver_ops: Function pointers provided by the HW driver to help
* manage HW details like caches.
*/
const struct pt_iommu_driver_ops *driver_ops;
/**
* @nid: Node ID to use for table memory allocations. The IOMMU driver
* may want to set the NID to the device's NID, if there are multiple
* table walkers.
*/
int nid;
/**
* @iommu_device: Device pointer used for any DMA cache flushing when
* PT_FEAT_DMA_INCOHERENT. This is the iommu device that created the
* page table which must have dma ops that perform cache flushing.
*/
struct device *iommu_device;
};
static inline struct pt_iommu *iommupt_from_domain(struct iommu_domain *domain)
{
if (!IS_ENABLED(CONFIG_IOMMU_PT) || !domain->is_iommupt)
return NULL;
return container_of(domain, struct pt_iommu, domain);
}
/**
* struct pt_iommu_info - Details about the IOMMU page table
*
* Returned from pt_iommu_ops->get_info()
*/
struct pt_iommu_info {
/**
* @pgsize_bitmap: A bitmask where each set bit indicates
* a page size that can be natively stored in the page table.
*/
u64 pgsize_bitmap;
};
struct pt_iommu_ops {
/**
* @map_range: Install translation for an IOVA range
* @iommu_table: Table to manipulate
* @iova: IO virtual address to start
* @paddr: Physical/Output address to start
* @len: Length of the range starting from @iova
* @prot: A bitmap of IOMMU_READ/WRITE/CACHE/NOEXEC/MMIO
* @gfp: GFP flags for any memory allocations
*
* The range starting at IOVA will have paddr installed into it. The
* rage is automatically segmented into optimally sized table entries,
* and can have any valid alignment.
*
* On error the caller will probably want to invoke unmap on the range
* from iova up to the amount indicated by @mapped to return the table
* back to an unchanged state.
*
* Context: The caller must hold a write range lock that includes
* the whole range.
*
* Returns: -ERRNO on failure, 0 on success. The number of bytes of VA
* that were mapped are added to @mapped, @mapped is not zerod first.
*/
int (*map_range)(struct pt_iommu *iommu_table, dma_addr_t iova,
phys_addr_t paddr, dma_addr_t len, unsigned int prot,
gfp_t gfp, size_t *mapped);
/**
* @unmap_range: Make a range of IOVA empty/not present
* @iommu_table: Table to manipulate
* @iova: IO virtual address to start
* @len: Length of the range starting from @iova
* @iotlb_gather: Gather struct that must be flushed on return
*
* unmap_range() will remove a translation created by map_range(). It
* cannot subdivide a mapping created by map_range(), so it should be
* called with IOVA ranges that match those passed to map_pages. The
* IOVA range can aggregate contiguous map_range() calls so long as no
* individual range is split.
*
* Context: The caller must hold a write range lock that includes
* the whole range.
*
* Returns: Number of bytes of VA unmapped. iova + res will be the
* point unmapping stopped.
*/
size_t (*unmap_range)(struct pt_iommu *iommu_table, dma_addr_t iova,
dma_addr_t len,
struct iommu_iotlb_gather *iotlb_gather);
/**
* @set_dirty: Make the iova write dirty
* @iommu_table: Table to manipulate
* @iova: IO virtual address to start
*
* This is only used by iommufd testing. It makes the iova dirty so that
* read_and_clear_dirty() will see it as dirty. Unlike all the other ops
* this one is safe to call without holding any locking. It may return
* -EAGAIN if there is a race.
*/
int (*set_dirty)(struct pt_iommu *iommu_table, dma_addr_t iova);
/**
* @get_info: Return the pt_iommu_info structure
* @iommu_table: Table to query
*
* Return some basic static information about the page table.
*/
void (*get_info)(struct pt_iommu *iommu_table,
struct pt_iommu_info *info);
/**
* @deinit: Undo a format specific init operation
* @iommu_table: Table to destroy
*
* Release all of the memory. The caller must have already removed the
* table from all HW access and all caches.
*/
void (*deinit)(struct pt_iommu *iommu_table);
};
/**
* struct pt_iommu_driver_ops - HW IOTLB cache flushing operations
*
* The IOMMU driver should implement these using container_of(iommu_table) to
* get to it's iommu_domain derived structure. All ops can be called in atomic
* contexts as they are buried under DMA API calls.
*/
struct pt_iommu_driver_ops {
/**
* @change_top: Update the top of table pointer
* @iommu_table: Table to operate on
* @top_paddr: New CPU physical address of the top pointer
* @top_level: IOMMU PT level of the new top
*
* Called under the get_top_lock() spinlock. The driver must update all
* HW references to this domain with a new top address and
* configuration. On return mappings placed in the new top must be
* reachable by the HW.
*
* top_level encodes the level in IOMMU PT format, level 0 is the
* smallest page size increasing from there. This has to be translated
* to any HW specific format. During this call the new top will not be
* visible to any other API.
*
* This op is only used by PT_FEAT_DYNAMIC_TOP, and is required if
* enabled.
*/
void (*change_top)(struct pt_iommu *iommu_table, phys_addr_t top_paddr,
unsigned int top_level);
/**
* @get_top_lock: lock to hold when changing the table top
* @iommu_table: Table to operate on
*
* Return a lock to hold when changing the table top page table from
* being stored in HW. The lock will be held prior to calling
* change_top() and released once the top is fully visible.
*
* Typically this would be a lock that protects the iommu_domain's
* attachment list.
*
* This op is only used by PT_FEAT_DYNAMIC_TOP, and is required if
* enabled.
*/
spinlock_t *(*get_top_lock)(struct pt_iommu *iommu_table);
};
static inline void pt_iommu_deinit(struct pt_iommu *iommu_table)
{
/*
* It is safe to call pt_iommu_deinit() before an init, or if init
* fails. The ops pointer will only become non-NULL if deinit needs to be
* run.
*/
if (iommu_table->ops)
iommu_table->ops->deinit(iommu_table);
}
/**
* struct pt_iommu_cfg - Common configuration values for all formats
*/
struct pt_iommu_cfg {
/**
* @features: Features required. Only these features will be turned on.
* The feature list should reflect what the IOMMU HW is capable of.
*/
unsigned int features;
/**
* @hw_max_vasz_lg2: Maximum VA the IOMMU HW can support. This will
* imply the top level of the table.
*/
u8 hw_max_vasz_lg2;
/**
* @hw_max_oasz_lg2: Maximum OA the IOMMU HW can support. The format
* might select a lower maximum OA.
*/
u8 hw_max_oasz_lg2;
};
/* Generate the exported function signatures from iommu_pt.h */
#define IOMMU_PROTOTYPES(fmt) \
phys_addr_t pt_iommu_##fmt##_iova_to_phys(struct iommu_domain *domain, \
dma_addr_t iova); \
int pt_iommu_##fmt##_read_and_clear_dirty( \
struct iommu_domain *domain, unsigned long iova, size_t size, \
unsigned long flags, struct iommu_dirty_bitmap *dirty); \
int pt_iommu_##fmt##_init(struct pt_iommu_##fmt *table, \
const struct pt_iommu_##fmt##_cfg *cfg, \
gfp_t gfp); \
void pt_iommu_##fmt##_hw_info(struct pt_iommu_##fmt *table, \
struct pt_iommu_##fmt##_hw_info *info)
#define IOMMU_FORMAT(fmt, member) \
struct pt_iommu_##fmt { \
struct pt_iommu iommu; \
struct pt_##fmt member; \
}; \
IOMMU_PROTOTYPES(fmt)
/*
* A driver uses IOMMU_PT_DOMAIN_OPS to populate the iommu_domain_ops for the
* iommu_pt
*/
#define IOMMU_PT_DOMAIN_OPS(fmt) \
.iova_to_phys = &pt_iommu_##fmt##_iova_to_phys
#define IOMMU_PT_DIRTY_OPS(fmt) \
.read_and_clear_dirty = &pt_iommu_##fmt##_read_and_clear_dirty
/*
* The driver should setup its domain struct like
* union {
* struct iommu_domain domain;
* struct pt_iommu_xxx xx;
* };
* PT_IOMMU_CHECK_DOMAIN(struct mock_iommu_domain, xx.iommu, domain);
*
* Which creates an alias between driver_domain.domain and
* driver_domain.xx.iommu.domain. This is to avoid a mass rename of existing
* driver_domain.domain users.
*/
#define PT_IOMMU_CHECK_DOMAIN(s, pt_iommu_memb, domain_memb) \
static_assert(offsetof(s, pt_iommu_memb.domain) == \
offsetof(s, domain_memb))
struct pt_iommu_amdv1_cfg {
struct pt_iommu_cfg common;
unsigned int starting_level;
};
struct pt_iommu_amdv1_hw_info {
u64 host_pt_root;
u8 mode;
};
IOMMU_FORMAT(amdv1, amdpt);
/* amdv1_mock is used by the iommufd selftest */
#define pt_iommu_amdv1_mock pt_iommu_amdv1
#define pt_iommu_amdv1_mock_cfg pt_iommu_amdv1_cfg
struct pt_iommu_amdv1_mock_hw_info;
IOMMU_PROTOTYPES(amdv1_mock);
struct pt_iommu_vtdss_cfg {
struct pt_iommu_cfg common;
/* 4 is a 57 bit 5 level table */
unsigned int top_level;
};
struct pt_iommu_vtdss_hw_info {
u64 ssptptr;
u8 aw;
};
IOMMU_FORMAT(vtdss, vtdss_pt);
struct pt_iommu_riscv_64_cfg {
struct pt_iommu_cfg common;
};
struct pt_iommu_riscv_64_hw_info {
u64 ppn;
u8 fsc_iosatp_mode;
};
IOMMU_FORMAT(riscv_64, riscv_64pt);
struct pt_iommu_x86_64_cfg {
struct pt_iommu_cfg common;
/* 4 is a 57 bit 5 level table */
unsigned int top_level;
};
struct pt_iommu_x86_64_hw_info {
u64 gcr3_pt;
u8 levels;
};
IOMMU_FORMAT(x86_64, x86_64_pt);
#undef IOMMU_PROTOTYPES
#undef IOMMU_FORMAT
#endif